NSC 54ABT377

54ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ’ABT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
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Features
n
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n Clock enable for address and data synchronization
applications
n
Eight edge-triggered D flip-flops
Buffered common clock
See ’ABT273 for master reset version
See ’ABT373 for transparent latch version
See ’ABT374 for TRI-STATE ® version
Output sink capability of 48 mA, source capability of
24 mA
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Non-destructive hot insertion capability
Disable time less than enable time to avoid bus
contention
Standard Microcircuit Drawing (SMD) 5962-9314801
Ordering Code:
Military
Package
Package Description
Number
54ABT377J-QML
J20A
20-Lead Ceramic Dual-In-Line
54ABT377W-QML
W20A
20-Lead Cerpack
54ABT377E-QML
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagram
Pin Assignment for LCC
Pin Assignment for
DIP and Cerpack
DS100216-11
DS100216-1
Pin
Names
D0–D7
Description
Data Inputs
CE
Clock Enable (Active LOW)
CP
Clock Pulse Input
Q0–Q7
Data Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100216
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54ABT377 Octal D-Type Flip-Flop with Clock Enable
July 1998
Truth Table
Mode Select-Function Table
Operating Mode
Inputs
Output
CE
Dn
Qn
Load “1”
I
h
H
Load “0”
I
I
L
Hold
h
X
No Change
H
X
No Change
CP
(Do Nothing)
X
H = HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
L = LOW Voltage Level
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
X = Immaterial
= LOW-to-HIGH Clock Transition
Logic Diagram
DS100216-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
DC Latchup Source Current
(Across Comm Operating Range)
Over Voltage Latchup
Storage Temperature
−65˚C to +150˚C
Ambient Temperature under Bias
−55˚C to +125˚C
Junction Temperature under Bias
Ceramic
−55˚C to +175˚C
VCC Pin Potential to
Ground Pin
−0.5V to +7.0V
Input Voltage (Note 2)
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
−0.5V to +4.75V
in the HIGH State
−0.5V to VCC
Current Applied to Output
in LOW State (Max)
Twice the rated IOL (mA)
−500 mA
VCC + 4.5V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Supply Voltage
Military
Minimum Input Edge Rate
Data Input
Enable Input
−55˚C to +125˚C
+4.5V to +5.5V
(∆V/∆t)
50 mV/ns
20 mV/ns
DC Electrical Characteristics
Symbol
Parameter
ABT377
Min
Typ
Units
VCC
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
Min
VOH
Output HIGH Voltage
V
Min
VOL
Output LOW Voltage
IIH
Input HIGH Current
2.0
54ABT
2.5
54ABT
2.0
V
54ABT
Recognized HIGH Signal
0.55
V
Min
5
µA
Max
7
µA
Max
−5
µA
Max
5
IBVI
Input HIGH Current
Conditions
Max
Recognized LOW Signal
IIN = −18 mA
IOH = −3 mA
IOH = −24 mA
IOL = 48 mA
VIN = 2.7V (Note 4)
VIN = VCC
VIN = 7.0V
Breakdown Test
IIL
Input LOW Current
−5
VID
Input Leakage Test
4.75
IOS
Output Short-Circuit Current
−100
ICEX
ICCH
VIN = 0.5V (Note 4)
VIN = 0.0V
IID = 1.9 µA
V
0.0
−275
mA
Max
All Other Pins Grounded
VOUT = 0.0V
Output High Leakage Current
50
µA
Max
VOUT = VCC
Power Supply Current
50
µA
Max
All Outputs HIGH
ICCL
Power Supply Current
30
mA
Max
ICCT
Maximum ICC/Input
1.5
mA
Max
All Outputs LOW
VI = VCC − 2.1V
Data Input VI = VCC − 2.1V
0.3
mA/
Max
Outputs Enabled
All Others at VCC or GND
ICCD
Dynamic ICC
No Load
MHz
Outputs Open (Note 3)
One bit Toggling, 50% Duty Cycle
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions
is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Note 3: For 8 bits toggling, ICCD < 0.5 mA/MHz.
Note 4: Guaranteed but not tested.
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AC Electrical Characteristics
Symbol
Parameter
54ABT
TA = −55˚C to +125˚C
VCC = 4.5V to 5.5V
Units
CL = 50 pF
Min
fmax
Max Clock
Max
150
MHz
Frequency
tPLH
Propagation Delay
2.2
6.0
tPHL
CP to On
2.8
6.8
ns
AC Operating Requirements
Symbol
54ABT
TA = −55˚C to +125˚C
VCC = 4.5V to 5.5V
Parameter
Units
CL = 50 pF
Min
ts(H)
Setup Time, HIGH
2.0
ts(L)
or LOW Dn to CP
2.0
th(H)
Hold Time, HIGH
1.8
th(L)
or LOW Dn to CP
1.8
ts(H)
Setup Time, HIGH
3.0
ts(L)
or LOW CE to CP
3.0
th(H)
Hold Time, HIGH
1.0
th(L)
or LOW CE to CP
1.0
tw(H)
Pulse Width, CP,
3.3
tw(L)
HIGH or LOW
3.3
Max
ns
ns
ns
ns
ns
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
5
pF
COUT (Note 5)
Output Capacitance
9
pF
Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
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Conditions
VCC = 0V, TA = 25˚C
VCC = 5.0V
AC Loading
DS100216-4
*Includes jig and probe capacitance
DS100216-5
FIGURE 1. Standard AC Test Load
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100216-6
FIGURE 2. VM = 1.5V
DS100216-9
Input Pulse Requirements
FIGURE 6. Setup Time, Hold Time
and Recovery Time Waveforms
Amplitude
Rep. Rate
tw
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100216-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
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Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Ceramic Chip Carrier
NS Package Number E20A
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6
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Dual-In-Line Package
NS Package Number J20A
20-Lead Ceramic Flatpack
NS Package Number W20A
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54ABT377 Octal D-Type Flip-Flop with Clock Enable
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