54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’LS114 features individual J, K and set inputs and common clock and common clear inputs. When the clock goes HIGH the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the Clock Pulse is HIGH and the bistable will perform according to the truth table as long as the minimum setup times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. Connection Diagram Logic Symbol Dual-In-Line Package TL/F/10176 – 1 TL/F/10176 – 2 Order Number 54LS114DMQB, 54LS114FMQB or 54LS114LMQB See NS Package Number E20A, J14A or W14B C1995 National Semiconductor Corporation VCC e Pin 14 GND e Pin 7 Pin Names Description J1, J2, K1, K2 CP CD SD1, SD2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Input (Active Falling Edge) Direct Clear Input (Active LOW) Direct Set Inputs (Active LOW) Outputs TL/F/10176 RRD-B30M105/Printed in U. S. A. 54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. 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Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C 54LS b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol 54LS114 Parameter Units Min Nom Max 4.5 5 5.5 VCC Supply Voltage VIH High Level Input Voltage V VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current TA Free Air Operating Temperature ts (H) ts (L) Setup Time Jn or Kn to CP 20 20 ns th (H) th (L) Hold Time Jn or Kn to CP 0 0 ns tw (H) tw (L) CP Pulse Width 20 15 ns tw CD or SDn Pulse Width 15 ns 2 V b 55 0.7 V b 0.4 mA 4 mA 125 §C Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max, VIL e Max VOL Low Level Output Voltage VCC e Min, IOL e Max, VIH e Min 0.4 2.5 V V 0.5 II Input Current @ Max Input Voltage VCC e Max, VI e 10V; Jn, Kn Inputs SD1, SD2 Inputs CD Input CP Input 0.1 0.3 0.6 0.8 mA mA mA mA IIH High Level Input Current VCC e Max, VI e 2.7V; Jn, Kn Inputs SD1, SD2 Inputs CD Input CP Input 20 60 120 160 mA mA mA mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. 2 Electrical Characteristics (Continued) Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min IIL Low Level Input Current VCC e Max, VI e 0.4V Jn, Kn Inputs SD1, SD2 Inputs CD Input CP Input IOS Short Circuit Output Current VCC e Max (Note 2) ICC Supply Current VCC e Max, VCP e 0V Typ (Note 1) b 20 Max Units b 0.4 b 0.8 b 1.6 b 1.44 mA mA mA mA b 100 mA 8.0 mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol RL e 2k, CL e 15 pF Parameter Min Units Max fmax Maximum Count Frequency tPLH tPHL Propagation Delay CP to Q or Q 30 16 24 ns tPLH tPHL Propagation Delay CD or SDn to Q or Q 16 24 ns Truth Table Inputs @ J L L H H Output tn @ K L H L H tn a 1 Q Qn L H Qn Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH H e HIGH Voltage Level L e LOW Voltage Level tn e Bit time before clock pulse. tn a 1 e Bit time after clock pulse. 3 MHz Logic Diagram (one half shown) TL/F/10176 – 3 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier (E) Order Number 54LS114LMQB NS Package Number E20A 4 Physical Dimensions inches (millimeters) (Continued) 14-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS114DMQB NS Package Number J14A 5 54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears Physical Dimensions inches (millimeters) (Continued) 14-Lead Ceramic Flat Package (W) Order Number 54LS114FMQB NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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