NSC 54ACT258D

54AC258 • 54ACT258
Quad 2-Input Multiplexer with TRI-STATE ® Outputs
General Description
The ’AC/’ACT258 is a quad 2-input multiplexer with
TRI-STATE outputs. Four bits of data from two sources can
be selected using a common data select input. The four outputs present the selected data in the complement (inverted)
form. The outputs may be switched to a high impedance
state with a HIGH on the common Output Enable (OE) input,
allowing the outputs to interface directly with bus-oriented
systems.
n
n
n
n
n
Multiplexer expansion by tying outputs together
Inverting TRI-STATE outputs
Outputs source/sink 24 mA
’ACT258 has TTL-compatible inputs
Standard Military Drawing (SMD)
— ’ACT258: 5962-88704
— ’AC258: 5962-91604
Features
n ICC and IOZ reduced by 50%
Logic Symbols
IEEE/IEC
DS100287-1
DS100287-2
Pin Names
Description
S
Common Data Select Input
OE
TRI-STATE Output Enable Input
I0a–I0d
Data Inputs from Source 0
I1a–I1d
Data Inputs from Source 1
Za–Zd
TRI-STATE Inverting Data Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100287
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54AC258 • 54ACT258 Quad 2-Input Multiplexer with TRI-STATE Outputs
August 1998
Connection Diagrams
Functional Description
The ’AC/’ACT258 is a quad 2-input multiplexer with
TRI-STATE outputs. It selects four bits of data from two
sources under control of a common Select input (S). When
the Select input is LOW, the I0x inputs are selected and when
Select is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in inverted form. The
’AC/’ACT258 is the logic implementation of a 4-pole,
2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The
logic equations for the outputs are shown below:
Za = OE • (I1a • S + I0a • S)
Zb = OE • (I1b • S + I0b • S)
Zc = OE • (I1c • S + I0c • S)
Zd = OE • (I1d • S + I0d • S)
Pin Assignment
for DIP and Flatpak
When the Output Enable input (OE) is HIGH, the outputs are
forced to a high impedance state. If the outputs of the
TRI-STATE devices are tied together, all but one device must
be in the high impedance state to avoid high currents that
would exceed the maximum ratings. Designers should ensure that Output Enable signals to TRI-STATE devices
whose outputs are tied together are designed so there is no
overlap.
DS100287-3
Pin Assignment
for LCC
Truth Table
DS100287-4
Output
Select
Data
Enable
Input
Inputs
OE
S
I0
I1
H
X
X
X
Z
L
H
X
L
H
L
H
X
H
L
L
L
L
X
H
L
L
H
X
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
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2
Outputs
Z
Logic Diagram
DS100287-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
Supply Voltage (VCC)
’AC
’ACT
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
54AC/ACT
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
± 50 mA
± 50 mA
−65˚C to +150˚C
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
0V to VCC
−55˚C to +125˚C
125 mV/ns
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications.
175˚C
DC Characteristics for ’AC Family Devices
Symbol
VIH
VIL
VOH
Parameter
VCC
54AC
TA = −55˚C to +125˚C
(V)
Guaranteed Limits
Minimum High Level
3.0
2.1
Input Voltage
4.5
3.15
5.5
3.85
Maximum Low Level
3.0
0.9
Input Voltage
4.5
1.35
5.5
1.65
Minimum High Level
3.0
2.9
Output Voltage
4.5
4.4
5.5
5.4
Units
Conditions
VOUT = 0.1V
V
or VCC − 0.1V
V
or VCC − 0.1V
VOUT = 0.1V
IOUT = −50 µA
V
(Note 2)
VIN = VIL or VIH
VOL
3.0
2.4
4.5
3.7
5.5
4.7
Maximum Low Level
3.0
0.1
Output Voltage
4.5
0.1
5.5
0.1
IOH = −12 mA
V
IOH = −24 mA
IOH = −24 mA
IOUT = 50 µA
V
(Note 2)
VIN = VIL or VIH
IIN
Maximum Input
3.0
0.50
4.5
0.50
IOL = 12 mA
V
IOL = 24 mA
IOL = 24 mA
VI = VCC, GND
5.5
0.50
5.5
± 1.0
µA
5.5
± 5.0
µA
Leakage Current
IOZ
Maximum TRI-STATE
Current
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4
VI (OE) = VIL, VIH
VI = VCC, GND
VO = VCC, GND
DC Characteristics for ’AC Family Devices
Symbol
Parameter
(Continued)
VCC
54AC
TA = −55˚C to +125˚C
(V)
Guaranteed Limits
Units
Conditions
IOLD
Minimum Dynamic
5.5
50
mA
IOHD
Output Current (Note 3)
5.5
−50
mA
VOLD = 1.65V Max
VOHD = 3.85V Min
ICC
Maximum Quiescent
5.5
80.0
µA
VIN = VCC
Supply Current
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C.
DC Characteristics for ’ACT Family Devices
Symbol
VIH
VIL
VOH
Parameter
VCC
54ACT
TA = −55˚C to +125˚C
(V)
Guaranteed Limits
Minimum High Level
4.5
2.0
Input Voltage
5.5
2.0
Maximum Low Level
4.5
0.8
Input Voltage
5.5
0.8
Minimum High Level
4.5
4.4
Output Voltage
5.5
5.4
Units
Conditions
V
VOUT = 0.1V
V
or VCC − 0.1V
VOUT = 0.1V
V
or VCC − 0.1V
IOUT = −50 µA
(Note 5)
VIN = VIL or VIH
VOL
4.5
3.70
5.5
4.70
Maximum Low Level
4.5
0.1
Output Voltage
5.5
0.1
V
IOH = −24 mA
V
IOH = −24 mA
IOUT = 50 µA
(Note 5)
VIN = VIL or VIH
4.5
0.50
5.5
0.50
V
IOL = 24 mA
IOL = 24 mA
VI = VCC, GND
IIN
Maximum Input Leakage
Current
5.5
± 1.0
µA
IOZ
Maximum TRI-STATE
5.5
± 5.0
µA
Current
VI = VIL, VIH
VO = VCC, GND
VI = VCC − 2.1V
ICCT
Maximum ICC/Input
5.5
1.6
mA
IOLD
Minimum Dynamic
5.5
50
mA
IOHD
Output Current (Note 6)
5.5
−50
mA
VOLD = 1.65V Max
VOHD = 3.85V Min
ICC
Maximum Quiescent
5.5
80.0
µA
VIN = VCC
Supply Current
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C.
5
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AC Electrical Characteristics
54AC
TA = −55˚C
VCC
Symbol
Parameter
(V)
(Note 8)
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Fig.
to +125˚C
CL = 50 pF
Units
Min
Max
Propagation Delay
3.3
1.0
12.0
In to Zn
5.0
1.0
9.5
Propagation Delay
3.3
1.0
10.5
In to Zn
5.0
1.0
7.5
Propagation Delay
3.3
1.0
15.0
S to Zn
5.0
1.0
11.5
Propagation Delay
3.3
1.0
14.0
S to Zn
5.0
1.0
10.5
Output Enable Time
3.3
1.0
11.5
5.0
1.0
9.0
3.3
1.0
10.5
5.0
1.0
8.5
3.3
1.0
11.5
5.0
1.0
9.5
3.3
1.0
10.5
5.0
1.0
8.5
Output Enable Time
Output Disable Time
Output Disable Time
No.
ns
ns
ns
ns
ns
ns
ns
ns
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics
54ACT
TA = −55˚C
VCC
Symbol
Parameter
(V)
(Note 9)
tPLH
Propagation Delay
Fig.
to +125˚C
CL = 50 pF
Units
Min
Max
5.0
1.0
10.5
ns
5.0
1.0
9.0
ns
5.0
1.0
13.0
ns
5.0
1.0
12.0
ns
In to Zn
tPHL
Propagation Delay
In to Zn
tPLH
Propagation Delay
S to Zn
tPHL
Propagation Delay
S to Zn
tPZH
Output Enable Time
5.0
1.0
10.5
ns
tPZL
Output Enable Time
5.0
1.0
10.0
ns
tPHZ
Output Disable Time
5.0
1.0
10.5
ns
tPLZ
Output Disable Time
5.0
1.0
10.0
ns
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
CIN
CPD
Typ
Units
Input Capacitance
Parameter
4.5
pF
Power Dissipation
55.0
pF
Capacitance
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6
Conditions
VCC = OPEN
VCC = 5.0V
No.
Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
7
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54AC258 • 54ACT258 Quad 2-Input Multiplexer with TRI-STATE Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
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with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
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