Revised March 1999 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs (J, K, PRESET, CLEAR, and CLOCK) and outputs (Q, Q). These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. Clear and Preset are independent of the clock and are accomplished by a low logic level on the corresponding input. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. Features ■ Input voltage level translation from 5V–3V ■ Ideal for low power/low noise 3.3V applications Ordering Code: Order Number 74LVX112M 74LVX112SJ 74LVX112MTC Package Number M16A Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description J1, J2, K1, K2 Data Inputs CLK1, CLK2 Clock Pulse Inputs (Active Falling edge) CLR1, CLR2 Direct Clear Inputs (Active LOW) PR1, PR2 Direct Preset Inputs (Active LOW) Q1, Q2, Q1, Q2 © 1999 Fairchild Semiconductor Corporation DS012158.prf www.fairchildsemi.com 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear October 1996 74LVX112 Truth Table Inputs Outputs PR CLR CP J K Q Q L H X X X H L H L X X X L H L L X X X H H H H h h Q0 Q0 H H l h L H H H H H h l H L l l Q0 Q0 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial = HIGH-to-LOW Clock Transition Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram (One Half Shown) www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA −0.5V to 7V DC Input Voltage (VI) 2.0V to 3.6V Input Voltage (VI) 0V to 5.5V Output Voltage (VO) DC Output Diode Current (IOK) 0V to VCC −40°C to +85°C Operating Temperature (TA) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA Input Rise and Fall Time (∆t/∆v) −0.5V to VCC + 0.5V DC Output Voltage (VO) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC Output Source ±25 mA or Sink Current (IO) DC VCC or Ground Current ±50 mA (ICC or IGND) 0 ns/V to 100 ns/V Note 2: Unused inputs must be held HIGH or LOW. They may not float. −65°C to +150°C Storage Temperature (TSTG) Power Dissipation 180 mW DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter VCC TA = +25°C Min TA = −40°C to +85°C Typ Max Min HIGH Level 2.0 1.5 Input Voltage 3.0 2.0 2.0 3.6 2.4 2.4 Max Units Conditions 1.5 V LOW Level 2.0 0.5 Input Voltage 3.0 0.8 0.5 0.8 3.6 0.8 0.8 V VIN = VIL or VIH HIGH Level 2.0 1.9 2.0 1.9 Output Voltage 3.0 2.9 3.0 2.9 3.0 2.58 Low Level 2.0 0.0 0.1 0.1 Output Voltage 3.0 0.0 0.1 0.1 IOH = −50 µA IOH = −50 µA V IOH = −4 mA 2.48 VIN = VIL or VIH V IOL = 50 µA IOL = 50 µA IOL = 4 mA 3.0 0.36 0.44 IIN Input Leakage Current 3.6 ±0.1 ±1.0 µA VIN = 5.5V or GND ICC Quiescent Supply Current 3.6 2.0 20.0 µA VIN = VCC or GND 3 www.fairchildsemi.com 74LVX112 Absolute Maximum Ratings(Note 1) 74LVX112 AC Electrical Characteristics Symbol VCC (V) Parameter tPLH Propagation Delay tPHL CPn to Qn or Qn TA = +25°C Min 2.7 3.3 ± 0.3 tPLH Propagation Delay tPHL PR or CLR to Qn or Qn 2.7 3.3 ± 0.3 tW Pulse Width (CP or CLR or PR) tS Setup Time (Jn or Kn to CPn) tH Hold Time (Jn or Kn to CPn) tREC Recovery Time (CLR or PR to CP) fMAX Maximum Clock TA = −40°C to +85°C Typ Max Min Max 7.5 12.0 1.0 14.2 11.0 16.7 1.0 19.0 8.5 11.0 1.0 13.4 10.0 15.0 1.0 16.5 50 15 7.0 11.5 1.0 12.3 10.1 14.3 1.0 16.5 6.7 10.2 1.0 11.7 9.7 13.5 1.0 15.0 2.7 5.0 5.0 3.3 ± 0.3 5.0 5.0 2.7 5.5 5.5 3.3 ± 0.3 5.0 5.0 2.7 1.0 1.0 3.3 ± 0.3 1.0 1.0 2.7 6.5 6.5 3.3 ± 0.3 6.0 6.0 2.7 Frequency 3.3 ± 0.3 CL (pF) Units 15 50 ns 15 50 ns 15 50 ns ns ns ns 90 140 85 15 85 115 70 50 110 150 100 90 120 80 MHz 15 50 tOSLH, Output to Output Skew 2.7 1.5 1.5 tOSHL (Note 3) 3.3 1.5 1.5 50 ns Note 3: Parameter guaranteed by design. tOSLH = |tPLHm–tPLHn|, tOSLH = |tPHLm–tPHLn| Capacitance Symbol TA = +25°C Parameter Min TA = −40°C to +85°C Typ Max 10 CIN Input Capacitance 4 CPD Power Dissipation 18 Min 10 Capacitance (Note 4) Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. www.fairchildsemi.com 4 Units Max pF pF 74LVX112 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.