ETC 74VCX162373DTR

74VCX162373
Low-Voltage 1.8/2.5/3.3V
16-Bit Transparent Latch
With 26 Series Resisters and
3.6V–Tolerant Inputs and Outputs
(3–State, Non–Inverting)
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The 74VCX162373 is an advanced performance, non–inverting 16–bit
transparent latch. It is designed for very high–speed, very low–power
operation in 1.8 V, 2.5 V or 3.3 V systems. The VCX162373 is byte
controlled, with each byte functioning identically, but independently.
Each byte has separate Output Enable and Latch Enable inputs. These
control pins can be tied together for full 16–bit operation.
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing to
3.3 V busses. It is guaranteed to be over–voltage tolerant to 3.6 V.
The 74VCX162373 contains 16 D–type latches with 3–state 3.6
V–tolerant outputs. It is designed with 26 series resistors in each of the
outputs to reduce noise. When the Latch Enable (LEn) inputs are HIGH,
data on the Dn inputs enters the latches. In this condition, the latches are
transparent, (a latch output will change state each time its D input
changes). When LE is LOW, the latch stores the information that was
present on the D inputs a setup time preceding the HIGH–to–LOW
transition of LE. The 3–state outputs are controlled by the Output Enable
(OEn) inputs. When OE is LOW, the outputs are enabled. When OE is
HIGH, the standard outputs are in the high impedance state, but this does
not interfere with new data entering into the latches.
• Designed for Low Voltage Operation: VCC = 1.65–3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.3 ns max for 3.0 to 3.6 V
•
•
•
•
•
•
August, 2000 – Rev. 0
This Material Copyrighted by Its Respective Manufacturer
48
48
74VCX162373DT
1
AWLYYWW
TSSOP–48
DT SUFFIX
CASE 1201
A
WL
YY
WW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
4.5 ns max for 2.3 to 2.7 V
9.0 ns max for 1.65 to 1.95 V
Static Drive: ±12 mA Drive at 3.0 V
±8 mA Drive at 2.3 V
±3 mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
Near Zero Static Supply Current in All Three Logic States (20 µA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds ±300 mA @ 125°C
ESD Performance: Human Body Model >2000 V; Machine Model >200 V
 Semiconductor Components Industries, LLC, 2000
MARKING DIAGRAM
1
Package
Shipping
74VCX162373DT
TSSOP
39 / Rail
74VCX162373DTR
TSSOP
2500 / Reel
Publication Order Number:
74VCX162373/D
74VCX162373
OE1 1
48 LE1
O0 2
47 D0
O1 3
46 D1
GND 4
OE1
45 GND
O2 5
44 D2
O3 6
43 D3
VCC 7
O4 8
42 VCC
O5 9
40 D5
LE1
D0
D1
1
OE2
48
LE2
47
46
nLE
D
nLE
D
2
Q
3
Q
41 D4
GND 10
39 GND
O6 11
38 D6
O7 12
37 D7
O8 13
36 D8
O9 14
35 D9
GND 15
34 GND
O10 16
33 D10
O11 17
32 D11
VCC 18
31 VCC
O12 19
30 D12
O13 20
29 D13
GND 21
28 GND
O14 22
27 D14
O15 23
26 D15
OE2 24
25 LE2
D2
D3
D4
D5
D6
D7
44
43
41
40
38
37
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
5
Q
6
Q
8
Q
9
Q
11
Q
12
Q
1
OE1 48
LE1 25
LE2 24
OE2
PIN NAMES
Function
OEn
LEn
D0–D15
O0–O15
Output Enable Inputs
Latch Enable Inputs
Inputs
Outputs
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
O1
nLE
D
nLE
D
nLE
D
nLE
27
D14
O7
D
29
D13
O6
nLE
30
D12
O5
D
32
D11
O4
nLE
33
D10
O3
D
35
D9
O2
nLE
36
D8
D
nLE
26
D15
D
13
Q
14
Q
16
Q
17
Q
19
Q
20
Q
22
Q
23
Q
O8
O9
O10
O11
O12
O13
O14
O15
EN1
EN2
EN3
EN4
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
Outputs
Inputs
25
Figure 2. Logic Diagram
Figure 1. 48–Lead Pinout
(Top View)
Pins
O0
24
1
1∇
1
2∇
1
3∇
1
4∇
Inputs
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
Outputs
LE1
OE1
D0:7
O0:7
LE2
OE2
D8:15
O8:15
X
H
X
Z
X
H
X
Z
H
L
L
L
H
L
L
L
H
L
H
H
H
L
H
H
L
L
X
O0
L
L
X
O0
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions Are Acceptable, for
ICC reasons, DO NOT FLOAT Inputs. O0 = No Change.
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74VCX162373
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
VCC
DC Supply Voltage
VI
VO
Value
Condition
Unit
–0.5 to +4.6
V
DC Input Voltage
–0.5 ≤ VI ≤ +4.6
V
DC Output Voltage
–0.5 ≤ VO ≤ +4.6
Output in 3–State
V
–0.5 ≤ VO ≤ VCC + 0.5
Note 1.; Outputs Active
V
IIK
DC Input Diode Current
–50
VI < GND
mA
IOK
DC Output Diode Current
–50
VO < GND
mA
+50
VO > VCC
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
–65 to +150
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions
is not implied.
1. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Operating
Data Retention Only
Min
Typ
Max
Unit
1.65
1.2
3.3
3.3
3.6
3.6
V
–0.3
3.6
V
0
0
VCC
3.6
V
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH
HIGH Level Output Current, VCC = 3.0V – 3.6V
–12
mA
IOL
LOW Level Output Current, VCC = 3.0V – 3.6V
12
mA
IOH
HIGH Level Output Current, VCC = 2.3V – 2.7V
–8
mA
IOL
LOW Level Output Current, VCC = 2.3V – 2.7V
8
mA
IOH
HIGH Level Output Current, VCC = 1.65 – 1.95V
–3
mA
IOL
LOW Level Output Current, VCC = 1.65 – 1.95V
3
mA
TA
Operating Free–Air Temperature
–40
+85
°C
∆t/∆V
Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V, VCC = 3.0V
0
10
ns/V
(Active State)
(3–State)
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74VCX162373
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C
Symbol
VIH
VIL
VOH
VOL
Characteristic
HIGH Level Input Voltage (Note 2.)
LOW Level Input Voltage (Note 2.)
HIGH Level Output Voltage
LOW Level Output Voltage
Condition
Min
1.65V ≤ VCC < 2.3V
0.65 x VCC
2.3V ≤ VCC ≤ 2.7V
1.6
2.7V < VCC ≤ 3.6V
2.0
Max
V
1.65V ≤ VCC < 2.3V
0.35 x VCC
2.3V ≤ VCC ≤ 2.7V
0.7
2.7V < VCC ≤ 3.6V
0.8
1.65V ≤ VCC ≤ 3.6V; IOH = –100µA
VCC – 0.2
VCC = 1.65V; IOH = –3mA
1.25
VCC = 2.3V; IOH = –4mA
2.0
VCC = 2.3V; IOH = –6mA
1.8
VCC = 2.3V; IOH = –8mA
1.7
VCC = 2.7V; IOH = –6mA
2.2
VCC = 3.0V; IOH = –8mA
2.4
VCC = 3.0V; IOH = –12mA
2.2
Unit
V
V
1.65V ≤ VCC ≤ 3.6V; IOL = 100µA
0.2
VCC = 1.65V; IOL = 3mA
0.3
VCC = 2.3V; IOL = 6mA
0.4
VCC = 2.3V; IOL = 8mA
0.6
VCC = 2.7V; IOL = 6mA
0.4
VCC = 3.0V; IOL = 8mA
0.55
V
VCC = 3.0V; IOL = 12mA
0.8
II
Input Leakage Current
1.65V ≤ VCC ≤ 3.6V; 0V ≤ VI ≤ 3.6V
±5.0
µA
IOZ
3–State Output Current
1.65V ≤ VCC ≤ 3.6V; 0V ≤ VO ≤ 3.6V;
VI = VIH or VIL
±10
µA
IOFF
Power–Off Leakage Current
ICC
Quiescent Supply Current (Note 3.)
∆ICC
Increase in ICC per Input
VCC = 0V; VI or VO = 3.6V
10
µA
1.65V ≤ VCC ≤ 3.6V; VI = GND or VCC
20
µA
1.65V ≤ VCC ≤ 3.6V; 3.6V ≤ VI, VO ≤ 3.6V
±20
µA
2.7V < VCC ≤ 3.6V; VIH = VCC – 0.6V
750
µA
2. These values of VI are used to test DC electrical characteristics only.
3. Outputs disabled or 3–state only.
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74VCX162373
AC CHARACTERISTICS (Note 4.; tR = tF = 2.0ns; CL = 30pF; RL = 500Ω)
Limits
TA = –40°C to +85°C
VCC = 3.0V to 3.6V
Symbol
Parameter
VCC = 2.3V to 2.7V
VCC = 1.65 to 1.95V
Waveform
Min
Max
Min
Max
Min
Max
Unit
tPLH
tPHL
Propagation Delay
Dn to On
1
0.8
0.8
3.3
3.3
1.0
1.0
4.5
4.5
1.5
1.5
9.0
9.0
ns
tPLH
tPHL
Propagation Delay
LE to On
1
0.8
0.8
3.6
3.6
1.0
1.0
4.9
4.9
1.5
1.5
9.8
9.8
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
2
0.8
0.8
3.9
3.9
1.0
1.0
5.4
5.4
1.5
1.5
9.8
9.8
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2
0.8
0.8
4.0
4.0
1.0
1.0
4.4
4.4
1.5
1.5
7.9
7.9
ns
ts
Setup Time, High or Low Dn to LE
3
1.5
1.5
2.5
ns
th
Hold Time, High or Low Dn to LE
3
1.0
1.0
1.0
ns
tw
LE Pulse Width, High
3
1.5
1.5
4.0
ns
tOSHL
tOSLH
Output–to–Output Skew
(Note 5.)
0.5
0.5
0.5
0.5
0.75
0.75
ns
4. For CL = 50pF, add approximately 300ps to the AC maximum specification.
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter
guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
VOLP
VOLV
VOHV
Characteristic
Condition
Typ
Unit
Dynamic LOW Peak Voltage
VCC = 1.8V, CL = 30pF, VIH = VCC, VIL = 0V
0.15
V
(Note 6.)
VCC = 2.5V, CL = 30pF, VIH = VCC, VIL = 0V
0.25
VCC = 3.3V, CL = 30pF, VIH = VCC, VIL = 0V
0.35
Dynamic LOW Valley Voltage
VCC = 1.8V, CL = 30pF, VIH = VCC, VIL = 0V
–0.15
(Note 6.)
VCC = 2.5V, CL = 30pF, VIH = VCC, VIL = 0V
–0.25
VCC = 3.3V, CL = 30pF, VIH = VCC, VIL = 0V
–0.35
Dynamic HIGH Valley Voltage
VCC = 1.8V, CL = 30pF, VIH = VCC, VIL = 0V
1.55
(Note 7.)
VCC = 2.5V, CL = 30pF, VIH = VCC, VIL = 0V
2.05
VCC = 3.3V, CL = 30pF, VIH = VCC, VIL = 0V
2.65
V
V
6. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is
measured in the LOW state.
7. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is
measured in the HIGH state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
Unit
CIN
Input Capacitance
Note 8.
6
pF
COUT
Output Capacitance
Note 8.
7
pF
CPD
Power Dissipation Capacitance
Note 8., 10MHz
20
pF
8. VCC = 1.8, 2.5 or 3.3V; VI = 0V or VCC.
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74VCX162373
VIH
Vm
Dn
Vm
0V
tPLH
tPHL
Vm
On
VOH
Vm
VOL
WAVEFORM 1 - PROPAGATION DELAYS
tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns
Figure 3. AC Waveforms
VIH
Vm
OEn
VIH
Dn
Vm
Vm
Vm
0V
tPZH
tPHZ
VOH
Vy
Vm
On
0V
ts
LEn
tw
Vm
On
tPLZ
≈ VCC
Vm
tPLH, tPHL
On
VOH
Vm
Vm
VOL
Vx
VOL
WAVEFORM 3 - LE to On PROPAGATION DELAYS, LE MINIMUM
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES
tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns
Figure 4. AC Waveforms
VCC
Symbol
3.3V ±0.3V
2.5V ±0.2V
1.8V ±0.15V
VIH
2.7V
VCC
VCC
Vm
1.5V
VCC/2
VCC/2
Vx
VOL + 0.3V
VOL + 0.15V
VOL + 0.15V
Vy
VOH – 0.3V
VOH – 0.15V
VOH – 0.15V
VCC
PULSE
GENERATOR
RL
DUT
RT
CL
TEST
RL
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ±0.3V;
VCC× 2 at VCC = 2.5 ±0.2V; 1.8V ±0.15V
tPZH, tPHZ
GND
CL = 30pF or equivalent (Includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 5. Test Circuit
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VIH
0V
≈ 0V
tPZL
th
6V or VCC × 2
OPEN
GND
74VCX162373
VIH
Vm
Dn
Vm
0V
tPLH
tPHL
Vm
On
VOH
Vm
VOL
WAVEFORM 4 - PROPAGATION DELAYS
tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns
Figure 6. AC Waveforms
VIH
Vm
OEn
VIH
Dn
Vm
Vm
Vm
0V
tPZH
tPHZ
VOH
Vy
Vm
On
0V
ts
LEn
tw
Vm
On
tPLZ
≈ VCC
Vm
tPLH, tPHL
On
VOH
Vm
Vm
VOL
Vx
VOL
WAVEFORM 6 - LE to On PROPAGATION DELAYS, LE MINIMUM
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES
tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted
WAVEFORM 5 - OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.0ns, 10% to 90%; f = 1MHz; tW = 500ns
Figure 7. AC Waveforms
VCC
Symbol
3.3V ±0.3V
2.7V
VIH
2.7V
2.7V
Vm
1.5V
1.5V
Vx
VOL + 0.3V
VOL + 0.3V
Vy
VOH – 0.3V
VOH – 0.3V
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VIH
0V
≈ 0V
tPZL
th
74VCX162373
AC CHARACTERISTICS (tR = tF = 2.0ns; CL = 50pF; RL = 500Ω)
Limits
TA = –40°C to +85°C
VCC = 3.0V to 3.6V
Symbol
Parameter
VCC = 2.7V
Waveform
Min
Max
Max
Unit
tPLH
tPHL
Propagation Delay
Dn to On
4
1.0
1.0
4.0
4.0
Min
4.5
4.5
ns
tPLH
tPHL
Propagation Delay
LE to On
4
1.0
1.0
4.0
4.0
5.0
5.0
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
5
1.0
1.0
5.0
5.0
6.0
6.0
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
5
1.0
1.0
4.5
4.5
5.5
5.5
ns
tOSHL
tOSLH
Output–to–Output Skew
(Note 9.)
0.5
0.5
0.5
0.5
ns
9. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter
guaranteed by design.
VCC
PULSE
GENERATOR
RL
DUT
RT
CL
TEST
RL
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ±0.3V;
VCC× 2 at VCC = 2.5 ±0.2V; 1.8V ±0.15V
tPZH, tPHZ
GND
CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 8. Test Circuit
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6V or VCC × 2
OPEN
GND
74VCX162373
P0
K
t
P2
D
TOP
COVER
TAPE
E
A0
+
K0
SEE
NOTE 2
B1
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±0.2 mm
(±0.008")
SEE NOTE 2
F
+
B0
W
+
D1
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
P
EMBOSSMENT
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B0
CENTER LINES
OF CAVITY
USER DIRECTION OF FEED
*TOP COVER
TAPE THICKNESS (t1)
0.10 mm
(0.004") MAX.
R MIN.
BENDING RADIUS
10°
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS R"
WITHOUT DAMAGE
EMBOSSED
CARRIER
100 mm
(3.937")
MAXIMUM COMPONENT ROTATION
EMBOSSMENT
1 mm MAX
TYPICAL
COMPONENT CAVITY
CENTER LINE
TAPE
1 mm
(0.039") MAX
TYPICAL
COMPONENT
CENTER LINE
250 mm
(9.843")
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 9. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)
Tape
Size
B1
Max
24mm
20.1mm
(0.791")
D
D1
E
F
K
P
P0
P2
R
T
W
1.5 + 0.1mm
-0.0
(0.059
+0.004" -0.0)
1.5mm
Min
(0.060")
1.75
±0.1 mm
(0.069
±0.004")
11.5
±0.10 mm
(0.453
±0.004")
11.9 mm
Max
(0.468")
16.0
±0.1 mm
(0.63
±0.004")
4.0
±0.1 mm
(0.157
±0.004")
2.0
±0.1 mm
(0.079
±0.004")
30 mm
(1.18")
0.6 mm
(0.024")
24.3 mm
(0.957")
1. Metric Dimensions Govern–English are in parentheses for reference only.
2. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
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74VCX162373
t MAX
13.0 mm ±0.2 mm
(0.512" ±0.008")
1.5 mm MIN
(0.06")
A
20.2 mm MIN
(0.795")
50 mm MIN
(1.969")
FULL RADIUS
G
Figure 10. Reel Dimensions
REEL DIMENSIONS
Tape Size
A Max
G
t Max
24 mm
360 mm
(14.173")
24.4 mm + 2.0 mm, -0.0
(0.961" + 0.078", -0.00)
30.4 mm
(1.197")
DIRECTION OF FEED
BARCODE LABEL
POCKET
Figure 11. Reel Winding Direction
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HOLE
74VCX162373
CAVITY
TAPE
TOP TAPE
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
TAPE LEADER
NO COMPONENTS
400 mm MIN
COMPONENTS
DIRECTION OF FEED
Figure 12. Tape Ends for Finished Goods
User Direction of Feed
Figure 13. Reel Configuration
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
É
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
É
ÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
É
ÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉ
K
L
G
48 Leads
Package Footprint
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This Material Copyrighted by Its Respective Manufacturer
F
74VCX162373
PACKAGE DIMENSIONS
TSSOP
DT SUFFIX
CASE 1201–01
ISSUE A
48X
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
K
K1
K REF
0.12 (0.005)
M
T U
S
V
S
T U
S
J J1
48
25
SECTION N–N
M
0.254 (0.010)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
B
–U–
L
N
1
24
A
–V–
PIN 1
IDENT.
N
F
DETAIL E
D
C
0.076 (0.003)
–T– SEATING
PLANE
M
0.25 (0.010)
–W–
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
12.40
12.60
6.00
6.20
--1.10
0.05
0.15
0.50
0.75
0.50 BSC
0.37
--0.09
0.20
0.09
0.16
0.17
0.27
0.17
0.23
7.95
8.25
0
8
INCHES
MIN
MAX
0.488
0.496
0.236
0.244
--0.043
0.002
0.006
0.020
0.030
0.0197 BSC
0.015
--0.004
0.008
0.004
0.006
0.007
0.011
0.007
0.009
0.313
0.325
0
8
H
G
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