NSC 100304D

100304
Low Power Quint AND/NAND Gate
General Description
The 100304 is monolithic quint AND/NAND gate. The Function output is the wire-NOR of all five AND gate outputs. All
inputs have 50 kΩ pull-down resistors.
n
n
n
n
n
Features
2000V ESD protection
Pin/function compatible with 100104
Voltage compensated operating range = −4.2V to −5.7V
Available to industrial grade temperature range
Available to Standard Microcircuit Drawing
(SMD) 5962-9153701
n Low Power Operation
Logic Symbol
DS100304-1
Logic Equation
F = (D1a • D2a) + (D1b • D2b) + D1c • D2c) + (D1d • D2d) + (D1e • D2e).
Pin Names
Description
Dna–Dne
Data Inputs
F
Function Output
Oa–Oe
Data Outputs
Oa–Oe
Complementary Data Outputs
© 1998 National Semiconductor Corporation
DS100304
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100304 Low Power Quint AND/NAND Gate
August 1998
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
DS100304-3
DS100304-2
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2
Absolute Maximum Ratings (Note 1)
≥2000V
ESD (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Above which the useful life may be impaired
−65˚C to +150˚C
Storage Temperature (TSTG)
Maximum Junction Temperature (TJ)
Ceramic
+175˚C
−7.0V to +0.5V
VEE Pin Potential to Ground Pin
Input Voltage (DC)
VEE to +0.5V
Output Current (DC Output HIGH)
−50 mA
Case Temperature (TC)
Military
Supply Voltage (VEE)
−55˚C to +125˚C
−5.7V to −4.2V
Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C
Symbol
VOH
Conditions
Parameter
Min
Max
Units
TC
Output HIGH Voltage
−1025
−870
mV
0˚C to
−1085
−870
mV
−55˚C
VIN = VIH (Max)
Loading with
−1830 −1620
mV
0˚C to
or VIL (Min)
50Ω0 to −2.0V
−1830 −1555
mV
−55˚C
−1035
mV
0˚C to
−1085
mV
−55˚C
VIN = VIH (Min)
Loading with
−1610
mV
0˚C to
or VIL (Max)
50Ω to −2.0V
−1555
mV
−870
mV
Notes
+125˚C
VOL
Output LOW Voltage
(Notes 3, 4, 5)
+125˚C
VOHC
Output HIGH Voltage
+125˚C
VOLC
Output LOW Voltage
(Notes 3, 4, 5)
+125˚C
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
−1165
−1830 −1475
mV
−55˚C
−55˚C
Guaranteed HIGH Signal
+125˚C
for All Inputs
−55˚C to
+125˚C
IIL
Input LOW Current
0.50
µA
−55˚C to
+125˚C
Guaranteed LOW Signal
for All Inputs
VEE = −4.2V
(Notes 3, 4, 5, 6)
(Notes 3, 4, 5, 6)
(Notes 3, 4, 5)
VIN = VIL (Min)
Input High Current
D2a–D2e
250
D1a–D1e
350
D2a–D2e
350
D1a–D1e
500
µA
0˚C to
+125˚C
IIH
IEE
Power Supply Current
−75
−25
µA
−55˚C
mA
−55˚C to
VEE = −5.7V
VIN = VIH (Max)
(Notes 3, 4, 5)
Inputs Open
(Notes 3, 4, 5)
+125˚C
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 4: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups, 1, 2 3, 7, and 8.
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.
3
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AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
TC = −55˚C
TC = +25˚C
TC = +125˚C
Min
Max
Min
Max
Min
Max
0.30
1.90
0.40
1.80
0.30
2.30
ns
0.80
2.90
0.90
2.80
0.90
3.40
ns
0.20
1.80
0.30
1.60
0.20
2.00
ns
Parameter
tPLH
Propagation Delay
tPHL
Dna–Dne to O, O
tPLH
Propagation Delay
tPHL
Data to F
tTLH
Transition Time
tTHL
20% to 80%, 80% to 20%
Units
Conditions
Notes
(Notes 7, 8, 9)
Figures 1, 2
(Note 10)
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25˚C temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each mfg. lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data).
Test Circuitry
DS100304-5
Notes:
VCC, VCCA = +2V, VEE = −2.5V
L1 and L2 = equal length 50Ω impedance lines
RT = 50Ω terminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ω to GND
CL = Fixture and stray capacitance ≤ 3 pF
FIGURE 1. AC Test Circuit
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Switching Waveforms
DS100304-6
FIGURE 2. Propagation Delay and Transition Times
5
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Physical Dimensions
inches (millimeters) unless otherwise noted
24-Pin Ceramic Dual-In-Line Package (D)
NS Package Number J24E
24-Pin Quad Cerpak (F)
NS Package Number W24B
7
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100304 Low Power Quint AND/NAND Gate
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ure to perform when properly used in accordance
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