Memory ICs 8k × 8 Bit SRAM BR6265BF-N10SL The BR6265BF-N10SL is an 8192 word × 8 bit CMOS static RAM. It runs on a 5V single power supply, and input can be directed coupled with TTL. Current dissipation in the non-selected state is extremely low at 20µA (max.), and memory information can be retained even at a low voltage of 2V, making this product ideal for battery backup operations. Both the access and cycle timing are 100ns, facilitating timing design. Applications •General-purpose •1)Features SRAM with an 8192 × 8 bit configuration. 5) Input and output use the same pin, and there are 3 output states. 6) No clock is necessary (asynchronous static circuit). 7) Input and output data are in the same phase. 8) Low power dissipation. 2) 5V single power supply voltage with ± 10% fluctuation tolerance. 3) High speed access time of 100ns. 4) TTL compatible input / output. •Block diagram A8 A5 A6 A7 A12 A9 A11 ROW ROW ADDRESS DECORDER 65536BIT (128 × 512) MEMORY CELL ARRAY BUFFER I / O0 INPUT DATA CONTROL I / O7 COLUMN SWITCH OUTPUT DATA CONTROL COLUMN DECODER COLUMN ADDRESS BUFFER A0 CE1 CE2 OE WE A1 A2 A3 A4 A10 CONTROL BUFFER 1 Memory ICs BR6265BF-N10SL •Absolute maximum ratings (Ta = 25°C) Parameter Symbol Power supply voltage VCC Power dissipation Pd Limits Unit – 0.5∗1 ~ + 7.0 V 850∗2 mW Operating temperature Topr 0 ~ 70 °C Storage temperature Tstg – 55 ~ + 125 °C – 0.5 ~ VCC + 0.5 V I / O voltage VI ∗1 At pulse width of 50 ns : – 3.0V (min.) ∗2 Reduced by 8.5mW for each increase in Ta of 1°C over 25°C. •Recommended operating conditions (Ta = 25°C) Parameter Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V Power supply voltage Input high level voltage VIH 2.2 — VCC + 0.5 V Input low level voltage VIL – 0.3 — 0.8 V Ambient temperature Ta — 70 °C 0 •Pin descriptions 2 Pin No. Pin name Function 1 NC 2 ~ 10, 21, 23 ~ 25 A0 ~ A12 11 ~ 13, 15 ~ 19 I / O0 ~ I / O7 20 CE1 Chip enable control input 26 CE2 Chip enable control input 22 OE Output enable control input 27 WE Write enable control input 28 VCC 5V ± 10%power supply 14 VSS Reference voltage for all input / output, 0V Internal chip and not connected 8192-byte memory address input 8-bit data I / O Memory ICs BR6265BF-N10SL •Electrical characteristics (unless otherwise noted, Ta = 0 to 70°C, V CC = 5V ± 10%) Symbol Min. Typ. Max. Unit Conditions Measurement circuit VIL – 0.3∗1 — 0.8 V — — Input high level voltage VIH 2.2 — VCC + 0.5 V Output low level voltage VOL 0 — 0.4 V Output high level voltage VOH Parameter Input low level voltage — — IOL = 2.1mA Fig.1 2.4 — VCC V IOH = – 1.0mA Fig.2 VCC × 0.8 — VCC V IOH = – 0.1mA — Input leakage current ILI — — ±1 µA VIN = 0 ~ VCC Fig.3 Output leakage current ILO — — ±1 µA VOUT = 0 ~ VCC Fig.4 ICCA1 — — 40 mA CE1 = VIL, CE2 = VIH, I / O: OPEN Minimum cycle time Fig.5 ICCA2 — — 10 mA CE1 = VIL, CE2 = VIH, I / O: OPEN f = 1MHz Fig.5 ISB — — 3 mA CE1 = VIH or CE2 = VIL ISB1 — — 20 µA CE1 ⭌ VCC – 0.2V, CE2 ⭌ VCC – 0.2V or CE2 ⬉ 0.2V ISB2 — — 20 µA CE2 ⬉ 0.2V Average operating current Standby current — Fig.6 — ∗1 At input voltage pulse width of 50 ns or less : – 3.0V 3 Memory ICs BR6265BF-N10SL •Measurement circuits VCC VCC VCC VCC 2.1mA 1.0mA I / O0 ~ I / O7 I / O0 ~ I / O7 VSS VSS V V VOH VOL Data sets all output to HIGH (Data FF) Data sets all output to LOW (Data 00) Fig. 2 Output high level voltage measurement circuit Fig. 1 Output low level voltage measurement circuit VCC VCC VCC IL1 A VIN VCC VCC A0 ~ A12 CE1, CE2 OE VOUT Fig. 3 Input leakage measurement circuit A VCC ICCA1, ICCA2 A VIH WE CE2 CE1 OE = 0 ~ VCC Fig. 4 Output leakage current measurement circuit VCC VIH A VSS VSS = 0 ~ VCC ILO I / O0 ~ I / O7 VCC I / O0 ~ I / O7 VCC OPEN q A0 ~ A12 SW ISB, 1 VIL or VIH (Min. cycle) VSS CE1 I / O0 ~ I / O7 A0 ~ A12 CE2 OPEN VCC or GND VSS w VIL or VIH (1MHz cycle) VIL q : Average operating current ICCA1 w : Average operating current ICCA2 Fig. 5 Current dissipation measurement circuit 4 Fig. 6 Standby current measurement circuit Memory ICs BR6265BF-N10SL •Operating modes Control pin Mode I/O Power dissipation OE CE1 CE2 WE X H X X Wait state High impedance Standby state X X L X Wait state High impedance Standby state H L H H Output disabled High impedance Operating state L L H H Read Data output Operating state X L H L Write Data output Operating state X : Either VIL or VIH AC test conditions (Ta = 0 to 70°C, V •Input pulse level : 0.8 to 2.4V CC = 5V ± 10%) Input rise / fall time : 5ns I / O timing level : 1.5V Output load : 1 TTL gate and CL = 100pF •Read cycle Parameter Symbol Min. Max. Unit ns Read cycle time tRC 100 — Address access time tAA — 100 ns CE1 access time tCO1 — 100 ns CE2 access time tCO2 — 100 ns OE access time tOE — 40 ns Output hold time tOH 10 — ns CE1 output set time tLZ1 10 — ns CE2 output set time tLZ2 10 — ns OE output reset time tOLZ 5 — ns CE1 deselect output floating tHZ1 — 35 ns CE2 deselect output floating tHZ2 — 35 ns tOHZ — 35 ns OE disable output floating 5 Memory ICs BR6265BF-N10SL •Read cycle timing chart 1 (CE1 = OE = V , CE2 = WE = V ) IL IH tRC Address tAA tOH Dout Previous Valid Data Valid Data •Read cycle timing chart 2 (WE = V ) Fig.7 IH tRC Address tAA CE1 tCO1 tHZ1 tLZ1 CE2 tCO2 tHZ2 tLZ2 OE tOHZ tOE tOLZ Valid Data Dout High Impedance Fgi.8 6 Memory ICs BR6265BF-N10SL •Write cycle Parameter Symbol Min. Max. Unit Write cycle time tWC 100 — ns Chip select time tCW 80 — ns Address valid time tAW 80 — ns Address setup time tAS 0 — ns Write pulse width tWP 60 — ns WE output delay time tWR 0 — ns CE1, CE2 output delay time tWR1 0 — ns WE · output floating time tWHZ — 35 ns Input data set time tDW 40 — ns Input data hold time tDH 0 — ns WE · output set time tOW 5 — ns •Write cycle timing chart 1 (WE control) tWC Address tAW tWR OE CE1 tCW CE2 tCW tAS tWP WE tDW DIN tDH Valid Data tWHZ tOW DOUT High Impedance Fig.9 7 Memory ICs BR6265BF-N10SL •Write cycle timing chart 2 (CE1 control) tWC Address tAW OE tWR1 tAS tCW CE1 CE2 tWP WE tDH tDW Valid Data DIN tWHZ tLZ1 DOUT Fig.10 8 Memory ICs BR6265BF-N10SL •Write cycle timing chart 3 (CE2 control) tWC Address tAW OE CE1 tAS tCW tWR1 CE2 tWP WE tDH tDW Valid Data DIN tWHZ tLZ2 DOUT Fig.11 ∗ While the I / O pin is in output state, input signals should not be applled which are in reverse phase to the output. ∗ The contents noted in this document may fall under the jurisdiction of services pertaining to overseas exchange rates and overseas control regulations (services pertaining to design, construction, specifications), and may requlre special handiing. 9 Memory ICs BR6265BF-N10SL •Data retention characteristics at low power supply voltage (Ta = 0 to 70°C): SL version products Parameter Symbol Min. Typ. Max. Unit Data retention power supply voltage VDR 2.0 — 5.5 V CE1 ⭌ VCC – 0.2V, CE2 ⭌ VCC – 0.2V or CE2 ⬉ 0.2V Data retention current ICCDR∗ — — 10 µA CE1 ⭌ VCC – 0.2V, CE2 ⭌ VCC – 0.2V or CE2 ⬉ 0.2V, VCC = 3.0V CS data retention time tCDR 0 — — ns — tR 5 — — ms — Operating recovery time Conditions ∗ 1µA (Max.), when Ta = 0 ~ 40°C •Data retention waveform at low power supply voltage Data Retention Mode 4.5V VCC 4.5V VDR tCDR CE1 tR CE1 ⭌ VDR – 0.2V 2.2V 2.2V Data Retention Mode VCC 4.5V VDR tR tCDR 0.4V CE2 0.4V CE2 ⬉ 0.2V Fig.12 10 4.5V Memory ICs BR6265BF-N10SL •External dimensions (Units: mm) 15 1 14 1.27 0.40 ± 0.10 0.15 ± 0.1 8.4 ± 0.2 0.20 2.55 ± 0.10 11.8 ± 0.3 18.0 ± 0.2 28 0.5Min. 0.10 SOP-N28 11