ETC CH7008-T

CH7008A
CHRONTEL
Digital PC to TV Encoder Features
Features
General Description
• Support for low voltage interface to VGA controller
• Universal digital interface accepts YCrCb (CCIR656)
or RGB (15, 16 or 24-bit multiplexed) video data in
both non-interlaced and interlaced formats
• TrueScale TM rendering engine supports underscan
operations for various graphic resolutions† ¥
• Enhanced text sharpness and adaptive flicker removal
with up to 5-lines of filtering†
• Enhanced dot crawl control and area reduction
• Fully programmable through serial port
• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,
G, H, I, M and N) TV formats
• Provides Composite, S-Video and SCART outputs
• Auto-detection of TV presence
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in 44-pin PLCC, 44-pin TQFP (1.4 mm)
Chrontel’s CH7008 digital PC to TV encoder is a standalone integrated circuit which provides a PC 99 compliant
solution for TV output on non-DVD enabled systems.
Suggested application use with the Intel 810 chipset &
Intel 810E chipset.* It provides a universal digital input
port to accept a pixel data stream from a compatible VGA
controller (or equivalent) and converts this directly into
NTSC or PAL TV format.
This circuit integrates a digital NTSC/PAL encoder with
9-bit DAC interface, and new adaptive flicker filter, and
high accuracy low-jitter phase locked loop to create
outstanding quality video. Through its TrueScaleTM
scaling and deflickering engine, the CH7008 supports full
vertical and horizontal underscan capability and operates
in 5 different resolutions including 640x480 and 800x600.
A new universal digital interface along with full
programmability make the CH7008 ideal for system-level
PC solutions. All features are software programmable
through a standard serial port, to enable a complete PC
solution using a TV as the primary display.
† Patent number 5,781,241
¥ Patent number 5,914,753
LINE
MEMORY
YUV-RGB CONVERTER
RGB-YUV
CONVERTER
TRUE SCALE
SCALING &
DEFLICKERING
ENGINE
DIGITAL
D[11:0]
PIXEL DATA
INPUT
INTERFACE
NTSC/PAL
ENCODER
& FILTERS
Y/R
TRIPLE
DAC
C/G
CVBS/B
ISET
SYSTEM CLOCK
SERIAL PORT
CONTROLLER
GPIO[1:0]
SC
SD
TIMING & SYNC
GENERATOR
PLL
RESET*
XCLK*
H
V
XI/FIN
XO CSYNC P-OUT DS/BCO
Figure 1: Functional Block Diagram
201-0000-027 Rev. 2.4, 04/12/2001
*Intel 810 and Intel 810E are Trademarks of Intel Corp
1
D0]
V
H
XCLK*
XCLK
VREF
DVDD2
P-OUT
DGND
DS/BCO
AGND
5
4
3
2
1
44
43
42
41
40
CH7008A
6
CHRONTEL
D[1]
7
39
XO
D[2]
8
38
XI/FIN
D[3]
9
37
AVDD
D[4]
10
36
DVDD
DVDD
11
35
RESET*
D[5]
12
34
DGND
D[6]
13
33
SC
DGND]
14
32
SD
D[7]
15
31
VDD
D[8]
16
30
ISET
D[9]
17
29
GND
20
21
22
23
24
25
26
27
28
GPIO[1]
DVDD
CSYNC
DGND
GND
CVBS
C
Y
19
D[11]
GPIO[0]
18
D[10]
CHRONTEL
CH7008
Figure 2: 44-Pin PLCC
2
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CHRONTEL
D0]
V
H
XCLK*
XCLK
VREF
DVDD2
P-OUT
DGND
DS/BCO
AGND
44
43
42
41
40
39
38
37
36
35
34
CH7008A
D[1]
1
33
XO
D[2]
2
32
XI/FIN
D[3]
3
31
AVDD
D[4]
4
30
DVDD
DVDD
5
29
RESET*
D[5]
6
28
DGND
D[6]
7
27
SC
DGND]
8
26
SD
D[7]
9
25
VDD
D[8]
10
24
ISET
D[9]
11
25
GND
13
14
15
16
17
18
19
20
21
22
D[11]
GPIO[0]
GPIO[1]
DVDD
CSYNC
DGND
GND
CVBS
C
Y
D[10]
12
CHRONTEL
CH7008
Figure 3: 44-Pin TQFP (1.4 mm)
201-0000-027 Rev. 2.4, 04/12/2001
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CHRONTEL
CH7008A
Table 1. Pin Descriptions
44-Pin
PLCC
44-Pin
TQFP
(1.4mm)
Type
Symbol
Description
1
39
In/Out
VREF
Reference Voltage Input
The VREF pin inputs a reference voltage of DVDD2/2. The signal is
derived externally through a resistor divider and decoupling capacitor,
and will be used as a reference level for data and sync inputs.
2
40
In
XCLK
External Clock Input
This input along with XCLK* will form a differential clock input. For
applications where a differential clock is not available, the XCLK* pin
should be connected to the VREF pin.
3
41
In
XCLK*
External Clock Input*
See XCLK description
4
42
In/Out
H
Horizontal Sync Input/Output
When the SYO bit is low, this pin accepts a horizontal sync input. The
level is 0 to DVDD2, with VREF as the threshold level.
When the SYO bit is high, the device will output a horizontal sync pulse.
The output is driven from the DVDD supply.
5
43
In/Out
V
Vertical Sync Input/Output
When the SYO bit is low, this pin accepts a vertical sync input. The level
is 0 to DVDD2 with VREF as the threshold level.
When the SYO bit is high, the device will output a vertical sync pulse.
The output is driven from the DVDD supply.
6-10,1213,15-19
44,1-4,67,9-13
In
D[0]-D[11]
Data [0] through Data [11] Inputs
These pins accept 12 data inputs from the graphics controller. The level
is 0 to DVDD2, with VREF as the threshold level.
20-21
14-15
In/Out
GPIO[0]
General Purpose Input/Output [0-1] and Internal pull-up
These pins provide general purpose I/O’s controlled via the IIC bus,
registers 1Bh and 1Ch, bits 7 and 6. The internal pull-up is to the DVDD
supply.
GPIO[1]
4
23
17
Out
CSYNC
Composite Sync Output
A 75 Ω termination resistor with short traces should be attached
between CSYNC and ground for optimum performance. In SCART
mode, this pin outputs the composite sync signal.
26
20
Out
CVBS/B
Composite Video Output/Blue Output
A 75 Ω termination resistor with short traces should be attached
between CVBS and ground for optimum performance. In normal
operating modes other than SCART, this pin outputs the composite
video signal. In SCART mode, this pin outputs the blue signal.
27
21
28
22
30
24
Out
C/G
Chroma Output/Green Output
A 75 Ω termination resistor with short traces should be attached
between C and ground for optimum performance. In normal operating
modes other than SCART, this pin outputs the chroma video signal. In
SCART mode, this pin outputs the green signal.
Out
Y/R
Luma Output / Red Output
A 75 Ω termination resistor with short traces should be attached
between Y and ground for optimum performance. In normal operating
modes other than SCART, this pin outputs the luma video signal. In
SCART mode, this pin outputs the red signal.
In
ISET
Current Set Resistor Input
This pin sets the DAC current. A 360 ohm resistor should be
connected between this pin and GND using short and wide traces.
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CHRONTEL
CH7008A
Table 1. Pin Descriptions
44-Pin
PLCC
44-Pin
TQFP
(1.4mm)
Type
Symbol
Description
32
26
In/Out
SD
Serial Data Input/Output
This pin functions as the serial data pin of the serial port, and uses the
DVDD supply.
33
27
In
SC
Serial Clock Input
This pin functions as the serial clock pin of the serial port, and uses
the DVDD supply.
35
29
In
RESET*
Reset* Input
When this pin is low, the CH7008 is held in the power-on reset
condition. When this pin is high, the device operates normally and reset
is controlled through the serial port register.
38
32
In
XI/FIN
Crystal Input/External Reference Input
A parallel resonance 14.31818MHz crystal should be attached
between this pin and XO. However, an external CMOS clock can be
attached to XI/FIN.
39
33
Out
XO
Crystal Output
A parallel resonance 14.31818MHz +20ppm crystal should be
attached between this pin and XI/FIN. However, if an external CMOS
clock is attached to XI/FIN, XO should not be connected.
41
35
In/Out
DS/BCO
Data start (input)/Buffered Clock (output)
In normal operating modes, when configured as an input, the rising
edge of this signal identifies the first active pixel of data for each
active line. The level is 0 to DVDD2, with VREF as the threshold level.
When configured as an output this pin provides a buffered clock
output, driven by the DVDD supply. The output clock can be selected
using the BCO register (17th) (see Registers and Programing).
43
37
Out
P-OUT
11,22,36
5,16,30
Power
DVDD
Digital Supply Voltage
14,24,34,
42
8,18,28,3
6
Power
DGND
Digital Ground
25,29
19,23
Power
GND
DAC
31
25
Power
VDD
DAC Supply Voltage
37
31
Power
AVDD
PLL Supply Voltage
40
34
Power
AGND
PLL Ground
44
38
Power
DVDD2
I/O SUPPLY VOLTAGE
Digital supply voltage for the P-OUT
201-0000-027 Rev. 2.4, 04/12/2001
Pixel Clock Output
This pin provides a pixel clock signal to the VGA controller (adjustable as
1X, 2X and 3X) and is driven from the DVDD2 supply. This clock will only
be provided in master clock modes, and will be tri-stated otherwise, (see
the section on Digital Video Interface and Registers and Programming
for more details). The capacitive loading on this pin should be kept to a
minimum.
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CHRONTEL
CH7008A
Digital Video Interface
The CH7008 digital video interface provides a flexible digital interface between a computer graphics
controller and the TV encoder IC forming the ideal quality/cost configuration for performing the TV-output
function. This digital interface consists of up to 12 data signals and 4 control signals, all of which are
subject to programmable control through the CH7008 register set. This interface can be configured as 8
or 12-bit inputs operating in multiplexed mode. It will also accept either YCrCb or RGB (15, 16 or 24-bit
color depth) data formats and will accept both non-interlaced and interlaced data formats. A summary of
the input data format modes is as follows:
Table 2. Input Data Formats
Bus
Width
Transfer Mode
Color Space and Depth
Format Reference
8-bit
8-bit
8-bit
12-bit
12-bit
2X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
RGB 15-bit
RGB 16-bit
YCrCb (24-bit)
RGB 24
RGB 24
5-5-5 over two bytes
5-6-5 over two bytes
Cb,Y0,Cr,Y1,(CCIR656 style)
8-8-8 over two words - ‘C’ version
8-8-8 over two words - ‘I’ version
The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode.
The CH7008 can operate in either master (the CH7008 generates a pixel frequency which is either returned as a
phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock).
The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired
output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X or
3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7008 will
automatically use both clock edges, if a multiplexed data format is selected.
Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be
selected to be generated by the CH7008. In the case of CCIR656 style input (IDF = 9), embedded sync may also be
used. In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, times the first
value of the (Total Pixels/line x Total Lines/Frame) column of Table 13 on page 29 (Display Mode Register 00H
description). The leading edge of the horizontal sync is used to determine the start of each line. The Vertical sync
signal must be able to be set to the second value in the (Total Pixels/Line x Total Lines/Frame) column of Table 13
on page 29.
Master Clock Mode: The CH7008 generates a clock signal (output at the P-OUT pin) which will be used by the
VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input
via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The
XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X
the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected
directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and
hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity).
Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock signal
will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the pixel
data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC transmits
back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet the
specified setup and hold times with respect to the pixel clock.
Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after the
leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count), plus
horizontal sync width, will determine when the chip will begin to sample pixels.
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201-0000-027 Rev. 2.4, 04/12/2001
CHRONTEL
CH7008A
Input Data Formats
The XCLK and XCLK* signals are used to latch data from the graphics chip. Data can be latched coincident with
the rising edge of XCLK, falling edge of XCLK, or both edges, depending upon register settings of XCM and MCP.
The input data format is shown in Figure 4. The Pixel Data bus represents an 8 or 12-bit multiplexed data stream,
which contains either RGB or YCrCb formatted data. In IDF settings of 4, 5, 7, 8 and 9, the input data rate is 2X
pixel clock, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel, encoded as shown in the
tables below. When the input is YCrCb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb0, Y0, Cr0, Y1 where Cb0,Y0,Cr0 refers to co-sited luminance and
color-difference samples — and the following Y1 byte refers to the next luminance sample, per CCIR656 standards.
However, the clock frequency is dependent upon the current mode, not 27MHz, as specified in CCIR656.
HS
SAV
(DSEN=0)
DS / BCO
XCLK (XCM=01)
XCLK*(XCM=01)
XCLK (XCM=00)
XCLK*(XCM=00)
D[11:0]
P0a
P0b
P1a
P1b
P2a
P2b
When DSEN=1(bit 4 of register 1Ch), SAV should be set to 11d.
Figure 4: Non-multiplexed Data Transfers
Table 3. RGB 8-bit Multiplexed Mode
IDF#
Format
Pixel#
Bus Data
7
RGB 5-6-5
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
P0a
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
201-0000-027 Rev. 2.4, 04/12/2001
P0b
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[5]
G0[4]
G0[3]
P1a
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
8
RGB 5-5-5
P1b
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[5]
G1[4]
G1[3]
P0a
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
P0b
x
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[4]
G0[3]
P1a
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P1b
x
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[4]
G1[3]
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CHRONTEL
CH7008A
Table 4. RGB 12-bit Multiplexed Mode
IDF#
Format
Pixel#
Bus Data
4
12-bit RGB (12-12)
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
P0a
G0[3]
G0[2]
G0[1]
G0[0]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
P0b
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[7]
G0[6]
G0[5]
G0[4]
P1a
G1[3]
G1[2]
G1[1]
G1[0]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
5
12-bit RGB (12-12)
P1b
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[7]
G1[6]
G1[5]
G1[4]
P0a
G0[4]
G0[3]
G0[2]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
G0[0]
B0[2]
B0[1]
B0[0]
P0b
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
G0[7]
G0[6]
G0[5]
R0[2]
R0[1]
R0[0]
G0[1]
P1a
G1[4]
G1[3]
G1[2]
B1[7]
B1[6]
B1[7]
B1[4]
B1[3]
G1[0]
B1[2]
B1[1]
B1[0]
P1b
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
G1[5]
R1[2]
R1[1]
R1[0]
G1[1]
P3a
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
P3b
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
Table 5. YCrCb Multiplexed Mode
IDF#
Format
Pixel#
Bus Data
8
9
YCrCb 8-bit
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
P0a
Cb0[7]
Cb0[6]
Cb0[5]
Cb0[4]
Cb0[3]
Cb0[2]
Cb0[1]
Cb0[0]
P0b
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
P1a
Cr0[7]
Cr0[6]
Cr0[5]
Cr0[4]
Cr0[3]
Cr0[2]
Cr0[1]
Cr0[0]
P1b
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
P2a
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
P2b
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
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CHRONTEL
CH7008A
When IDF = 9, (YCrCb 8-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the
embedded sync will be similar to the CCIR656 convention, and the first byte of the ‘video timing reference code’
will be assumed to occur when a Cb sample would occur – if the video stream was continuous. This is delineated in
Table 6 shown below.
Table 6. YCrCb Multiplexed Mode with Embedded Syncs
IDF#
Format
Pixel#
Bus Data
9
YCrCb 8-bit
P0a
1
1
1
1
1
1
1
1
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
P0b
0
0
0
0
0
0
0
0
P1a
0
0
0
0
0
0
0
0
P1b
S[7]
S[6]
S[5]
S[4]
S[3]
S[2]
S[1]
S[0]
P2a
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
P2b
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
P3a
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
P3b
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
In this mode, the S[7:0] byte contains the following data:
S[6]
S[5]
S[4]
=
=
=
F
V
H
=
=
=
1 during field 2, 0 during field 1
1 during field blanking, 0 elsewhere
1 during EAV (the synchronization reference at the end of active video)
0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3-0] are ignored.
201-0000-027 Rev. 2.4, 04/12/2001
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CHRONTEL
CH7007A
Functional Description
The CH7008 is a TV-output companion chip to graphics controllers providing digital output in either YCrCb or
RGB format. This solution involves both hardware and software elements which work together to produce an
optimum TV screen image based on the original computer generated pixel data. All essential circuitry for this
conversion are integrated on chip. On chip circuitry includes memory, memory control, scaling, PLL, DAC, filters
and NTSC/PAL encoder. All internal signal processing, including NTSC/PAL encoding, is performed using digital
techniques to ensure that the high-quality video signals are not affected by drift issues associated with analog
components. No additional adjustment is required during manufacturing.
CH7008 is ideal for PC motherboards, web browsers or VGA add-in boards where a minimum of discrete support
components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation.
Architectural Overview
The CH7008 is a complete TV output subsystem which uses both hardware and software elements to produce an
image on TV which is virtually identical to the image that would be displayed on a monitor. Simply creating a
compatible TV output from a VGA input involves a relatively straightforward process. This process includes a
standard conversion from RGB to YUV color space, converting from a non-interlaced to an interlaced frame
sequence, and encoding the pixel stream into NTSC or PAL compliant format. However, creating an optimum
computer-generated image on a TV screen involves a highly sophisticated process of scaling, deflickering, and
filtering. This results in a compatible TV output that displays a sharp and subtle image, of the right size, with
minimal artifacts from the conversion process.
As a key part of the overall system solution, the CH7008 software establishes the correct framework for the VGA
input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600), the
CH7008 software may be invoked to establish the appropriate TV output display. The software then programs the
various timing parameters of the VGA controller to create an output signal that will be compatible with the chosen
resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates, total
pixels per line, and total lines per frame. By performing these adjustments in software, the CH7008 can render a
superior TV image without the added cost of a full frame buffer memory – normally used to implement features
such as scaling and full synchronization.
The CH7008 hardware accepts digital RGB or YCrCb inputs, which are latched in synchronization with the pixel
clock. These inputs are then color-space converted into YUV in 4-2-2 format, and stored in a line buffer memory.
The stored pixels are fed into a block where scan-rate conversion, underscan scaling and 2-line, 3-line, 4-line or 5line vertical flicker filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to
either NTSC or PAL scan rates; the vertical flicker filter eliminates flicker at the output while the underscan scaling
reduces the size of the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through
digital filters to minimize aliasing problems. The digital encoder receives the filtered signals and transforms them to
composite and S-Video outputs, which are converted by the three 9-bit DACs into analog outputs.
Color Burst Generation*
The CH7008 allows the subcarrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator,
leaving the subcarrier frequency independent of the sampling rate. As a result, the CH7008 may be used with any
VGA chip (with an appropriate digital interface) since the CH7008 subcarrier frequency can be generated without
being dependent on the precise pixel rates of VGA controllers. This feature is a significant benefit, since even a
±0.01% subcarrier frequency variation may be enough to cause some television monitors to lose color lock.
In addition, the CH7008 has the capability to genlock the color burst signal to the VGA horizontal sync frequency,
which enables a fully synchronous system between the graphics controller and the television. When genlocked, the
CH7008 can also stop “dot crawl” motion (for composite mode operation in NTSC modes) to eliminate the
annoyance of moving borders. Both of these features are under programmable control through the register set.
Display Modes
The CH7008 display mode is controlled by three independent factors: input resolution, TV format, and scale factor,
which are programmed via the display mode register. It is designed to accept input resolutions of 640x480, 800x600,
640x400 (including 320x200 scan-doubled output), 720x400 and 512x384.
201-0000-027 Rev. 2.4, 04/12/2001
* Patent number 5,874,846
10
CHRONTEL
CH7008A
Display Modes (continued)
It is designed to support output to either NTSC or PAL television formats. The CH7008 provides interpolated
scaling with selectable factors of 5:4, 1:1, 7:8, 5:6, 3:4 and 7:10 in order to support adjustable overscan or underscan
operation when displayed on a TV. This combination of factors results in a matrix of useful operating modes which
are listed in detail in Table 7.
Table 7. CH7008 Display Modes
TV Format
Standard
Input
(active)
Resolution
Scale
Factor
Active
TV Lines
Percent (1)
Overscan
Pixel
Clock
Horizontal
Total
Vertical
Total
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
640x480
640x480
640x480
800x600
800x600
800x600
640x400
640x400
640x400
720x400
720x400
512x384
512x384
1:1
7:8
5:6
5:6
3:4
7:10
5:4
1:1
7:8
5:4
1:1
5:4
1:1
480
420
400
500
450
420
500
400
350
500
400
480
384
10%
(3%)
(8%)
16%
4%
(3%)
16%
(8%)
(19%)
16%
(8%)
10%
(11%)
24.671
28.196
30.210
39.273
43.636
47.832
21.147
26.434
30.210
23.790
29.455
20.140
24.671
784
784
800
1040
1040
1064
840
840
840
945
936
800
784
525
600
630
630
700
750
420
525
600
420
525
420
525
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
640x480
640x480
640x480
800x600
800x600
800x600
640x400
640x400
720x400
720x400
512x384
512x384
5:4
1:1
5:6
1:1
5:6
3:4
5:4
1:1
5:4
1:1
5:4
1:1
600
480
400
600
500
450
500
400
500
400
480
384
14%
(8%)
(29%)
14%
(4%)
(15%)
(4%)
(29%)
(4%)
(29%)
(8%)
(35%)
21.000
26.250
31.500
29.500
36.000
39.000
25.000
31.500
28.125
34.875
21.000
26.250
840
840
840
944
960
936
1000
1008
1125
1116
840
840
500
625
750
625
750
836
500
625
500
625
500
625
(1) Note: Percent underscan is a calculated value based on average viewable lines on each TV format, assuming an average TV overscan of 10%. (Negative values) indicate modes which are operating in underscan.
For NTSC: 480 active lines - 10% (overscan) = 432 viewable lines (average)
For PAL: 576 active lines - 10% (overscan) = 518 viewable lines (average)
The inclusion of multiple levels of scaling for each resolution have been created to enable optimal use of the
CH7008 for different application needs. In general, underscan (modes where percent overscan is negative) provides
an image that is viewable in its entirety on screen; it should be used as the default for most applications (e.g.,
viewing text screens, operating games, running productivity applications and working within Windows).
Overscanning provides an image that extends past the edges of the TV screen, exactly like normal television
programs and movies appear on TV, and is only recommended for viewing movies or video clips coming from the
computer. In addition to the above mode table, the CH7008 also support interlaced input modes, both in CCIR 656
and proprietary formats (see Display Mode Register section).
Flicker Filter and Text Enhancement
The CH7008 integrates an advanced 2-line, 3-line, 4-line and 5-line (depending on mode) vertical deflickering filter
circuit to help eliminate the flicker associated with interlaced displays. This flicker circuit provides an adaptive filter
algorithm for implementing flicker reduction with selections of high, medium or low flicker content for both luma
and chroma channels (see register descriptions). In addition, a special text enhancement circuit incorporates
201-0000-027 Rev. 2.4, 04/12/2001
11
CHRONTEL
CH7008A
Display Modes (continued)
additional filtering for enhancing the readability of text. These modes are fully programmable via serial port under
the flicker filter register.
Internal Voltage Reference
An on chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a
reference resistor at pin ISET, and register controlled divider, sets the output ranges of the DACs. The CH7008
bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal for PAL or NTSC-J,
which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor from ISET
to ground is 360 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for
DAC output is 1/48th. Therefore, for each DAC, the current output per LSB step is determined by the following
equation:
ILSB = V(ISET)/ISET reference resistor * 1/GAIN
For DACG=0, this is: ILSB = 1.235/360 * 1/48 = 71.4 µA (nominal)
For DACG=1, this is: ILSB = 1.317/360 * 1/48 = 76.2 µA (nominal)
Power Management
The CH7008 supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off
and Composite Off to provide optimal power consumption for the application involved. Using the programmable
power down modes accessed over the serial port, the CH7008 may be placed in either Normal state, or any of the
four power managed states, as listed below (see “Power Management Register” under theRegister Descriptions
section for programming information). To support power management, a TV sensing function (see “Connection
Detect Register” under the Register Descriptions section) is provided, which identifies whether a TV is connected to
either S-Video or composite. This sensing function can then be used to enter into the appropriate operating state
(e.g., if TV is sensed only on composite, the S-Video Off mode could be set by software).
Table 8. Power Management
Operating State
Functional Description
Normal (On):
In the normal operating state, all functions and pins are active.
Power Down:
In the power-down state, most pins and circuitry are disabled.The DS/BCO pin
will continue to provide either the VCO divided by K3, or 14.318 MHz out when
selected as an output, and the P-OUT pin will continue to output a clock
reference when in master clock mode.
S-Video Off:
Power is shut off to the unused DACs associated with S-Video outputs.
Composite Off:
In Composite-off state, power is shut off to the unused DAC associated with
CVBS output.
Full Power Down:
In this power-down state, all but the serial port interface circuits are disabled.
This places the CH7008 in its lowest power consumption mode.
Luminance and Chrominance Filter Options
The CH7008 contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and SVideo outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown,
the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and
chrominance video bandwidth output is shown in Table 9.
12
201-0000-027 Rev. 2.4, 04/12/2001
CHRONTEL
CH7008A
Table 9. Video Bandwidth
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Chrominance
00
0.62
0.78
0.53
0.65
0.83
1.03
0.70
0.87
0.74
0.93
0.63
0.78
0.89
0.62
0.78
0.93
0.64
0.74
0.79
0.77
0.95
1.02
0.77
0.86
0.94
0.71
0.71
CBW[1:0]
01
10
0.68
0.80
0.85
1.00
0.58
0.68
0.71
0.83
0.91
1.07
1.13
1.32
0.77
0.90
0.95
1.12
0.81
0.95
1.02
1.20
0.68
0.80
0.86
1.00
0.98
1.15
0.68
0.80
0.85
1.00
1.02
1.20
0.71
0.83
0.81
0.95
0.87
1.02
0.85
1.00
1.03
1.22
1.12
1.32
0.85
0.99
0.94
1.11
1.03
1.21
0.78
0.91
0.78
0.91
Luminance Bandwidth with Sin(X) /X (MHz)
11
0.95
1.18
0.81
0.99
1.27
1.57
1.07
1.33
1.13
1.42
0.95
1.19
1.36
0.95
1.18
1.42
0.98
1.13
1.21
1.18
1.44
1.56
1.18
1.31
1.44
1.08
1.08
CVBS
YCV
0
1
2.26
3.37
2.82
4.21
1.93
2.87
2.36
3.52
3.03
4.51
3.75
5.59
2.56
3.81
3.17
4.72
2.69
4.01
3.39
5.05
2.28
3.39
2.84
4.24
3.25
4.84
2.26
3.37
2.82
4.21
3.39
5.05
2.35
3.50
2.70
4.02
2.89
4.31
2.82
4.20
3.44
5.13
3.73
5.56
2.82
4.20
3.13
4.66
3.43
5.11
2.58
3.85
2.58
3.85
S-Video
YSV[1:0], YPEAK = 0
00
01
1X
2.26
3.37
5.23
2.82
4.21
6.53
1.93
2.87
4.46
2.36
3.52
5.46
3.03
4.51
7.00
3.75
5.59
8.68
2.56
3.81
5.92
3.17
4.72
7.33
2.69
4.01
6.22
3.39
5.05
7.84
2.28
3.39
5.26
2.84
4.24
6.58
3.25
4.84
7.52
2.26
3.37
5.23
2.82
4.21
6.53
3.39
5.05
7.84
2.35
3.50
5.43
2.70
4.02
6.24
2.89
4.31
6.68
2.82
4.20
6.53
3.44
5.13
7.97
3.73
5.56
8.63
2.82
4.20
6.52
3.13
4.66
7.24
3.43
5.11
7.94
2.58
3.85
5.97
2.58
3.85
5.97
S-Video
YSV[1:0], YPEAK = 1
00
01
1X
2.57
4.44
5.23
3.21
5.56
6.53
2.19
3.79
4.46
2.68
4.64
5.46
3.44
5.95
7.00
4.27
7.38
8.68
2.91
5.04
5.92
3.60
6.23
7.33
3.06
5.29
6.22
3.85
6.67
7.84
2.59
4.48
5.26
3.23
5.59
6.58
3.70
6.39
7.52
2.57
4.44
5.23
3.21
5.56
6.53
3.85
6.67
7.84
2.67
4.62
5.43
3.07
5.30
6.24
3.29
5.68
6.68
3.21
5.55
6.53
3.92
6.77
7.97
4.24
7.34
8.63
3.20
5.54
6.52
3.56
6.16
7.24
3.90
6.75
7.94
2.94
5.08
5.97
2.94
5.08
5.97
The composite luminance and chrominance frequency response is depicted in Figures 5 through 7.
201-0000-027 Rev. 2.4, 04/12/2001
13
CHRONTEL
CH7008A
Luminance and Chrominance Filter Options (continued)
00
-66
-12
12
-18
18
<i>
<i>
(YCVdB
YCVdB
)n
n
-24
24
-30
30
-36
36
-42
42
00
11
22
33
44
55
fn,i
66
f
77
88
99
10
10
11
11
12
12
11
12
n,i
106 10 6
Figure 5: Composite Luminance Frequency Response (YCV = 0)
0
-6
-12
-18
<i >
YSVdB
<i>
(YSVdB
)n
-24
-30
-36
-42
0
1
2
3
4
5
6
7
8
9
10
f
n,i
6
10
Figure 6: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = 0)
14
201-0000-027 Rev. 2.4, 04/12/2001
CHRONTEL
CH7008A
Luminance and Chrominance Filter Options (continued)
00
-66
-12
12
18
-18
<i >
UVfirdB
n
(UVfirdB<i>)n
24
-24
30
-30
36
-36
42
-42
00
11
22
33
44
55
66
fn,ifn , i
77
88
99
10
10
11
11
12
12
66
1010
Figure 7: Chrominance Frequency Response
201-0000-027 Rev. 2.4, 04/12/2001
15
CHRONTEL
CH7008A
NTSC and PAL Operation
Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to
characterize these outputs are listed in Table 10 and shown in Figure 8. (See Figures 11 through 16 for illustrations
of composite and S-Video output waveforms).
CCIR624-3 Compliance
The CH7008 is predominantly compliant with the recommendations called out in CCIR624-3. The following are the
only exceptions to this compliance:
• The frequencies of Fsc, Fh, and Fv can only be guaranteed in master mode, not in slave mode when the graphics
device generates these frequencies.
• It is assumed that gamma correction, if required, is performed in the graphics device which establishes the color
reference signals.
• All modes provide the exact number of lines called out for NTSC and PAL modes respectively, except mode 21,
which outputs 800x600 resolution, scaled by 3:4, to PAL format with a total of 627 lines (vs. 625).
• Chroma signal frequency response will fall within 10% of the exact recommended value.
• Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to
approximate CCIR624-3 requirements, but will fall into a range of values due to the variety of clock frequencies
used to support multiple operating modes.
Table 10. NTSC/PAL Composite Output Timing Parameters (in mS)
Symbol
Level (mV)
Description
Duration (uS)
NTSC
PAL
NTSC
PAL
287
300
1.49 - 1.51
1.48 - 1.51
0
0
4.69 - 4.72
4.69 - 4.71
A
Front Porch
B
Horizontal Sync
C
Breezeway
287
300
0.59 - 0.61
0.88 - 0.92
D
Color Burst
287
300
2.50 - 2.53
2.24 - 2.26
E
Back Porch
287
300
1.55 - 1.61
2.62 - 2.71
F
Black
340
300
0.00 - 7.50
0.00 - 8.67
G
Active Video
340
300
37.66 - 52.67
34.68 - 52.01
H
Black
340
300
0.00 - 7.50
0.00 - 8.67
For this table and all subsequent figures, key values are:
Note:
16
1.
2.
3.
4.
ISET = 360 ohms; V(ISET) = 1.235V; 75 ohms doubly terminated load.
Durations vary slightly in different modes due to the different clock frequencies used.
Active video and black (F, G, H) times vary greatly due to different scaling ratios used in different modes.
Black times (F and H) vary with position controls.
201-0000-027 Rev. 2.4, 04/12/2001
CHRONTEL
A
CH7008A
B
C
D
E
F
G
H
Figure 8: NTSC / PAL Composite Output
S
STAR
TART
T
O
OF
F
V
VSY
SYN
NC
C
A
N
NALO
ALOG
G
StartA
of
fieldFIE
1 LD
FIE
LD 1
1
523
520
520
524
521
521
525
522
522
1
523
523
2
524
524
3
525
525
114
22
5
3
36
4
47
Pre-equalizing
Vertical sync
pulse interval
pulse interval
Reference
Line
A
A
N
N
ALO
ALO
G
G
vertical
sub-carrier phase
interval
FIE
FIE
LD
LD 2
t1+V
color
field
12
261
258
258
262
259
259
263
260
260
264
261
261
265
262
262
267
264
264
266
263
263
6
69
5
58
10
77
12
9
9
11
88
Post-equalizing
pulse interval
268
265
265
270
267
267
269
266
266
271
268
268
272
269
269
273
270
270
274
271
271
275
272
272
START
OF
VSYNC
Start of
field 2
Reference
ANALOG
sub-carrier
FIELD 1 phaset2+V
color field 2
523
520
524
521
525
522
1
523
Start of
field 3
2
524
14
3
525
36
25
7
4
85
10
7
9
6
12
9
11
8
Reference
ANALOG
sub-carrier
FIELD phase
2
t3+V
color field 3
261
258
262
259
263
260
264
261
265
262
266
263
267
264
268
265
269
266
270
267
271
268
272
269
273
270
274
271
275
272
Start of
field 4
Reference
sub-carrier phase
color field 4
Figure 9: Interlaced NTSC Video Timing
201-0000-027 Rev. 2.4, 04/12/2001
17
CHRONTEL
CH7008A
ST
AR
TA
RT
OF
VS
YNC
SY
ANALO
ALOG
FIELD 1
620
620
621
621
622
622
623
623
624
624
625
625
1
2
3
4
5
6
7
7
8
8
9
9
10
10
ANALO
ALOG
FIELD 2
308
308
309
309
310
310
311
311
312
312
313
313
314
314
315
31
5
316
31
6
317
31
7
318
31
8
319
31
9
320
32
0
321
32
1
322
32
2
323
32
3
ALOG
ANALO
FIELD 3
620
620
621
621
622
622
623
623
624
624
625
625
1
2
3
4
5
6
7
7
8
8
9
9
10
10
ANALO
ALOG
FIELD 4
308
308
BU
URS
RST
T
B
BLA
LAN
NK
KIN
ING
G
B
INTERVALS
309
309
310
310
311
311
312
312
313
313
314
314
31
5
315
31
6
316
31
7
317
31
8
318
31
9
319
32
0
320
32
1
321
32
2
322
32
3
323
4
3HASE = 135°° RELATIVE TO U
BU
URS
RST
TP
PH
HAS
ASE
E=
=R
REF
EFE
RE
NCE
P
B
ER
ENC
EP
HASE = 135 RELATIVE TO U
PA
AL
SWITC
ITCH
H=
= 0,
0, +
+V
CO
OM
MP
PO
T
P
L SW
VC
ON
NE
E
NT
2N
1H
BU
URS
RST
TP
PH
HAS
ASE
E=
=R
REF
EFE
RE
NCE
P
HA
SE +
0°° =
5°° R
IVE
B
ER
ENC
EP
ASE
+9
90
= 22
225
RE
ELA
LAT
TIV
E TO
TO U
U
PA
AL
SWITC
ITCH
H=
= 1,
1, -- V
VC
CO
OM
MP
P
L SW
PO
ON
NE
EN
NT
T
Figure 10: Interlaced PAL Video Timing
18
201-0000-027 Rev. 2.4, 04/12/2001
CHRONTEL
CH7008A
White
Yellow
26.66
24.66
1.000
0.925
Cyan
Green
21.37
19.37
0.801
0.726
Magenta
Red
16.22
14.22
0.608
0.533
Blue
Black
Blank
11.08
9.08
7.65
0.415
0.340
0.287
Sync
0.00
0.000
Color bars:
Black
Blue
Red
Magenta
V
Green
Cyan
Yellow
mA
White
Color/Level
Figure 11: NTSC Y (Luminance) Output Waveform (DACG = 0)
26.75
24.62
1.003
0.923
Cyan
Green
21.11
18.98
0.792
0.712
Magenta
Red
15.62
13.49
0.586
0.506
Blue
10.14
0.380
Blank/ Black
8.00
0.300
Sync
0.00
0.000
Black
White
Yellow
Color bars:
Blue
Red
Magenta
V
Green
Cyan
Yellow
mA
White
Color/Level
Figure 12: PAL Y (Luminance) Video Output Waveform (DACG = 1)
201-0000-027 Rev. 2.4, 04/12/2001
19
CHRONTEL
CH7008A
0.842
Peak Burst
18.08
0.678
Blank
14.29
0.536
Peak Burst
10.51
0.394
Black
22.44
Blue
Yellow/Blue
Red
0.968
0.938
Magenta
25.80
25.01
Green
Cyan/Red
Green/Magenta
Cyan
V
White
mA
Yellow
Color bars:
Color/Level
3.579545 MHz Color Burst
(9 cycles)
Yellow/Blue
Green/Magenta
Cyan/Red
6.15
0.230
3.57
2.79
0.134
0.105
Figure 13: NTSC C (Chrominance) Video Output Waveform (DACG = 0)
0.897
Peak Burst
19.21
0.720
Blank
15.24
0.572
Peak Burst
11.28
0.423
Black
23.93
Blue
Yellow/Blue
Red
1.032
1.000
Magenta
27.51
26.68
Green
Cyan/Red
Green/Magenta
Cyan
V
Yellow
mA
White
Color bars:
Color/Level
4.433619 MHz Color Burst
(10 cycles)
Yellow/Blue
6.56
0.246
Green/Magenta
Cyan/Red
3.81
2.97
0.143
0.111
Figure 14: PAL C (Chrominance) Video Output Waveform (DACG = 1)
20
201-0000-027 Rev. 2.4, 04/12/2001
CH7008A
CHRONTEL
11.44
0.429
Black
9.08
0.340
Blank
7.65
0.287
Peak Burst
4.45
Black
Peak Burst
Blue
1.000
Red
26.66
Magenta
White
Color bars:
Green
1.233
Cyan
V
32.88
Yellow
mA
Peak Chrome
White
Color/Level
0.145
3.579545 MHz Color Burst
(9 cycles)
Sync
0.00
0.000
Figure 15: Composite NTSC Video Output Waveform (DACG = 0)
0.449
Blank/Black
8.00
0.300
Peak Burst
4.04
0.151
Sync
0.00
0.000
Black
11.97
Blue
Peak Burst
Red
1.003
Magenta
26.75
Green
White
Color bars:
Cyan
V
1.249
Yellow
mA
White
Color/Level
Peak Chrome 33.31
4.433619 MHz Color Burst
(10 cycles)
Figure 16: Composite PAL Video Output Waveform (DACG = 1)
201-0000-027 Rev. 2.4, 04/12/2001
21
CHRONTEL
CH7008A
Register Control
The CH7008 registers are controlled via a serial port interface. The serial port bus uses only serial port clock to
latch data into registers, and does not use any internally generated clocks so that the device can be written to in all
power down modes. The devices retains all register states.
Regarding the CH7008 registers programming, please see Application Note AN-47 for details.
22
201-0000-027 Rev. 2.4, 04/12/2001
CHRONTEL
CH7008A
Registers and Programming
The CH7008 is a fully programmable device, providing for full functional control through a set of registers accessed
from the serial port. The CH7008 contains a total of 37 registers, which are listed in Table 11 and described in detail
under Register Descriptions. Detailed descriptions of operating modes and their effects are contained in the previous
section, Functional Description. An addition (+) sign in the Bits column below signifies that the parameter contains
more than 8 bits, and the remaining bits are located in another register.
Table 11. Register Map
Register
Display Mode
Symbol
Address
DMR
00H
Bits
8
Functional Summary
Display mode selection
Flicker Filter
FFR
01H
6
Flicker filter mode selection
Video Bandwidth
VBW
03H
8
Luma and chroma filter bandwidth selection
Input Data Format
IDF
04H
6
Data format and bit-width selections
Clock Mode
CM
06H
8
Sets the clock mode to be used
Start Active Video
SAV
07H
8+
Active video delay setting
Position Overflow
PO
08H
3
MSB bits of position values
Black Level
BLR
09H
8
Black level adjustment input latch clock edge select
Horizontal Position
HPR
0AH
8+
Enables horizontal movement of displayed image on
TV
Vertical Position
VPR
0BH
8+
Enables vertical movement of displayed image on
TV
Sync Polarity
SPR
0DH
4
Determines the horizontal and vertical sync polarity
Power Management
PMR
0EH
5
Enables power saving modes
Connection Detect
CDR
10H
4
Detection of TV presence
Contrast Enhancement
CE
11H
3
Contrast enhancement setting
PLL M and N extra bits
MNE
13H
5
Contains the MSB bits for the M and N PLL values
PLL-M Value
PLLM
14H
8+
Sets the PLL M value - bits (7:0)
PLL-N Value
PLLN
15H
8+
Sets the PLL N value - bits (7:0)
Buffered Clock
BCO
17H
6
Determines the clock output at pin 41
Subcarrier Frequency
Adjust
FSCI
18H -1FH
4 or 8
each
Determines the subcarrier frequency
PLL and Memory Control
PLLC
20H
6
Controls for the PLL and memory sections
CIV Control
CIVC
21H
5
Control of CIV value
Calculated Fsc Increment
Value
CIV
21H 24H
8 each
Readable register containing the calculated
subcarrier increment value
Version ID
VID
25H
8
Device version number
Test
TR
26H 29H
30
Reserved for test (details not included herein)
Address
AR
3FH
6
Current register being addressed
201-0000-027 Rev. 2.4, 04/12/2001
23
CHRONTEL
CH7008A
Register Descriptions (continued)
Table 12. Non-Macrovision Register Map (Note: MacrovisionTM controls available only by special arrangement)
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00H
IR2
IR1
IRO
VOS1
VOS0
SR2
SR1
SR0
FC1
FC0
FY1
FY0
FT1
FT0
CBW0
01H
02H
03H
FLFF
04H
CVBW
CBW1
DACG
Reserved
YPEAK
YSV1
YSV0
YCV
IDF3
IDF2
IDF1
IDF0
XCM0
PCM1
PCM0
05H
06H
CFRB
M/S*
Reserved
MCP
XCM1
07H
SAV7
SAV6
SAV5
SAV4
SAV3
08H
09H
BL7
SAV2
SAV1
SAV0
SAV8
HP8
VP8
BL6
BL5
BL4
BL3
BL2
BL1
BL0
0AH
HP7
HP6
HP5
HP4
HP3
HP2
HP1
HP0
0BH
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
DES
SYO
VSP
HSP
SCART
Reset*
PD2
PD1
PD0
0CH
0DH
0EH
0FH
10H
YT
11H
CT
CVBST
SENSE
CE2
CE1
CE0
12H
13H
Reserved
Reserved
N9
N8
M8
14H
M7
M6
M5
M4
M3
M2
M1
M0
15H
N7
N6
N5
N4
N3
N2
N1
N0
SHF2
SHF1
16H
17H
SHF0
SCO2
SCO1
SCO0
18H
FSCI31
FSCI30
FSCI29
FSCI28
19H
FSCI27
FSCI26
FSCI25
FSCI24
1AH
FSCI23
FSCI22
FSCI21
FSCI20
1BH
GPIOIN1
GPIOIN0
DVDD2
P-OUTP
FSCI19
FSCl18
FSCl17
FSCl16
1CH
GOENB1
GOENB0
DSM
DSEN
FSCI15
FSCl14
FSCl13
FSCI12
1DH
FSCI11
FSCl10
FSCl9
FSCI8
1EH
FSCI7
FSCI6
FSCI5
FSCI4
1FH
20H
PLLCPl
21H
FSCI2
FSCI1
FSCI0
PLLS
PLL5VD
PLL5VA
MEM5V
CIV25
CIV24
ClVH1
ClVH0
AClV
22H
CIV23
CIV22
CIV21
CIV20
CIV19
CIV18
CIV17
CIV16
23H
CIV15
CIV14
CIV13
CIV12
CIV11
CIV10
CIV9
CIV8
24H
CIV7
CIV6
CIV5
CIV4
CIV3
CIV2
CIV1
CIVO
25H
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
26H
TS3
TS2
TS1
TS0
RSA
BST
NST
TE
MS2
MS1
MSO
MTD
YLM8
CLM8
28H
YLM7
YLM6
YLM5
YLM4
YLM3
YLM2
YLM1
YLM0
29H
CLM7
CLM6
CLM5
CLM4
CLM3
CLM2
CLM1
CLM0
3FH
Reserved
Reserved
AR5
AR4
AR3
AR2
AR1
AR0
27H
24
FSCI3
PLLCAP
201-0000-027 Rev. 2.4, 04/12/2001
CH7008A
CHRONTEL
Register Descriptions (continued)
Address: 00H
Bits: 8
Display Mode Register
Bit:
7
6
5
4
3
2
1
0
Symbol:
IR2
IR1
IR0
VOS1
VOS0
SR2
SR1
SR0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
1
1
0
1
0
1
0
This register provides programmable control of the CH7008 display mode, including input resolution (IR[2:0]),
output TV standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according to the
table below (default is 640x480 input, NTSC output, 7/8’s scaling).
Table 13. Display Modes
Mode
IR[2:0]
VOS
[1:0]
SR
[2:0]
Input Data
Format
(Active
Video)
0
000
00
000
512x384
1
000
00
001
512x384
840x625
PAL
1/1
26.250000
2
000
01
000
512x384
800x420
NTSC
5/4
20.139860
3
000
01
001
512x384
784x525
NTSC
1/1
24.671329
4
001
00
000
720X400
1125X500
PAL
5/4
28.125000
5
001
00
001
720x400
1116x625
PAL
1/1
34.875000
6
001
01
000
720x400
945x420
NTSC
5/4
23.790210
7
001
01
001
720x400
936x525
NTSC
1/1
29.454545
8
010
00
000
640x400
1000x500
PAL
5/4
25.000000
Total
Pixels/Line
x Total
Lines/Frame
Output
Format
Scaling
Pixel Clock
(MHz)
840x500
PAL
5/4
21.000000
9
010
00
001
640x400
1008x625
PAL
1/1
31.5000000
10
010
01
000
640x400
840x420
NTSC
5/4
21.146853
11
010
01
001
640x400
840x525
NTSC
1/1
26.433566
12
010
01
010
640x400
840x600
NTSC
7/8
30.209790
13
011
00
000
640x480
840x500
PAL
5/4
21.000000
14
011
00
001
640x480
840x625
PAL
1/1
26.250000
15
011
00
011
640x480
840x750
PAL
5/6
31.5000000
16
011
01
001
640x480
784x525
NTSC
1/1
24.671329
17
011
01
010
640x480
784x600
NTSC
7/8
28.195804
18
011
01
011
640x480
800x630
NTSC
5/6
30.209790
19
100
00
001
800x600
944x625
PAL
1/1
29.500000
20
100
00
011
800x600
960x750
PAL
5/6
36.0000000
21
100
00
100
800x600
936x836
PAL
3/4
39.000000
22
100
01
011
800x600
1040x630
NTSC
5/6
39.272727
23
100
01
100
800x600
1040x700
NTSC
3/4
43.636364
24
100
01
101
800x600
1064x750
NTSC
7/10
47.832168
25*
101
00
001
720x576
864x625
PAL
1/1
13.500000
26*
101
01
001
720x480
858x525
NTSC
1/1
13.500000
* Interlaced modes of operation. (For those modes, some functions will be bypassed. For details, please contact the
application department.)
201-0000-027 Rev. 2.4, 04/12/2001
25
CHRONTEL
CH7008A
Register Descriptions (continued)
VOS[1:0]
00
01
10
11
Output Format
PAL
NTSC
PAL-M
NTSC-J
Flicker Filter Register
Bit:
7
Symbol: FFR
Address: 01H
Bits: 6
6
5
4
3
2
1
0
Symbol:
FC1
FC0
FY1
FY0
FT1
FT0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
Default:
1
1
0
0
1
0
The flicker filter register provides for adjusting the operation of the various filters used in rendering the on-screen
image. Adjusting settings between minimal and maximal values enables optimization between sharpness and flicker
content. The FC[1:0] bits determine the settings for the chroma channel. The FT[1:0] bits determine the settings for
the text enhancement circuit. The FY[1:0] bits determine the settings for the luma channel. In addition, the Chroma
channel filtering includes a setting to enable the chroma dot crawl reduction circuit.
Note: When writing to register O1H, FY[1:0] is bits 3:2. FT[1:0] is bits 1:0. When reading from the register O1H, FY
[1:0] is bits 1:0 and FT[1:0] is bits 3:2.
Table 14. Flicker Filter Settings
FY[1:0]
Settings for Luma Channel
00
Minimal Flicker Filtering
01
Slight Flicker Filtering
10
Maximum Flicker Filtering
11
Invalid
FT[1:0]
Settings for Text Enhancement Circuit
00
Maximum Text Enhancement
01
Slight Text Enhancement
10
Minimum Text Enhancement
11
Invalid
FC[1:0]
Settings for Chroma Channel
00
Minimal Flicker Filtering
01
Slight Flicker Filtering
10
Maximum Flicker Filtering
11
Enable Chroma DotCrawl Reduction
26
201-0000-027 Rev. 2.4, 04/12/2001
CHRONTEL
CH7008A
Register Descriptions (continued)
Video Bandwidth Register
Bit:
7
6
Symbol:
FLFF
Type:
R/W
Default:
0
0
Symbol: VBW
Address: 03H
Bits: 8
5
4
3
2
1
0
CVBW
CBW1
CBW0
YPEAK
YSV1
YSV0
YCV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
This register enables the selection of alternative filters for use in the luma and chroma channels. There are currently
four filter options defined for the chroma channel, four filter options in the S-Video luma channel and two filter
options in the composite luma channel. The Tables 15 and 16 below show the various settings.
Table 15. Luma Filter Bandwidth
YCV
Luma Composite Video Filter Adjust
0
Low bandwidth
1
High bandwidth
YSV[1:0]
Luma S-Video Filter Adjust
00
Low bandwidth
01
Medium bandwidth
10
High bandwidth
11
Reserved
YPEAK
Disables the Y-peaking circuit
0
Disables the peaking filter in luma s-video channel
1
Enables the peaking filter in luma s-video channel
Table 16. Chroma Filter Bandwidth
CBW[1:0]
Chroma Filter Adjust
00
Low bandwidth
01
Medium bandwidth
10
Med-high bandwidth
11
High bandwidth
Bit 6 (CVBW) outputs the S-Video luma signal on both the S-Video luma output and the CVBS output. A 1 in this
location enables the output of a black and white image on composite video, thereby eliminating the degrading
effects of the color signal (such as dot crawl or false colors), which is useful for viewing text with high accuracy.
Bit 7 (FLFF) controls the flicker filter used in the 7/10’s scaling modes. In these scaling modes, setting FLFF to 1
causes a five line flicker filter to be used. The default setting of 0 uses a four line flicker filter.
201-0000-027 Rev. 2.4, 04/12/2001
27
CHRONTEL
CH7008A
Register Descriptions (continued)
Input Data Format Register
Bit:
7
Symbol: IDF
Address: 04H
Bits: 6
6
5
3
2
1
0
Symbol:
DACG
Reserved
4
IDF3
IDF2
IDF1
IDF0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
0
This register sets the variables required to define the incoming pixel data stream.
Table 17. Input Data Format
IDF[3:0]
Description
0000
Not available
0001
Not available
0010
Not available
0011
Not available
0100
12-bit multiplexed RGB (24-bit color) input (“C” multiplex scheme)
0101
12-bit multiplexed RGB (24-bit color) input (“I” multiplex scheme)
0110
Not available
0111
8-bit multiplexed RGB (16-bit color, 565) input
1000
8-bit multiplexed RGB (15-bit color, 555) input
1001-1111
8-bit multiplexed YCrCb (24-bit color) input (Y, Cr and Cb are multiplexed)
Reserved (bit 5): This bit should be set to 0.
DACG (bit 6): This bit controls the gain of the D/A converters. When DACG=0, the nominal DAC current is 71
µA, which provides the correct levels for NTSC and PAL-M. When DACG=1, the nominal DAC current is 76µA,
which provides the correct levels for PAL and NTSC-J.
Clock Mode Register
Symbol: CM
Address: 06H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
CFRB
M/S*
Reserved
MCP
XCM1
XCM0
PCM1
PCM0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
1
0
0
0
0
The setting of the clock mode bits determines the clocking mechanism used in the CH7008. The clock modes are
shown in the table below. PCM controls the frequency of the P-OUT clock, and XCM identifies the frequency of the
XCLK input clock.
28
201-0000-027 Rev. 2.4, 04/12/2001
CHRONTEL
CH7008A
Register Descriptions (continued)
Note: Although it is possible to set the XCM [1:0] and PCM[1:0] values independent of the input data format, there are
only certain combinations of input data format, XCM and PCM, that will result in valid data being demultiplexed at the
input of the device. Refer to the “Input Data Format Register” for these combinations.
Note: Display modes 25 and 26 must use a 2X multiplexed input data format and a 2X XCLK.
Table 1. Input Data Format Register
XCM[1:0]
PCM[1:0]
XCLK
P-Out
Input Data Modes Supported
00
00
1X
1X
4, 5, 7, 8, 9
00
01
1X
2X
4, 5, 7, 8, 9
00
1X
1X
3X
4, 5, 7, 8, 9
01
00
2X
1X
4, 5, 7, 8, 9
01
01
2X
2X
4, 5, 7, 8, 9
01
1X
2X
3X
4, 5, 7, 8, 9
The Clock Mode Register also contains the following bits:
• MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the
negative edge, one selects the positive edge.
• M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the
14.31818MHz clock is used as a frequency reference to the PLL. In slave mode (0) the XCLK input is used as
a reference to the PLL, and is divided by the value specified by XCM[1:0]. The divide by N and M are forced
to one.
• CFRB (bit 7) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the
subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the
subcarrier to free-run, and should be used when the ACIV bit is set to one.
Start Active Video Register
Symbol: SAV
Address: 07H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
SAV7
SAV6
SAV5
SAV4
SAV3
SAV2
SAV1
SAV0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
0
0
0
This register sets the delay in pixel increments from leading edge of horizontal sync, or the rising edge of data start,
to the start of active video. The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value
contained in the position overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set
anywhere between 0 and 511 pixels. Therefore, in any 2X clock mode, the number of 2X clocks from the leading
edge of sync to the first active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X
clocks from the leading edge of sync to the first active data must be a multiple of three clocks. When using the
DS/BCO pin as a data start input, this register should be set to decimal value 11.
201-0000-027 Rev. 2.4, 04/12/2001
29
CHRONTEL
CH7008A
Register Descriptions (continued)
Position Overflow Register
Bit:
7
6
Symbol: PO
Address: 08H
Bits: 3
5
4
3
2
1
0
Symbol:
SAV8
HP8
VP8
Type:
R/W
R/W
R/W
Default:
0
0
0
This position overflow register contains the MSB values for the SAV, HP and VP values, as follows:
•
•
•
VP8 (bit 0) is the MSB of the vertical position value (see explanation under “Vertical Position Register”).
HP8 (bit 1) is the MSB of the horizontal position value (see explanation under “Horizontal Position
Register”).
SAV8 (bit 2) is the MSB of the start of active video value (see explanation under “Start Active Video
Register”).
Black Level Register
Symbol: BLR
Address: 09H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
BL7
BL6
BL5
BL4
BL3
BL2
BL1
BL0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
1
1
1
1
1
1
1
This register sets the black level. The luminance data is added to this black level, which must be set between 90 and
208, with the default value being 127. Recommended values for NTSC and PAL-M are 127, 105 for PAL and 100
for NTSC-J.
Horizontal Position Register
Symbol: HPR
Address: 0AH
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
HP7
HP6
HP5
HP4
HP3
HP2
HP1
HP0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
0
0
0
The horizontal position register is used to shift the displayed TV image in a horizontal direction (left or right) to
achieve a horizontally centered image on screen. The entire bit field, HP[8:0] is comprised of this register HP[7:0]
plus the MSB value contained in the position overflow register, bit HP8. Increasing this value moves the displayed
image position RIGHT; decreasing this value moves the displayed image position LEFT. Each increment moves the
image position by 4 input pixels.
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CH7008A
Register Descriptions (continued)
Vertical Position Register
Symbol: VPR
Address: 0BH
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
0
0
0
This register is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically centered image on screen. This bit field, VP[8:0] represents the TV line number (relative to the VGA vertical sync)
used to initiate the generation and insertion of the TV vertical interval (i.e., the first sequence of equalizing pulses).
Increasing values delay the output of the TV vertical sync, causing the image position to move UP on the TV screen.
Decreasing values, therefore, move the image position DOWN. Each increment moves the image position by one
TV lines (approximately 4 input lines). The maximum value that should be programmed into the VP[8:0] value is
the number of TV lines minus one, divided by two (262, 312 or 313). When panning the image up, the number
should be increased until (TVLPF-1) /2 is reached; the next step should be to reset the register to zero. When panning the image down the screen, the VP[8:0] value should be decremented until the value zero is reached. The next
step should set the register to (TVLPF-1) /2, and then decrementing can continue. If this value is programmed to a
number greater than (TV lines per frame-1) /2, a TV vertical SYNC will not be generated.
Sync Polarity Register
Bit:
7
Symbol: SPR
Address: 0DH
Bits: 4
6
5
4
3
2
1
0
Symbol:
DES
SYO
VSP
HSP
Type:
R/W
R/W
R/W
R/W
Default:
0
0
0
0
This register provides selection of the synchronization signal input to, or output from, the CH7008.
• HSP (bit 0) is Horizontal Sync Polarity - an HSP value of zero means the horizontal sync is active low and a
value of one means the horizontal sync is active high.
• VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low and a value of
one means the vertical sync is active high.
• SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7008. A
value of one means that H and V sync are output from the CH7008.
• DES (bit 3) is Detect Embedded Sync - a DES value of zero means that H and V sync will be obtained from
the direct pin inputs. A DES value of one means that H and V sync will be detected from the embedded codes
on the pixel input stream. Note that this will only be valid for the YCrCb input modes.
Note: When sync direction is set to be an output, horizontal sync will use a fixed pulse width of 64 pixels and vertical
sync will use a fixed pulse width of 1 line.
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CH7008A
Register Descriptions (continued)
Power Management Register
Bit:
7
6
Symbol: PMR
Address: 0EH
Bits: 5
5
4
3
2
1
0
Symbol:
SCART
Reset*
PD2
PD1
PD0
Type:
R/W
R/W
R/W
R/W
R/W
Default:
0
1
1
0
1
This register provides control of the power management functions, a software reset (Reset*) and the SCART output
enable. The CH7008 provides programmable control of its operating states, as described in the table below.
Table 1. Power Management
PD[2:0]
Operating State
Functional Description
000
Composite Off
CVBS DAC is powered down.
001
Power Down
Most pins and circuitry are disabled (except for the buffered clock outputs
which are limited to the 14MHz output and VCO divided outputs).
010
S-Video Off
S-Video DACs are powered down.
011
Normal (On)
All circuits and pins are active.
1XX
Full Power Down
All circuitry is powered down except serial port interface circuit.
Reset* (bit 3) is soft reset. Setting this bit will reset all circuitry requiring a power on reset, except for this bit itself
and the serial port state machines.
SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7008 will operate normally, outputting Y/C
and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from
the DACs and composite sync from the CSYNC pin.
Note: For complete details regarding the operation of these modes, see the Power Management in Functional Description
sections.
Connection Detect Register
Bit:
7
6
Symbol: CDR
Address: 10H
Bits: 4
5
4
3
2
1
0
Symbol:
YT
CT
CVBST
SENSE
Type:
R
R
R
W
Default:
0
0
0
0
The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or Composite
video outputs. The status bits, YT, CT, and CVBST correspond to the DAC outputs for S-Video (Y and C outputs)
and Composite video (CVBS), respectively. However, the values contained in these status bits are NOT VALID
until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of
outputs, then reading out the applicable status bits. The detection sequence works as follows:
1. Ensure the power management register bits 2-0 are set to 011 (normal mode).
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CH7008A
Register Descriptions (continued)
1. Ensure that the XCLK and XCLK* input pins are receiving clock signals (alternatively, XCLK* can be
connected to the VREF pin).
2. Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that
during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted.
3. Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs
and the reference value expected (Vthreshold = 1.235V). If the measured voltage is below this threshold
value, it is considered connected, if it is above this voltage it is considered unconnected. During this step,
each of the three status bits corresponding to individual analog outputs will be set if they are NOT
connected.
4. Read the status bits. The status bits Y, C and CVBST (corresponding to S-Video Y and C outputs and
composite video) now contain valid information which can be read to determine which outputs are
connected to a TV. Again, a “0” indicates a valid connection, a “1” indicates an unconnected output.
Contrast Enhancement Register
Bit:
7
6
Symbol: CE
Address: 11H
Bits: 3
5
4
3
2
1
0
CE2
CE1
CE0
Type:
R/W
R/W
R/W
Default:
0
1
1
Symbol:
This register provides control of the contrast enhancement feature of the CH7008, according to the table below. At a
setting of 000, the video signal will be pulled towards the maximum black level. As the value of CE[2:0] is
increased, the amount that the signal is pulled towards black is decreased until unity gain is reached at a setting of
011. From this point on, the video signal is pulled towards the white direction, with the effect increasing with
increasing settings of CE[2:0].
Table 18. Contrast Enhancement Function
CE[2:0]
Description (all gains limited to 0-255)
000
Contrast enhancement gain 3 Yout = (5/4)*(Yin-102) = Enhances Black
001
Contrast enhancement gain 2 Yout = (9/8)*(Yin-57)
010
Contrast enhancement gain 1 Yout = (17/16)*(Yin-30)
011
Normal mode Yout = (1/1)*(Yin-0) = Normal Contrast
100
Contrast enhancement gain 1 Yout = (17/16)*(Yin-0)
101
Contrast enhancement gain 2 Yout = (9/8)*(Yin-0)
110
Contrast enhancement gain 3 Yout = (5/4)*(Yin-0)
111
Contrast enhancement gain 4 Yout = (3/2)*(Yin-0) = Enhances White
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CH7008A
Register Descriptions (continued)
256
224
192
160
128
96
64
32
0
0
32
64
96
128
160
192
224 256
Figure 17: Luma Transfer Function at different contrast enhancement settings.
PLL Overflow Register
Bit:
7
6
Symbol: MNE
Address: 13H
Bits: 5
5
4
3
2
1
0
Symbol:
Reserved
Reserved
N9
N8
M8
Type:
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
The PLL Overflow Register contains the MSB bits for the’M’ and ’N’ values, which will be described in the PLL-M
and PLL-N registers, respectively. The reserved bits should not be written to.
PLL M Value Register
Symbol: PLLM
Address: 14H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
M7
M6
M5
M4
M3
M2
M1
M0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
1
0
0
0
0
0
1
The PLL M value register determines the division factor applied to the frequency reference clock before it is input to
the PLL phase detector when the CH7008 is operating in master mode. In slave mode, an external pixel clock is
used instead of the frequency reference, and the division factor is determined by the XCM[3:0] value. This register
contains the lower 8 bits of the complete 9-bit M value.
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CH7008A
Register Descriptions (continued)
PLL N Value Register
Symbol: PLLN
Address: 15H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
N7
N6
N5
N4
N3
N2
N1
N0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
1
0
0
0
0
0
0
0
The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL
phase detector, when the CH7008 is operating in master mode. In slave mode, the value of ‘N’ is always 1. This
register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master mode and is
calculated according to the equation below:
Fpixel = Fref* [(N+2) / (M+2)]
When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table
below
Table 19. M and N Values for Each Mode
Mode
0
VGA Resolution, TV
Standard, Scaling Ratio
512x384, PAL, 5:4
N 10bits
M 9bits
Mode
VGA Resolution, TV
Standard, Scaling Ratio
N 10bits
M 9bits
20
14
640x480, PAL, 1:1
9
4
9
13
4
15
640X480, PAL, 5:6
9
3
1
512x384, PAL, 1:1
2
512X384, NTSC, 5:4
126
89
16
640X480, NTSC, 1:1
110
63
3
512X384, NTSC, 1:1
110
63
17
640X480, NTSC, 7:8
126
63
18
640X480, NTSC, 5:6
190
89
4
720X400, PAL, 5:4
53
26
5
720X400, PAL, 1:1
339
138
19
800X600, PAL, 1:1
647
313
20
800X600, PAL, 5:6
86
33
21
800X600, PAL, 3:4
284
103
6
720X400, NTSC, 5:4
106
63
7
720X400, NTSC, 1:1
70
33
8
640X400, PAL, 5:4
108
61
22
800X600, NTSC, 5:6
94
33
23
800X600, NTSC, 3:4
62
19
9
640X400, PAL, 1:1
9
3
10
640X400, NTSC, 5:4
94
63
24
800X600, NTSC, 7:10
302
89
25
720X576, PAL, 1:1
31
33
26
720X480, NTSC, 1:1
31
33
11
640x400, NTSC, 1:1
22
11
12
640X400, NTSC, 7:8
190
89
13
640X480, PAL, 5:4
20
13
Buffered Clock Output Register
Bit:
7
6
Symbol:
Symbol: BCO
Address: 17H
Bits: 6
5
4
3
2
1
0
SHF2
SHF1
SHF0
SCO2
SCO1
SCO0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
0
When this pin is selected to be an output, the buffered clock output register determines which clock is selected to be
output at the DS/BCO clock output pin and what frequency value is output when a VCO derived signal is output.
The tables below show the possible outputs.
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CH7008A
Register Descriptions (continued)
Table 20. Clock Output Selection
SCO[2:0]
Buffered Clock Output
000
14MHz crystal
001
(for test use only)
010
VCO divided by K3 (see Table 21)
011
Field ID signal
100
(for test use only)
101
(for test use only)
110
TV horizontal sync (for test use only)
111
TV vertical sync (for test use only)
Table 21. K3 Selection
SHF[2:0]
K3
000
2.5
010
3.5
011
4
100
4.5
101
5
110
6
111
7
Subcarrier Value Registers
Bit:
7
6
Symbol: FSCI
Address: 18H - 1FH
Bits: 4 or 8 each
3
2
1
0
Symbol:
5
4
FSCI#
FSCI#
FSCI#
FSCI#
Type:
R/W
R/W
R/W
R/W
Default:
The lower four bits of registers 18H through 1FH contain a 32-bit value which is used as an increment value for the
ROM address generation circuitry. The bit locations are specified as the following:
Register
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Contents
FSCI[31:28]
FSCI[27:24]
FSCI[23:20]
FSCI[19:16]
FSCI[15:12]
FSCI[11:8]
FSCI[7:4]
FSCI[3:0]
Register Descriptions (continued)
When the CH7008 is operating in the master clock mode, the tables below should be used to set the FSCI registers.
When using these values, the ACIV bit in register 21H should be set to “0” and the CFRB bit in register 06H should
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CH7008A
CHRONTEL
be set to “1”.
Table 22. FSCI Values (525-Line Modes)
Mode
NTSC
“Normal Dot Crawl”
NTSC
“No Dot Crawl”
PAL-M
“Normal Dot Crawl”
2
763,363,328
763,366,524
762,524,467
3
623,153,737
623,156,346
622,468,953
6
574,429,782
574,432,187
573,798,541
7
463,962,517
463,964,459
463,452,668
10
646,233,505
646,236,211
645,523,358
11
516,986,804
516,988,968
516,418,687
12
452,363,454
452,365,347
451,866,351
16
623,153,737
623,156,346
622,468,953
17
545,259,520
545,261,803
544,660,334
18
508,908,885
508,911,016
508,349,645
22
521,957,831
521,960,016
521,384,251
23
469,762,048
469,764,015
469,245,826
24
428,554,851
438,556,645
428,083,911
26
569,408,543
569,410,927
568,782,819
Table 23. FSCI Values (625-Line Modes)
Mode
PAL
“Normal Dot Crawl”
PAL-N
“Normal Dot Crawl”
0
806,021,060
651,209,077
1
644,816,848
520,967,262
4
601,829,058
486,236,111
5
485,346,014
392,125,896
8
677,057,690
547,015,625
9
537,347,373
434,139,385
13
806,021,060
651,209,077
14
644,816,848
520,967,262
15
537,347,373
434,139,385
19
645,499,916
521,519,134
20
528,951,320
427,355,957
21
488,262,757*
394,482,422
25
705,268,427
569,807,942
When the CH7008 is operating in the slave clock mode, the ACIV bit in register 21H should be set to “1” and the
CFRB bit in register 06H should be set to “0”.
*Note: For reduced cross-color and cross-luminance artifacts, a value of 488,265,597 can be used with CFRB = "0"
& ACIV = "0".
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CHRONTEL
CH7008A
Register Descriptions (continued)
Symbol:
Address: 1BH
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
GPIOIN1
GPIOIN0
DVDD2
P-OUTP
FSCI19
FSCI18
FSCI17
FSCI16
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
0
0
0
Register 1BH, bit 4 (P-OUTP) controls the polarity of the P-OUT pin.
Register 1BH, bit 5 controls the P-OUT drive level, and should be set to 0 when DVDD2 is 1.8V, and set
to 1 when DVDD2 is 3.3V.
Register 1BH, bits 7 and 6 control the GPIO pins. When the corresponding GOENB bits are low, these
registers values are driven out of the GPIO pins. When the corresponding GOENB bits are high, these
registers values can be read to determine the level forced into the GPIO pins.
Symbol:
Address: 1CH
Bits: 6
Bit:
7
6
5
4
3
2
1
0
Symbol:
GOENB1
GOENB0
DSM
DSEN
FSCI15
FSCI14
FSCI13
FSCI12
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
1
1
1
1
0
0
0
0
Register 1CH, bit 4 controls whether the Data Start pin or the Horizontal Sync pin is used to determine the
start of active video. When this bit is low, the pin continues to operate as the BCO pin described in the
BCO register section. When this bit is high the pin becomes an input for the Data Start signal. A value of
0 is recommended.
Register 1CH, bit 5 determines how the Data Start input is used. A value of 1 is recommended.
Register 1CH, bits 7and 6 control the GPIO pins direction. When a GOENB bit is low, the corresponding
GPIO pin is an output pin. When a GOENB bit is high, the corresponding GPIO pin can be read to determine the level forced into it.
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CH7008A
Register Descriptions (continued)
PLL Control Register
Bit:
7
Symbol: PLLC
Address: 20H
Bits: 6
6
5
4
3
2
1
0
Symbol:
PLLCPI
PLLCAP
PLLS
PLL5VD
PLL5VA
MEM5V
Type:
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
0
1
0
1
0
The following PLL and memory controls are available through the PLL control register:
MEM5V
MEM5V should be set to 0 when DVDD is 3.3 volts, and 1 when DVDD is 5 volts.
PLL5VA
PLL5VA is set to 1 when AVDD is 5 volts.
PLL5VD
PLL5VD is set to 1 when DVDD is 5 volts. A value of 0 is used when DVDD is 3.3 volts (default).
PPLLS
When the PLL5VA is 1 PLLS should be 1. When PLL5VA is 0 PLLS should be 0.
PLLCAP
PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs
Mode is shown below.
PLLCPI
The default value should be used.
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CHRONTEL
CH7008A
Register Descriptions (continued)
Table 26. PLL Capacitor Setting
40
Mode
PLLCAP
Value
0
1
1
1
2
1
3
0
4
1
5
0
6
1
7
1
8
0
9
1
10
1
11
1
12
0
13
1
14
1
15
1
16
0
17
0
18
0
19
0
20
1
21
0
22
1
23
1
24
0
25
1
26
1
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CH7008A
CIV Control Register
Bit:
7
Symbol: CIVC
Address: 21H
Bits: 5
6
5
4
3
2
1
0
Symbol:
CIV25
CIV24
CIVH1
CIVH0
ACIV
Type:
R
R
R/W
R/W
R/W
Default:
0
0
0
0
1
The following controls are available through the CIV control register:
ACIV
When the automatic calculated increment value is 1, the number calculated and present at the CIV
registers will automatically be used as the increment value for subcarrier generation, removing the
need for the user to read the CIV value and write in a new FSCI value. Whenever this bit is set to
1, the subcarrier generation must be forced to free-run mode (CFRB = 0).
CIVH[1:0]
These bits control the hysteresis circuit which is used to calculate the CIV value.
CIV[25:24]
See descriptions in the next section.
Calculated Increment Value Register
Symbol: CIV
Address: 22H - 24H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
CIV#
CIV#
CIV#
CIV#
CIV#
CIV#
CIV#
CIV#
Type:
R
R
R
R
R
R
R
R
Default:
0
0
0
0
0
0
0
0
The CIV registers 22H through 24H contain a 26-bit value, which is the calculated increment value that should be
used as the upper 26 bits of FSCI. This value is determined by a comparison of the pixel clock and the 14MHz
clock. The bit locations and calculation of CIV are specified as the following:
Register
Contents
21H
CIV[25:24]
22H
CIV[23:16]
23H
CIV[15:8]
24H
CIV[7:0]
Version ID Register
Symbol: VID
Address: 25H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Type:
R
R
R
R
R
R
R
R
Default:
0
1
0
0
0
0
0
0
This read-only register contains a 8-bit value indicating the identification number assigned to this version of the
CH7008. The default value shown is pre-programmed into this chip and is useful for checking for the correct
version of this chip, before proceeding with its programming.
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CHRONTEL
CH7008A
Address Register
Symbol: AR
Address: 3FH
Bits: 6
Bit:
7
6
5
4
3
2
1
0
Symbol:
Reserved
Reserved
AR5
AR4
AR3
AR2
AR1
AR0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
Default:
X
X
X
X
X
X
The Address Register points to the register currently being accessed.
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CH7008A
Electrical Specifications
Table 27. Absolute Maximum Ratings
Symbol
Description
VDD relative to GND
Input voltage of all digital pins1
Min
Typ
Max
Units
- 0.5
7.0
V
GND - 0.5
VDD + 0.5
V
TSC
Analog output short circuit duration
TAMB
Ambient operating temperature
- 55
TSTOR
Storage temperature
- 65
TJ
Junction temperature
Vapor phase soldering (one minute)
220
°C
TVPS
Indefinite
Sec
85
°C
150
°C
150
°C
Notes:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated under the normal operating condition of this specification is not recommended.
Exposure to absolute maximum rating conditions for extended periods my affect reliability.
2. The device is fabricated using high-performance CMOS technology. It should be handled as an ESD
sensitive device. Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can
induce destructive latch.
Table 28. Recommended Operating Conditions
Symbol
VDD
Min
Typ
Max
Units
DAC power supply voltage
Description
4.75
5.00
5.25
V
AVDD
Analog supply voltage
4.75
5.00
5.25
DVDD
Digital supply voltage
3.1
3.3
3.6
DVDD2
Digital supply voltage (P-OUT pin) VGA controller
interface = 1.8V
1.7
1.8
1.9
V
DVDD2
Digital supply voltage (P-OUT pin) VGA controller
interface = 3.3V
3.1
3.3
3.6
V
RL
Output load to DAC outputs
Ω
37.5
Table 29. Electrical Characteristics (Operating Conditions: TA = 0oC - 70oC, VDD = 5V ± 5%)
Description
Video D/A resolution
Min
9
Typ
Max
Units
9
9
Bits
33.89
Full scale output current
mA
10
Video level error
%
VDD & AVDD (5V) current (simultaneous S-Video & composite
outputs)
105
mA
DVDD (3.3V) current
45
mA
4
DVDD2 (1.8V) current (15pF load)
Total power down current
201-0000-027 Rev. 2.4, 04/12/2001
0.06
mA
mA
43
CHRONTEL
CH7008A
Timing Information
SYNC-SLAVE MODE
P-OUT
VOH
VOL
t1
t1
t2
XCLK
VOH
VOL
XCLK*
VOH
VOL
t4
t3
D[11:0]
VOH
P0a
P0b
P1a
P1b
P2a
VOL
t3
DS
P2b
t5
t4
VOH
VOL
t3
H
VOH
64 PIXELS
VOL
V
VOH
1 VGA
Line
VOL
t5
Symbol
t5
Parameter
Min
Typ
Max
Unit
1.7
3.6
V
DVDD2
Digital I/O Supply Voltage
VOH
Output High level of interface signals
DVDD2 - 0.2
DVDD2 + 0.2
V
VOL
Output Low level of interface signals
-0.2
0.2
V
t1
P-OUT rise/fall time w/15pF load, VREF = 1.65 V
t2
XCLK & XCLK* rise/fall time w/15pF load
7
ns
Setup time:
Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DS = VREF)
Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DS = VREF)
1.5
ns
t3
Hold time:
Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DS = VREF)
Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DS = VREF)
1.5
ns
t4
t5
D[11:0], H, V & DS rise/fall time w/15pF load
44
3
1
3
3
ns
ns
201-0000-027 Rev. 2.4, 04/12/2001
CHRONTEL
CH7008A
SYNC-MASTER MODE
P-OUT
VOH
VOL
H
t1
t7
VOL
V
t1
t6
VOH
64 PIXELS
VOH
1 VGA
Line
VOL
t5
t5
t2
XCLK
VOH
VOL
XCLK*
VOH
VOL
t4
t3
D[11:0]
VOH
P0a
P0b
P1a
P1b
P2a
VOL
DS
P2b
t5
VOH
VOL
t3
Symbol
Parameter
Min
Typ
Max
Unit
1.7
3.6
V
DVDD2
Digital I/O Supply Voltage
VOH
Output High level of interface signals
DVDD2 - 0.2
DVDD2 + 0.2
V
VOL
Output Low level of interface signals
-0.2
0.2
V
t1
P-OUT rise/fall time w/15pF load, VREF = 1.65 V
t2
XCLK & XCLK* rise/fall time w/15pF load
Setup time:
Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DS = VREF)
Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DS = VREF)
1.5
ns
t3
Hold time:
Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DS = VREF)
Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DS = VREF)
1.5
ns
t4
t5
D[11:0], H, V & DS rise/fall time w/15pF load
t6
Hold time:
P-OUT to HSYNC, VSYNC delay
1
t7
(P-OUT=VREF) to (XCLK =XCLK*) delay
2
201-0000-027 Rev. 2.4, 04/12/2001
3
1
3
ns
7
3
1.5
ns
ns
2.5
ns
9
ns
45
CHRONTEL
CH7008A
Table 30. Digital Inputs / Outputs
Symbol
Description
Max
Unit
0.4
V
2.7
VDD + 0.5
V
Serial Port (SC, SD) Input
Low Voltage
GND-0.5
1.4
V
VDATAIH
D[0-11] Input
High Voltage
Vref+0.25
DVDD+0.5
V
VDATAIL
D[0-11] Input
Low Voltage
GND-0.5
Vref-0.25
V
VSDOL
SD (serial port data) Output
Low Voltage
VSPIH
Serial Port (SC, SD) Input
High Voltage
VSPIL
Test Condition
Min
IOL = 2.0 mA
VP-OUTOH
P-OUT Output
High Voltage
IOL = - 400 µA
VP-OUTOL
P-OUT Output
Low Voltage
IOL = 3.2 mA
Typ
2.8
V
0.2
V
Note:
VDATA - refers to all digital pixel and clock inputs.
VP-OUT - refers to pixel data output Time - Graphics.
46
201-0000-027 Rev. 2.4, 04/12/2001
CH7008A
CHRONTEL
Package Dimensions
44-pin PLCC
J
PIN 1
IDENTIFIER
G
F
TOP
VIEW
BOTTOM
VIEW
A B
K
C
A
LEAD
CO-PLANARITY
.004 “
B
Table of Dimensions (inches, unless specified)
No. of Leads
SYMBOL
B
A
J
G
F
K
C
0.685
0.695
0.650
0.656
0.020
–
0.050
0.013
0.021
0.590
0.630
0.165
0.180
44 (10 X 10 mm)
Millimeters
MIN
MAX
201-0000-027 Rev. 2.4, 04/12/2001
47
CHRONTEL
CH7008A
44-pin TQFP (1.4 mm)
A
B
I
1
A B
H
C
D
J
F
LEAD
E
.004
G
Table of Dimensions
No. of Leads
SYMBOL
A
B
C
D
E
F
G
H
I
J
0.17
7°
0.0067
7°
44 (10 x 10 mm)
Millimeters
Inches
48
MIN
11.80
9.90
MAX
12.20
10.10
MIN
0.465
0.390
MAX
0.480
0.398
0.80
0.031
0.30
1.35
0.05
0.40
1.45
0.15
0.012
0.0531
0.00197
0.016
0.0571
0.0059
1.016
0.040
0.50
0.75
0°
0.0197
0.0295
0°
201-0000-027 Rev. 2.4, 04/12/2001
CHRONTEL
CH7008A
ORDERING INFORMATION
Part number
Package type
Number of pins
Voltage supply
CH7008-V
PLCC
44
3.3V/5V
CH7008-T
TQFP
44
3.3V/5V
Chrontel
2210 O’Toole Avenue, Suite 100,
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: sales@chrontel.com
2001 Chrontel, Inc. All Rights Reserved.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE
SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably
expect to result in personal injury or death. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not
responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no
liability for errors contained in this document. Printed in the U.S.A.
201-0000-027 Rev. 2.4, 04/12/2001
49