CR16MHS9/CR16MHS5 CompactRISC 16-Bit Reprogrammable/ROM Microcontroller 1.0 General Description The CR16MHS9 and CR16MHS5 CompactRISC™ microcontrollers are general-purpose 16-bit microcontrollers based on a Reduced Instruction Set Computer (RISC) architecture. The device operates as a complete microcomputer with all system timing, interrupt logic, flash program memory or ROM memory, RAM, EEPROM data memory, and I/O ports included on-chip. It is ideally suited to a wide range of embedded controller applications because of its high performance, on-chip integrated features and low power consumption, resulting in decreased system cost. The CR16MHS9 and CR16MHS5 offer the high performance of a RISC architecture while retaining the advantages of a traditional Complex Instruction Set Computer (CISC): compact code, on-chip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 20 million instructions per second (MIPS) at a clock rate of 20 MHz. Block Diagram Fast Osc Slow Osc Processing Unit CR16B Core Clock Generator Power-on-Reset Core Bus Bus Interface Unit Peripheral Bus Controller 48k Flash Program/ ROM Memory 2 kbyte RAM 640 Bytes EEPROM Data Memory boot ROM Interrupt Power-Save Control Management (ICU) WATCHDOG Peripheral Bus I/O µWire/SPI Two USARTs Two MFTs A/D Note: Not all peripherals shown above will be contained in every device. CompactRISC™ is a trademark of National Semiconductor Corporation. ©2001 National Semiconductor Corporation MIWU Two Analog Comparators Real-Time Timer CR16MHS9/CR16MHS5 CompactRISC 16-Bit Reprogrammable/ROM Microcontroller January 2001 CR16MHS9/CR16MHS5 1.0 General Description (Continued) • All CR16MHS9 and CR16MHS5 devices have 48 kbytes of reprogrammable flash program memory or ROM Memory, 1.5 kbytes of ISP memory, 2 kbytes of static RAM, and 640 bytes of non-volatile EEPROM data memory. The 80-pin device has two USARTs, two 16-bit multi-function timers, one SPI/MICROWIRE-PLUS™ serial interface, an 8-channel A/D converter, two analog comparators, WATCHDOG™ protection mechanism, and up to 48 general-purpose I/O pins. All CR16MHS9 and CR16MHS5 devices operate with a highfrequency crystal as the main clock source. Some packages allow the device to operate with either the main clock source or with a slow (32.768 KHz) oscillator in Power Save mode. The device supports several Power Save modes which are combined with multi-source interrupt and wake-up capabilities. Powerful cross-development tools are available from National Semiconductor and third party suppliers to support the development and debugging of application software for the CR16MHS9 and CR16MHS5 . These tools let you program the application software in C and are designed to take full advantage of the CompactRISC architecture. 2.0 • • • • • • Features CPU Features — Fully static core, capable of operating at any rate from 0 to 20 MHz (4 MHz minimum in active mode) — 50 ns instruction cycle time with a 20 MHz external clock frequency — Multi-source vectored interrupts (internal, external, and on-chip peripheral) — On-chip power-on reset On-Chip Memory — 48 kbytes of flash program memory or ROM memory — For flash program memory, 1.5 kbytes of ISP memory is used to store boot loader code — 2 kbytes of static RAM data memory — 640 bytes of non-volatile EEPROM data memory, word-programmable On-Chip Peripherals — Two Universal Synchronous/Asynchronous Receiver/ Transmitter (USART) devices — Programmable Idle Timer and real-time timer — Two dual 16-bit multi-function timers (MFT1 and MFT2) — SPI/MICROWIRE-PLUS serial interface — 8-channel, 8-bit Analog-to-Digital (A/D) converter with external voltage reference, programmable sampleand-hold delay, and programmable conversion frequency — Integrated WATCHDOG logic I/O Features — Up to 48 general-purpose I/O pins (shared with on-chip peripheral I/O pins) — Programmable I/O pin characteristics: TRI-STATE output, push-pull output, weak pull-up input, high-impedance input — Software-configurable Schmitt triggers on inputs Power Supply — 4.5V to 5.5V single-supply operation Temperature Range — –40°C to +85°C 2 — –40°C to +125°C Development Support — Real-time emulation and full program debug capabilities available — CompactRISC tools provide C programming and debugging support Programmable devices NSID Speed (MHz) Flash (kByte) EEPROM Data Memory (Bytes) SRAM (kBytes) USART Timer I/Os Temp. Range Peripherals Package Type CR16MHS9VJEx 20 48 640 2 2 2 48 E, I ADC, Comparators 80PQFP ROM devices NSID Speed (MHz) ROM (kByte) EEPROM Data Memory (Bytes) SRAM (kBytes) USART Timer I/Os Temp. Range Peripherals Package Type CR16MHS5VJExy 20 48 640 2 2 2 48 E, I ADC, Comparators 80PQFP Note: • Suffix x in the NSID is defined below: Temperature Ranges: E = Extended I = Industrial • -40°C to +125°C is represented when x is 7 -40°C to +85°C is represented when x is 8 Suffix y in the NSID defines the ROM code. Note: All devices contains Clock and Reset, MICROWIRE/ SPI, Multi-Input Wake-Up (MIWU), Power Management (PMM), and the Real-Time Timer and Watchdog (TWM) modules. 3 CR16MHS9/CR16MHS5 CR16 CompactRISC microcontroller Family Selection Guide CR16MHS9/CR16MHS5 3.0 Device Overview The 640 bytes of EEPROM data memory are used for nonvolatile storage of data, such as configuration settings entered by the end-user. The CPU reads or writes this memory by using ordinary byte-wide or word-wide memory access commands. After the CPU performs a write to this memory, the on-chip hardware completes the EEPROM programming in the background. A register status bit indicates the status of the EEPROM programming operation. The CR16MHS9 and CR16MHS5 CompactRISC microcontrollers are complete microcomputers with all system timing, interrupt logic, program memory, data memory, and I/O ports included on-chip, making it well-suited to a wide range of embedded controller applications. The block diagram on page 1 of the data sheet shows the major on-chip components of the CR16MHS9. 3.1 CR16B CPU CORE The CR16MHS9 and CR16MHS5 use the CR16B CPU core module. This is the same core used in other CompactRISC family members. There is a factory programmed boot memory used to store In-System-Programming (ISP) code. (this code allows programming of the program memory via one of the USART interfaces in the final application.) The high performance of the CPU core results from the implementation of a pipelined architecture with a two-bytes-percycle pipelined system bus. As a result, the CPU can support a peak execution rate of one instruction per clock cycle. For the flash program memory, the CR16MHS9 device internally generates the necessary voltages for programming. No additional power supply is required. 3.3 Compared with conventional RISC processors, the CR16MHS9 and CR16MHS5 differs in the following ways: • • • • • Each CR16MHS9 device has 48 software-configurable I/O pins, organized into six 8-pin ports called Port B, Port C, Port F, Port G, Port L, and Port I. Each pin can be configured to operate as a general-purpose input or general-purpose output. In addition, many I/O pins can be configured to operate as a designated input or output for an on-chip peripheral module such as the USART, timer, A/D converter, or MICROWIRE/SPI interface. The CPU core uses on-chip rather than external memory. This eliminates the need for large and complex bus interface units. Most instructions are 16 bits, so all basic instructions are just two bytes long. (Additional bytes are sometimes required for immediate values, so instructions can be two or four bytes long.) Non-aligned word access is allowed. Each instruction can operate on 8-bit or 16-bit. Most embedded systems face EMI and noise constraints that limit clock speed to these lower ranges. A lower clock speed means a simpler, less costly silicon implementation. The instruction pipeline uses three stages. A smaller pipeline eliminates the need for costly branch prediction mechanisms and bypass registers, while maintaining adequate performance for typical embedded controller applications. 3.2 INPUT/OUTPUT PORTS The I/O pin characteristics are fully programmable. Each pin can be configured to operate as a TRI-STATE output, pushpull output, weak pull-up input, or high-impedance input. Input pins can be software-configured to use Schmitt triggers for noise resistance. 3.4 BUS INTERFACE UNIT The Bus Interface Unit (BIU) controls the interface between the on-chip modules to the internal core bus. It determines the configured parameters for bus access (such as the number of wait states for memory access) and issues the appropriate bus signals for each requested access. MEMORY The BIU uses a set of control registers to determine how many wait states and hold states are to be used when accessing EEPROM memory. Upon start-up of the device, these registers must be programmed with appropriate values so that the minimum allowable number states is used. This number varies with the clock frequency and the type of onchip device being accessed. The CompactRISC architecture supports a uniform linear address space of 2 megabytes. The CR16MHS9 and CR16MHS5 implementation of this architecture uses only the lowest 64 kbytes of address space. Four types of on-chip memory occupy specific intervals within this address space: 48 kbytes of flash program memory, 1.5 kbytes of ISP memory, 2 kbytes of static RAM, and 640 bytes of EEPROM data memory. 3.5 INTERRUPTS The 48 kbytes of flash program memory are used to store the application program. It has security features to prevent unintentional programming and to prevent unauthorized access to the program code. This memory can be programmed either with CR16MHS9 plugged into an EPROM programmer unit (external programming) or with the CR16MHS9 installed in the application system (in-system programming). The Interrupt Control Unit (ICU) receives interrupt requests from internal and external sources and generates interrupts to the CPU. An interrupt is an event that temporarily stops the normal flow of program execution and causes a separate interrupt service routine to be executed. After the interrupt is serviced, CPU execution continues with the next instruction in the program following the point of interruption. The 2 kbytes of static RAM are used for temporary storage of data and for the program stack and interrupt stack. Read and write operations can be byte-wide or word-wide, depending on the instruction executed by the CPU. Each memory access requires one clock cycle; no wait cycles or hold cycles are required. Interrupts from the timers, USARTs, MICROWIRE/SPI interface, multi-input wake-up, and A/D converter are all maskable interrupts; they can be enabled or disabled by the software. There are 16 of these maskable interrupts, organized into 16 predetermined levels of priority. 4 3.6 MULTI-INPUT WAKE-UP The Multi-Input Wake-up (MIWU) module can be used for either of two purposes: to provide inputs for waking up (exiting) from the HALT, IDLE, or Power Save mode; or to provide general-purpose edge-triggered maskable interrupts from external sources. This eight-channel module generates one combined interrupt to the CPU based on the signals received on its eight input channels. Channels can be individually enabled or disabled, and programmed to respond to positive or negative edges. 3.7 DUAL CLOCK AND RESET The Dual Clock and Reset (CLK2RES) module generates a high-speed main system clock from an external crystal network. It also provides the main system reset signal and a power-on reset function. 3.10 REAL-TIME TIMER AND WATCHDOG The Timing and Watchdog Module (TWM) generates the clocks and interrupts used for timing periodic functions in the system. It also provides Watchdog protection against software errors. The module operates on the slow (32.768 KHz) clock. The real-time timer generates a periodic interrupt to the CPU at a software-programmed interval. This can be used for realtime functions such as a time-of-day clock. The Watchdog is designed to detect program execution errors such as an infinite loop or a “runaway” program. Once Watchdog operation is initiated, the application program must periodically write a specific value to a Watchdog register, within specific time intervals. If the software fails to do so, a Watchdog error is triggered, which resets the device. 3.11 USART In the 80-pin package, the module also generates a slow system clock (32.768 KHz) from another external crystal network. The slow clock is used for operating the device in power-save mode. The USART is a Universal Synchronous/Asynchronous Receiver-Transmitter, a device used for serial communications. It supports a wide range of programmable baud rates and data formats, and handles parity generation and several error detection schemes. The baud rate is generated on-chip, under software control. 3.8 3.12 POWER MANAGEMENT MICROWIRE/SPI The Power Management Module (PMM) improves the efficiency of the CR16MHS9 and CR16MHS5 devices by changing the operating mode (and therefore the power consumption) according to the current level of activity. The MICROWIRE/SPI (MWSPI) interface module supports asynchronous serial communications with other devices that conform to MICROWIRE or Serial Peripheral Interface (SPI) specifications. The CR16MHS9 and CR16MHS5 devices can operate in any of four power modes: The MICROWIRE interface allows several devices to communicate over a single system consisting of three wires: serial in, serial out, and shift clock. At any given time, one device on the MICROWIRE interface operates as the master, while all other devices operate as slaves. An 80-pin CR16MHS supports the full set of slave select and Ready lines for multi-slave implementation. • • • • Active: The device operates at full speed using the highfrequency clock. All device functions are fully operational. Power Save: The device operates at reduced speed using the slow clock. The CPU and some modules can continue to operate at this low speed. IDLE: The device is inactive except for the Power Management Module and Timing and Watchdog Module, which continue to operate using the slow clock. HALT: The device is inactive but still retains its internal state (RAM and register contents). 3.9 MULTI-FUNCTION TIMER The Multi-Function Timer (MFT16) module contains two independent timer/counter units called MFT1 and MFT2, each containing a pair of 16-bit timer/counter registers. Each timer/ counter unit can be configured to operate in any of the following modes: • • • Processor-Independent Pulse Width Modulation (PWM) mode, which generates pulses of a specified width and duty cycle, and which also provides a general-purpose timer/counter Dual Input Capture mode, which measures the elapsed time between occurrences of external events, and which also provides a general-purpose timer/counter Dual Independent Timer mode, which generates system timing signals or counts occurrences of external events 5 3.13 A/D CONVERTER The A/D Converter (ADC) module is an 8-channel multiplexed-input analog-to-digital converter. The A/D Converter receives an analog voltage signal on an input pin and converts the analog signal into an 8-bit digital value using successive approximation. The CPU can then read the result from a memory-mapped register. The module supports four automated operating modes, providing single-channel or scanned 4-channel operation in single or continuous mode. The 80-pin device has a separate pin, Vref, for the A/D reference voltage. 3.14 ANALOG COMPARATORS The Dual Analog Comparator (ACMP2) module contains two independent analog comparators with all necessary control logic. Each comparator unit compares the analog input voltages applied to two input pins and determines which voltage is higher. The CPU uses a memory-mapped register to control the comparator and to obtain the comparison results. The comparison result can also be applied to comparator output pins. CR16MHS9/CR16MHS5 The highest-priority interrupt is the Non-Maskable Interrupt (NMI), which is generated by a signal received on the NMI input pin. CR16MHS9/CR16MHS5 3.15 4.0 DEVELOPMENT SUPPORT A powerful cross-development tool set is available from National Semiconductor and third parties to support the development and debugging of application software for the CR16MHS9 and CR16MHS5 . The tool set lets you program the application software in C and is designed to take full advantage of the CompactRISC architecture. Memory Map The CompactRISC architecture supports a uniform linear address space of 2 megabytes. The device implementation of this architecture uses only the lowest 64 kbytes of address space, ranging from 0000 to FFFF hex. Table 1 There are In-System Emulation (ISE) devices available for the CR16MHS9 and CR16MHS5 from iSYSTEM™, as well as lower-cost evaluation boards. See your National Semiconductor sales representative for current information on availability of various features of emulation equipment and evaluation boards. Device Memory Map Address Range (hex) 6 Description 0000-BFFF Flash Program Memory (48 kbytes) DA00-DFF7 ISP Memory (1.5 kbytes) DFF8-DFFF Program ROM control/status E000-E7FF Static RAM (2 kbytes) F000-F27F EEPROM Data Memory (640 bytes) F900-F930 Device configuration registers FB00-FB06 Port B registers FB10-FB16 Port C registers FC40-FC88 Clock, Power Management, and Wake-up registers FCA0-FCA8 Port G registers FD20-FD28 Port F registers FE00-FE0C Interrupt registers FE40-FE4E USART 1 registers FE60-FE68 MICROWIRE registers FE80-FE8E USART 2 registers FEE0-FEE8 Port I registers FF00-FF08 Port L registers FF20-FF2A Timer and WATCHDOG registers FF40-FF50 T1 Timer registers FF60-FF70 T2 Timer registers FFC0-FFD0 A/D Converter registers FFE0-FFE0 Analog Comparator register Device Pinouts x represents 7, or 8 PB4 PB5 PB6 PB7 PL2 PL3 NC PL4 PL5 NC y represents ROM codes; for programmable devices, leave out y. PL6 PL7 GND Vcc GND NC PC0 PC1 PC2 PC3 The CR16MHS9 and CR16MHS5 are available in the following package: 1 PC4 PB3 21 PC5 PB2 PC6 PB1 PC7 PB0 RESET NC NC ENV0 CLKOUT2 PL1 ENV1 PL0 PG7 NC PG6 GND PG5 Vcc PG4 GND PG3 AGND PG2 AVcc PG1 Vref PG0 NC NC PI7 PF7 PI6 PF6 PI5 61 PF5 Top View Order Number CR16MHS9VJEx, CR16MHS5VJExy See NS Package Number VJE80A 7 PI3 PI2 PI1 PI0 NC NC X2CKI X2CKO GND Vcc GND X1CKI X1CKO NC NMI PF0 PF1 PF2 PF3 PF4 41 PI4 CR16MHS9/CR16MHS5 5.0 CR16MHS9/CR16MHS5 CompactRISC 16-Bit Reprogrammable/ROM Microcontroller 6.0 Physical Dimension inches (millimeters) unless otherwise noted 80 Lead Molded Plastic Quad Flat Package Order Number CR16MHS9VJEx, CR16MHS5VJExy See NS Package Number VJE80A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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