CXA3627N All Band Tuner IC with On-chip PLL Description The CXA3627N is a monolithic TV tuner IC which integrates local oscillator and mixer circuits for VHF band, local oscillator and mixer circuits for UHF band, an IF amplifier and a tuning PLL onto a single chip, enabling further miniaturization of the tuner. Features • Low power consumption (5V, 63mA typ.) • Low noise figure, low distortion characteristics • High gain/low gain selectable • Supports IF double-tuned/adjacent channel trap • Balanced oscillator circuits with excellent oscillation stability • On-chip PLL supports I2C bus 30 pin SSOP (Plastic) Absolute Maximum Ratings • Supply voltage VCC • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation PD • On-chip high voltage drive transistor for charge pump • Frequency step selectable from 31.25, 50 or 62.5kHz (when using a 4MHz crystal) • Low-phase noise synthesizer • On-chip 4-output band switch (output voltage: 5V, current capacity: 13mA) • 30-pin SSOP small package • UHF band switch output switchable Operating Conditions Supply voltage VCC –0.3 to +5.5 –25 to +75 –55 to +150 580 V °C °C mW 4.75 to 5.30 V Applications • TV tuners • VCR tuners • CATV tuners Structure Bipolar silicon monolithic IC Note: This IC has pins whose electrostatic discharge strength is weak as the operating frequency is high and the high-frequency process is used for this IC. Take care of handling the IC. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E02715A2Y-PS CXA3627N Block Diagram and Pin Configuration 30 IFOUT IF AMP SCL 1 SDA 2 29 ADSW 28 BS3 BS1 3 BS2 4 IFIN1 5 IFIN2 6 Vcc I2C Bus Interface Shift Register Divider 1/128, 160, 256 REF OSC Phase Detector Charge Pump Band SW Driver REF OSC 26 CPO 25 VT Programmable Divider 14/15 bit 7 27 Prescaler 1/2 24 GND2 MIXOUT1 8 23 UOSCB2 MIXOUT2 9 22 UOSCE2 21 UOSCE1 GND1 10 20 UOSCB1 VHF MIX VHFIN 11 19 VOSCB2 BYP 12 18 VOSCC2 BS4 13 17 VOSCC1 UHF MIX 16 VOSCB1 UHFIN1 14 UHFIN2 15 –2– CXA3627N Pin Description Pin No. Symbol Description 1 SCL SCL input 2 SDA SDA I/O 3 BS1 Band switch output 1 4 BS2 Band switch output 2 5 IFIN1 IF amplifier input 6 IFIN2 IF amplifier input 7 Vcc Power supply 8 MIXOUT1 MIX output (open collector) 9 MIXOUT2 MIX output (open collector) 10 GND1 Analog circuit GND 11 VHFIN VHF input 12 BYP Switch of VHF input GND and UHF band switch output (GND: UHF for BS4, Open: UHF for BS3) 13 BS4 Band switch output 4 14 UHFIN1 UHF input 15 UHFIN2 UHF input 16 VOSCB1 VHF oscillator (base pin) 17 VOSCC1 VHF oscillator (collector pin) 18 VOSCC2 VHF oscillator (collector pin) 19 VOSCB2 VHF oscillator (base pin) 20 UOSCB1 UHF oscillator (base pin) 21 UOSCE1 UHF oscillator (emitter pin) 22 UOSCE2 UHF oscillator (emitter pin) 23 UOSCB2 UHF oscillator (base pin) 24 GND2 PLL circuit GND 25 VT Tuning voltage output (open collector) 26 CPO Charge pump output (loop filter connection) 27 REFOSC Crystal connection for PLL reference oscillator 28 BS3 Band switch output 3 29 ADSW Address selection (I2C bus) 30 IFOUT IF amplifier output –3– CXA3627N Pin Description Pin No. Symbol Pin voltage [V] Equivalent circuit Description 7 1 SCL — Clock input 40k 1 7 2 SDA — 40k Data input 2 5p 7 3 BS1 3 4 4 BS2 Band switch outputs. This pin corresponding to the selected band goes High. High: 4.9 Low: 0.0 7 13 BS4 13 14 28 BS3 100k –4– CXA3627N Pin No. Symbol Pin voltage [V] Equivalent circuit Description 7 5 5 IFIN1 1.6k 6 6 IFIN2 7 VCC 2.0 IF inputs. These pins must be connected to the mixer outputs via coupling capacitance. — Power supply. 8 8 MIXOUT1 — Mixer outputs. These pins output the signal in open collector format, and they must be connected to the power supply via a load. Analog circuit GND. 9 MIXOUT2 10 GND1 — VHFIN 2.4 during VHF reception 0.0 during UHF reception 11 9 7 10k 15p 100 VHF input. The input format is unbalanced input. 11 3k 12 BYP 3k 3.8 (when open) 12 VHF input GND and selection of band switching. GND: BS4 UHF Open: BS3 UHF 7 14 UHFIN1 0.0 during VHF reception 2.3 during UHF reception 15 14 15 3k 3k UHFIN2 –5– UHF inputs. Input a balanced signal to Pins 14 and 15, or ground either of Pin 14 or 15 with a capacitor and input the signal to the other pin. CXA3627N Pin No. Symbol 16 VOSCB1 18 VOSCC1 17 VOSCC2 19 VOSCB2 20 UOSCB1 21 UOSCE1 22 UOSCE2 23 UOSCB2 24 GND2 Pin voltage [V] 2.3 during VHF reception 2.5 during UHF reception 4.0 during VHF reception 5.0 during UHF reception 4.0 during VHF reception 5.0 during UHF reception 2.3 during VHF reception 2.5 during UHF reception Equivalent circuit 19 18 17 Description 16 7 20 20 5k External resonance circuit connection for VHF oscillator. 5k 2.4 during VHF reception 2.2 during UHF reception 2.0 during VHF reception 1.5 during UHF reception 2.0 during VHF reception 1.5 during UHF reception 2.4 during VHF reception 2.2 during UHF reception 7 23 22 21 External resonance circuit connection for UHF oscillator. 20 3k — 3k — PLL circuit GND. Varicap drive voltage output. This pin outputs the signal in open collector format, and it must be connected to the tuning power supply via a load. 7 25 VT — 26 25 70 26 CPO Charge pump output. Connects the loop filter. 2.0 7 30k 100 27 REFOSC 4.4 25p Crystal connection for reference oscillator. 27 38p –6– CXA3627N Pin No. Symbol Pin voltage [V] Equivalent circuit Description 7 150k 29 ADSW 1.25 (when open) Address selection. Controls address bits 1 and 2. 29 50k 5p 7 30 IFOUT 2.8 30 IF output. –7– CXA3627N Electrical Characteristics (See the Electrical Characteristics Measurement Circuit.) (Vcc = 5V, IFVCC = 5V, Ta = 25°C) Circuit Current Item Symbol Measurement conditions Min. Typ. Max. Unit Iccv VCC current Band switch output open during VHF operation 41 64 88 mA Iccu VCC current Band switch output open during UHF operation 40 63 87 mA Measurement conditions Min. Typ. Max. Unit Circuit current OSC/MIX/IF Amplifier Block Item Conversion gain∗1 Noise figure∗1, ∗2 1% cross modulation 1∗1, ∗3 Symbol CG1 VHF operation fRF = 55MHz High gain mode 19.0 22.0 25.0 dB CG2 VHF operation fRF = 360MHz High gain mode 19.5 22.5 25.5 dB CG3 UHF operation fRF = 360MHz High gain mode 23.0 26.0 29.0 dB CG4 UHF operation fRF = 800MHz High gain mode 23.0 26.0 29.0 dB CG5 VHF operation fRF = 55MHz Low gain mode 17.0 20.0 23.0 dB CG6 VHF operation fRF = 360MHz Low gain mode 17.5 20.5 23.5 dB CG7 UHF operation fRF = 360MHz Low gain mode 21.0 24.0 27.0 dB CG8 UHF operation fRF = 800MHz Low gain mode 21.0 24.0 27.0 dB NF1 VHF operation fRF = 55MHz High gain mode 12 15 dB NF2 VHF operation fRF = 360MHz High gain mode 12 15 dB NF3 UHF operation fRF = 360MHz High gain mode 10 13 dB NF4 UHF operation fRF = 800MHz High gain mode 11 14 dB NF5 VHF operation fRF = 55MHz Low gain mode 13 16 dB NF6 VHF operation fRF = 360MHz Low gain mode 13 16 dB NF7 UHF operation fRF = 360MHz Low gain mode 11 14 dB NF8 UHF operation fRF = 800MHz Low gain mode 12 15 dB CM1 VHF operation fD = 55MHz fUD = ±12MHz (30% AM) High gain mode 99 103 dBµ CM2 VHF operation fD = 360MHz fUD = ±12MHz (30% AM) High gain mode 99 103 dBµ CM3 UHF operation fD = 360MHz fUD = ±12MHz (30% AM) High gain mode 97 101 dBµ CM4 UHF operation fD = 800MHz fUD = ±12MHz (30% AM) High gain mode 94 98 dBµ CM5 VHF operation fD = 55MHz fUD = ±12MHz (30% AM) Low gain mode 100 104 dBµ CM6 VHF operation fD = 360MHz fUD = ±12MHz (30% AM) Low gain mode 100 104 dBµ CM7 UHF operation fD = 360MHz fUD = ±12MHz (30% AM) Low gain mode 98 102 dBµ CM8 UHF operation fD = 800MHz fUD = ±12MHz (30% AM) Low gain mode 94 98 dBµ 8 11 dBm Maximum output power Pomax 50Ω load, saturation output –8– CXA3627N Item Symbol Measurement conditions Min. Typ. Max. Unit ∆fsw1 VHF operation fOSC = 100MHz ∆f from 3s to 3min after switch ON ±200 kHz ∆fsw2 VHF operation fOSC = 405MHz ∆f from 3s to 3min after switch ON ±650 kHz ∆fsw3 UHF operation fOSC = 405MHz ∆f from 3s to 3min after switch ON ±350 kHz ∆fsw4 UHF operation fOSC = 845MHz ∆f from 3s to 3min after switch ON ±400 kHz ∆fst1 VHF operation fOSC = 100MHz ∆f when VCC 5V changes ±5% ±100 kHz Supply voltage drift ∆fst2 (PLL not operating) ∗ 4 ∆fst3 VHF operation fOSC = 405MHz ∆f when VCC 5V changes ±5% ±350 kHz UHF operation fOSC = 405MHz ∆f when VCC 5V changes ±5% ±100 kHz ∆fst4 UHF operation fOSC = 845MHz ∆f when VCC 5V changes ±5% ±100 kHz C/N1 VHF operation 10kHz offset CP = 1 Phase comparison frequency = 31.25kHz 80 dBc/Hz C/N2 UHF operation 10kHz offset CP = 1 Phase comparison frequency = 31.25kHz 80 dBc/Hz Switch ON drift (PLL not operating) ∗4 Oscillator phase noise ∗1 Value measured with untuned input. ∗2 NF meter direct-reading value (DSB measurement). ∗3 Value with a desired reception signal input level of –30dBm, an interference signal of 100kHz/30% AM, and an interference signal level where S/I = 46dB measured with a spectrum analyzer. ∗4 Value when the PLL is not operating. –9– CXA3627N PLL Block Item Symbol Min. Typ. Max. Unit LUT1 VHF operation CP = 1 fOSC 100MHz ← → fOSC 405MHz 50 ms LUT2 UHF operation CP = 1 fOSC 405MHz ← → fOSC 845MHz 50 ms REFL Phase comparison frequency = 31.25kHz CP = 1 Lock-up time Reference leak Measurement conditions dBc 50 CL and DA inputs "H" level input voltage VIH 3 Vcc V "L" level input voltage VIL GND 1.5 V "H" level input current IIH VIH = Vcc 0 –0.1 µA "L" level input current IIL VIL = GND –0.2 –4 µA AD input "H" level input voltage VIH 3 Vcc V "L" level input voltage VIL GND 1 V "H" level input current IIH VIH = Vcc 100 200 µA "L" level input current IIL VIL = GND –35 –100 µA "H" output leak current ISDALK VIN = 5.5V 5 µA "L" output voltage VSDAL Sink = –3mA GND 0.4 V Output current 1 ICPO1 When CP = 0 is selected ±30 ±80 µA Leak current 1 LeakCP1 When CP = 0 is selected 30 nA Output current 2 ICPO2 ±320 µA Leak current 2 LeakCP2 When CP = 1 is selected 100 nA Maximum output voltage VTH 34 V Minimum output voltage VTL 0.8 V 12 MHz 26 pF SDA output CPO (charge pump) When CP = 1 is selected ±120 ±50 ±200 VT (VC voltage output) Sink current = 1mA 0.15 REFOSC Oscillation frequency range FXTOSC 3 Input capacitance CXTOSC 22 24 Negative resistance RNEG Crystal source impedance fREF = 4MHz –1 –3 Output current IBS When ON Saturation voltage VSAT When ON Source current = 13mA Leak current LeakBS When OFF IFVCC = 5.5V kΩ Band SW – 10 – –13 mA 250 330 mV 0.5 3 µA CXA3627N Item Symbol Measurement conditions Min. Typ. Max. Unit 400 kHz Bus timing (I2C bus) SCL clock frequency fSCL Start waiting time tW;STA tH;STA tLOW tHIGH tS;STA tH;DAT tS;DAT tR tF tS;STO Start hold time Low hold time High hold time Start setup time Data hold time Data setup time Rise time Fall time Stop setup time 0 1300 ns 600 ns 1300 ns 600 ns 600 ns 0 900 600 600 – 11 – ns ns 300 ns 300 ns ns CXA3627N Electrical Characteristics Measurement Circuit IF OUT +30V 22k 4700p 240 BS2 220n 10k 0.056µ 1n BS1 4.7k 10k 2.5φ 2.5T 0.5p 1n 1T363 0.5p 0.5p 100p 10k XTAL 4MHz 360 1n 2.5φ 2.5T 1T363 10k 4.7k 1n 7p 56p 1k 3.0φ 5.5T 1T363 1T362 56p 15p 8p 100p VHFIN BYP BS4 UHFIN1 UHFIN2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VOSCB1 VOSCB2 VOSCC1 GND1 1 VOSCC2 UOSCE2 MIXOUT2 UOSCE1 UOSCB2 16 MIXOUT1 17 Vcc 18 VT 19 IFIN2 20 CPO 21 IFIN1 22 REFOSC 23 BS2 24 BS3 25 BS1 26 ADSW 27 SDA 28 IFOUT 29 27 SCL 30 7p UOSCB1 2p GND2 7p 2.2n 1n BS1 BS2 1n 51 51 360 1n 360 1n 1n 360 150p 4.5T 4.5T 150p 56p 56p 100 1n 1n 4.7µ ADSW SCL SDA +5V – 12 – VHF IN UHF IN 4.7k CXA3627N Application Circuit IF OUT +30V 22k 1n 4700p BS2 240 1.2µH 220n 10k 0.056µ 1n BS1 10k 2.5φ 1.5T 1n 2.5φ 2.5T 0.5p 1T369 10k 0.5p FMT 10p 100p 12p XTAL 100p 4.7k 1n 100p 4MHz UHFIN2 11 12 13 14 15 VOSCB1 VOSCC1 UHFIN1 10 VOSCC2 BS4 9 VOSCB2 BYP UOSCB1 VHFIN 8 3.8φ 14.5T UOSCE1 GND1 16 UOSCE2 17 MIXOUT2 18 UOSCB2 19 7 1n 3.2φ 7.5T BVL 47p 20 6 150p 200 BS2 21 4.7k 27 MIXOUT1 22 5 33p 47p 23 GND2 4 24 8p Vcc 3 BS1 15p 2.2n IFIN2 REFOSC BS2 2 25 CPO BS3 BS1 1 26 IFIN1 ADSW 27 SDA 28 IFOUT 29 SCL 30 8p VT 22p 200 1T363 1T362 8p 100p 3k 1k 4.7k 3.0φ 5.5T 2k 1n 4.5T 1n 1n 1n 4.5T BU BVH 1n 1n 56p 100 1n 56p 1n 4.7µ ADSW SCL SDA +5V VHF IN UHF IN Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 13 – CXA3627N Description of Functions The CXA3627N is the terrestrial TV broadcasting tuner IC which converts frequencies to IF in order to tune and detect only the desired reception frequency of VHF and UHF band signals. In addition to the mixer, local oscillation and IF amplifier circuits required for frequency conversion to IF, this IC also integrates a PLL circuit for local oscillation frequency control onto a single chip. The functions of the various circuits are described below. 1. Mixer circuit This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local oscillation signal. 2. Local oscillation circuit A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and inductance. 3. IF amplifier circuit This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage. 4. PLL circuit This PLL circuit fixes the local oscillation frequency to the desired frequency. It consists of a programmable divider, reference divider, phase comparator, charge pump and reference oscillator. The control format supports the I2C bus format. The frequency steps of 31.25, 50 or 62.5kHz can be selected by the I2C bus data-based reference divider frequency division setting value. 5. Band switch circuit The CXA3555N has four sets of built-in PNP transistors for switching between the VL, VH and UHF bands and for switching the FM trap, etc. These PNP transistors can be controlled by the bus data. The emitters for these PNP transistors are connected to the power supply pin (VCC), and are ON and output 5V when the bus data is "1 (H)". Two types of relations of the bus data and the IC internal OSC/MIX circuits operation are available as shown below. These relations can be selected by grounding or leaving open Pin 12 (BYP). BYP: Grounding Band SW data MIX circuit OSC circuit BS1 BS2 BS3 BS4 VHF UHF VHF UHF ∗ ∗ ∗ 0 O X O X ∗ ∗ ∗ 1 X O X O BYP: Open Band SW data MIX circuit OSC circuit BS1 BS2 BS3 BS4 VHF UHF VHF UHF ∗ ∗ 0 ∗ O X O X ∗ ∗ 1 ∗ X O X O ∗: Don't care O: Operating X: Not operating – 14 – CXA3627N Description of Analog Block Operation (See the Electrical Characteristics Measurement Circuit.) VHF oscillator circuit • This is the differential amplifier-type oscillator circuit. Pins 16 and 19 are base and Pins 17 and 18 are collector. Pins 16, 18 and Pins 19, 17 have the in-phase input/output relation respectively. This circuit is oscillated with the positive feedback applied by connecting the output to the input via the coupling capacitor and the feedback capacitor. Oscillation frequency is varied by connecting an LC parallel resonance circuit including a varicap and controlling the voltage applied to the varicap. VHF mixer circuit • The mixer circuit employs a double balanced mixer with little local oscillation signal leakage. The input format is base input type, with Pin 12 grounded either directly or via a capacitor and the RF signal input to Pin 11. (Pin 12 can also be used to select VHF/UHF switching mode with the BS3/BS4 data.) • The RF signal is fed from the oscillator, converted to IF frequency and output from Pins 8 and 9. Pins 8 and 9 are open collectors, so external power feed is necessary. Also, connect single-tuned filters to Pins 8 and 9. UHF oscillator circuit • The oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential oscillation operation via an LC resonance circuit including a varicap. • Resonance capacitance is connected between Pins 20 and 21, Pins 21 and 22, and Pins 22 and 23, and an LC resonance circuit including a varicap is connected between Pins 20 and 23. UHF mixer circuit • This circuit employs a double balanced mixer like the VHF mixer circuit. The input format is base input type, with Pins 14 and 15 as the RF input pins. The input method can be selected from balanced input consisting of differential input to Pins 14 and 15 or unbalanced input consisting of grounding Pin 14 via a capacitor and input to Pin 15. • Pins 8 and 9 are the mixer outputs. Pins 8 and 9 are open collectors, so external power feed is necessary. Also, connect single-tuned filters to Pins 8 and 9. IF amplifier circuit • Pins 5 and 6 are the IF amplifier inputs, and the input impedance is approximately 1.6kΩ. • The signals frequency converted by the mixer are output from Pins 8 and 9, and Pins 8 and 9 are connected to Pins 5 and 6 via capacitors. (An adjacent channel trap circuit can be formed by connecting LC parallel circuits in place of capacitors.) • The signal amplified by the IF amplifier is output from Pin 30. The output impedance is approximately 10Ω. – 15 – CXA3627N Description of PLL Block This IC is controlled by the I2C bus. The PLL of this IC performs high-speed phase comparison, providing low reference leak and quick lock-up time characteristics. During power on, the power-on reset circuit operates to initialize the frequency data to all "0" and the band data to all "OFF". Power-on reset is performed when VCC ≥ 3.2V at room temperature (Ta = 25°C). 1) Address setting Up to four addresses can be selected by the hardware bit settings, so that multiple PLL can exist within one system. The responding address can be set according to the ADSW pin voltage. Address 1 1 0 0 0 MA1 MA0 R/W Hardware bits ADSW pin voltage MA1 MA0 0 to 0.1Vcc 0 0 OPEN or 0.2Vcc to 0.3Vcc 0 1 0.4Vcc to 0.6Vcc 1 0 0.9Vcc to Vcc 1 1 2) Frequency data setting The VCO lock frequency is obtained according to the following formula. fosc = 2 × fref × (32M + S) fosc: local oscillator frequency fref: phase comparison frequency M: main divider frequency division ratio S: swallow counter frequency division ratio The variable frequency division ranges of M and S are as follows, and are set as binary. S < M ≤ 1023 0 ≤ S ≤ 31 – 16 – CXA3627N 3) Control format When performing control for this IC, byte 1 contains the address data, bytes 2 and 3 contain the frequency data, byte 4 contains the control data, and byte 5 contains the band switch data. These data are latch transferred in the manner of byte 1, byte 2 + byte 3, and byte 4 + byte 5. When the correct address is received and acknowledged, the data is recognized as frequency data if the first bit of the next byte is "0", and as control data and band switch data if this bit is "1". Also, when data transmission is stopped part-way, the previously programmed data is valid. Therefore, once the control and band switch data have been programmed, 3-byte commands consisting of the address and frequency data are possible. Further, even if the I2C bus stop conditions are not met, data can be input by sending the start conditions and the new address. The control format is as shown in the table below. Slave Receiver MSB LSB bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Address byte 1 1 0 0 0 MA1 MA0 0 A Divider byte1 0 M9 M8 M7 M6 M5 M4 M3 A Divider byte2 M2 M1 M0 S4 S3 S2 S1 S0 A Control byte 1 CP GC CD X R1 R0 OS A Band SW byte X X X X BS4 BS3 BS2 BS1 A Mode X: Don't care A: MA0, MA1: M0 to: S0 to: CD: OS: CP: GC: BS1 to BS4: R0, R1: Acknowledge bit address setting main divider frequency division ratio setting swallow counter frequency division ratio setting charge pump OFF (when "1") varicap output OFF (when "1") charge pump current switching (200µA when "1", 50µA when "0") gain switching (IC gain reduced by 2dB when "1") band switch control (output PNP transistor ON when "1") reference divider frequency division ratio setting (See the Reference Divider Frequency Division Ratio Table.) Reference Divider Frequency Division Ratio Table R1 R0 Reference Divider 0 1 256 1 1 128 X 0 160 X: Don't care – 17 – CXA3627N I2C Bus Timing Chart tW;STA SDA tR tS;STA tF tS;STO SCL tH;STA START tS;STA tW;STA tH;STA tLOW tHIGH tLOW tHIGH tS;DAT CLOCK = Start setup time = Start waiting time = Start hold time = Low clock pulse width = High clock pulse width tH;DAT DATA CHANGE tS;DAT tH;DAT tS;STO tR tF – 18 – = Data setup time = Data hold time = Stop setup time = Rise time = Fall time STOP CXA3627N Example of Representative Characteristics Band SW output voltage vs. Output current (BS1, BS2, BS3, BS4) Circuit current vs. Supply voltage 70 5.4 Vcc = 5V 68 VHF UHF 66 5.2 64 Output voltage [V] Icc – Circuit current [mA] 5.3 62 60 58 56 5.1 5.0 4.9 4.8 54 4.7 52 50 4.7 4.8 4.9 5.0 5.1 5.2 5.3 4.6 0 5.4 3 6 15 Conversion gain vs. Reception frequency (Untuned input) Noise figure vs. Reception frequency (Untuned input, in DSB) UHF VHF (High) VHF (Low) 10 0 0 fIF = 45MHz High gain mode NF – Noise figure [dB] 30 20 15 VHF (High) VHF (Low) 5 0 0 100 200 300 400 500 600 700 800 900 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] Next adjacent cross modulation vs. Reception frequency (Untuned input) 120 100 VHF (High) UHF 300 VHF (Low) VHF (High) Vcc + 5% Vcc – 5% (Vcc = 5V) 200 VHF (Low) +B drift [kHz] 80 70 60 50 30 Oscillation frequency power supply fluctuation (PLL off) 400 90 40 UHF 10 Reception frequency [MHz] 110 18 20 fIF = 45MHz High gain mode CG – Conversion gain [dB] 12 Output current [mA] 40 CM – Cross modulation [dBµ] 9 Vcc – Supply voptage [V] fUD = fD + 12MHz fUD = fD – 12MHz (100kHz, 30% AM) 100 UHF 0 –100 –200 20 10 0 0 –300 fIF = 45MHz High gain mode –400 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] 100 200 300 400 500 600 700 800 900 Oscillation frequency [MHz] – 19 – CXA3627N Oscillator phase noise vs. Reception frequency (untuned input) 130 fIF = 45MHz High gain mode C/N – Oscillator phase noise [dBc/Hz] 120 VHF (Low) VHF (High) UHF 110 100 VHF (Low) 90 UHF VHF (High) 80 70 VHF (Low) VHF (High) 60 UHF 1kHz offset 10kHz offset 100kHz offset 50 40 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] I/O characteristics (untuned input) PCS beat characteristics (untuned input) 20 20 High gain mode 10 10 0 fIF 0 –10 IF output level [dBm] IF output level [dBm] –10 –20 –30 –20 –30 –40 fBeat fLocal = 495MHz fP = 449.25MHz fc = 452.83MHz (fP –12dB) fs = 453.75MHz (fP –1.7dB) –50 –40 –60 fRF = 45MHz High gain mode fRF = 145MHz (VHF) fRF = 495MHz (UHF) –50 –60 –60 –50 –40 –30 –20 –10 0 10 –70 fIF = 45.75MHz fBeat = fIF ± 950kHz 20 RF level [dBm] –80 –40 –30 –20 –10 0 10 RF level (SG Setting level) [dBm] – 20 – 20 CXA3627N Tuning Response Time VHF (Low) 95MHz → VHF (High) 395MHz CP = 0 T = 47.2ms 5.0V/div Offset 10.0V –75.0000ms 25.0000ms 125.0000ms 20.0ms/div CP = 1 T = 15.0ms 5.0V/div Offset 10.0V –40.0000ms 10.0000ms 10.0ms/div – 21 – 60.0000ms CXA3627N UHF 413MHz → UHF 847MHz CP = 0 T = 63.6ms 5.0V/div Offset 10.0V –70.0000ms 30.0000ms 130.0000ms 20.0ms/div CP = 1 T = 20.2ms 5.0V/div Offset 10.0V –40.0000ms 10.0000ms 10.0ms/div – 22 – 60.0000ms CXA3627N VHF (High) 395MHz → VHF (Low) 95MHz CP = 0 T = 27.0ms 5.0V/div Offset 10.0V –110.0000ms –10.0000ms 90.0000ms 20.0ms/div CP = 1 T = 7.2ms 5.0V/div Offset 10.0V –45.0000ms 5.0000ms 10.0ms/div – 23 – 55.0000ms CXA3627N UHF 847MHz → UHF 413MHz CP = 0 T = 35.6ms 5.0V/div Offset 10.0V –110.0000ms –10.0000ms 90.0000ms 20.0ms/div CP = 1 T = 14.4ms 5.0V/div Offset 10.0V –90.0000ms 10.0000ms 20.0ms/div – 24 – 110.0000ms CXA3627N IF output spectrum REF = –10.0dBm 10dB/div VHF (Low) fRF = 55MHz fLO = 100MHz RF input level: –40dBm CENTER 45.00100MHz RES BW 1.0kHz VBW 10Hz SPAN 50.00kHz SWP 30.0s REF = –10.0dBm 10dB/div VHF (High) fRF = 350MHz fLO = 395MHz RF input level: –40dBm CENTER 45.00350MHz RES BW 1.0kHz VBW 10Hz SPAN 50.00kHz SWP 30.0s REF = –0.0dBm 10dB/div UHF fRF = 800MHz fLO = 845MHz RF input level: –40dBm CENTER 45.00188MHz RES BW 1.0kHz VBW 10Hz – 25 – SPAN 50.00kHz SWP 30.0s CXA3627N VHF Input Impedance j50 j25 0 j100 50 50MHz 11 12 1000p 350MHz –j25 S11 –j100 –j50 UHF Input Impedance j50 j25 0 j100 50 14 15 1000p 350MHz S11 –j25 –j100 800MHz –j50 – 26 – CXA3627N IF Output Impedance j50 j25 j100 45MHz 0 38MHz 50 –j25 –j100 –j50 – 27 – CXA3627N Package Outline Unit: mm 30PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 ∗9.7 ± 0.1 0.10 1 A 15 0.65 0.13 M b=0.22 ± 0.03 0.5 ± 0.2 0.1 ± 0.1 + 0.03 0.15 – 0.01 b 7.6 ± 0.2 16 ∗5.6 ± 0.1 30 DETAIL B : PALLADIUM NOTE: Dimension "∗" does not include mold protrusion. 0˚ to 10˚ PACKAGE STRUCTURE DETAIL A SONY CODE EIAJ CODE SSOP-30P-L01 P-SSOP30-5.6x9.7-0.65 JEDEC CODE – 28 – PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT PALLADIUM PLATING LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.1g Sony Corporation