0 LogiCORE PCI Interface v3.0 DS 208 (v.1.2) June 28, 2002 0 0 Data Sheet, v3.0.99 Introduction LogiCORE Facts With the Xilinx LogiCORE PCI-X Interface, a designer can build a customized PCI-X 1.0a-compliant core with high sustained performance, 800 Mbytes/sec. PCI-X64 / PCI64 Resource Utilization1 Slice Four Input LUTs 2646 Slice Flip Flops 1605 IOB Flip Flops 257 IOBs 90 BUFGs / DCMs 2/1 PCI-X64 Mode Only Resource Utilization1 Slice Four Input LUTs 2126 Slice Flip Flops 1461 IOB Flip Flops 257 IOBs 90 BUFGs / DCMs 1/1 PCI64 Mode Only Resource Utilization1 Slice Four Input LUTs 1915 Slice Flip Flops 1350 IOB Flip Flops 253 IOBs 90 BUFGs / DCMs 1/0 Provided with Core Documentation PCI-X Design Guide Features • Fully PCI-X 1.0a-compliant core, 64-bit, 100/66/33 MHz interface with 3.3 V operation • Customizable, programmable, single-chip solution • Predefined implementation for predictable timing • Incorporates Xilinx Smart-IP Technology • Fully verified design tested with Xilinx proprietary testbench and hardware • Available for configuration and download on the web: - Web-based Configuration and Download Tool - Web-based User Constraint File Generator Tool • Instant Access to New Releases • Integrated extended capabilities: • • - PCI-X Capability Item - Power Management Capability Item - Message Signalled Interrupt Capability Item Supported PCI-X only functions: - Split Completion - Memory Read Dword - Memory Read Block - Memory Write Block Supported PCI only functions: - Memory Read - Memory Read Multiple - Memory Read Line - Memory Write and Invalidate Design File Formats PCI-X Implementation Guide Verilog/VHDL Simulation Model NGO Netlist Constraint Files User Constraint Files (UCF) Example Design Verilog/VHDL Example Design Design Tool Requirements Xilinx Tools v4.2i, Service Pack 3 Tested Entry and Synplicity Synplify Verification Tools2 Synopsys FPGA Express Exemplar Leonardo Spectrum Xilinx XST3 Cadence Verilog XL Model Technology ModelSim 1. The resource utilization depends on configuration of the interface and the user design. Unused resources are trimmed by the Xilinx technology mapper. The utilization figures reported in this table are representative of a maximum configuration. 2. See the implementation guide or product release notes for current supported versions. 3. XST is command line option only. See Implementation Guide for details. © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. DS 208 (v.1.2) June 28, 2002 Data Sheet, v3.0.99 www.xilinx.com 1-800-255-7778 1 LogiCORE PCI Interface v3.0 The core meets the setup, hold, and clock to timing requirements as specified in the PCI-X specification. The interface is verified through extensive simulation. LogiCORE Facts (Cont) PCI64/33 Only PCI-X64/66 Only PCI-X64/100 Only PCI-X64/66 PCI64/33 PCI-X 64 Supported Devices Virtex-E V300EBG432-8C Virtex-II 2V1000FG456-5C Virtex-E V300EBG432-8C Virtex-II 2V1000FG456-5C 3.3v only 3.3v only 3.3v only 3.3v only Virtex-II 2V1000FG456-5C 3.3v only Virtex-II 2V1000FG456-5C 3.3v only Xilinx provides technical support for this LogiCORE product when used as described in the Design Guide and the Implementation Guide. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices not listed, or if customized beyond that allowed in the product documentation. Note: Fully compliant designs over 66 MHz require two bitstreams. Note: Universal card implementations not supported. Note: Commercial devices only; 0 C < Tj < 85 C. Memory Write - I/O Read - I/O Write - Configuration Read - Configuration Write - Interrupt Acknowledge - Bus Parking - Type 0 Configuration Space Header - Full 64-bit Addressing Support - Up to 6 Base Address Registers - Expansion ROM Base Address Register - Instant-On Base Address Registers - Parity Generation, Parity Error Detection - Full Command/Status Registers Block SelectRAM™ memory. Blocks of on-chip ultra-fast RAM with synchronous write and dual-port RAM capabilities. Used in PCI-X designs to implement FIFOs. • SelectRAM memory. Distributed on-chip ultra-fast RAM with synchronous write option and dual-port RAM capabilities. Used in PCI-X designs to implement FIFOs. Smart-IP Technology Supported PCI and PCI-X functions: - • The interface is carefully optimized for best possible performance and utilization in Xilinx FPGA devices. More Features • Other features that enable efficient implementation of a PCI-X system include: Drawing on the architectural advantages of Xilinx FPGAs, Xilinx Smart-IP technology ensures the highest performance, predictability, repeatability, and flexibility in PCI-X designs. The Smart-IP technology is incorporated in every LogiCORE PCI-X Interface. Xilinx Smart-IP technology leverages the Xilinx architectural advantages, such as look-up tables and segmented routing, as well as floorplanning information, such as logic mapping and location constraints. This technology provides the best physical layout, predictability, and performance. Additionally, these features allow for significantly reduced compile times over competing architectures. To guarantee the critical setup, hold, minimum clock to out, and maximum clock to out timing, the PCI-X interface is delivered with Smart-IP constraint files that are unique for a device and package combination. These constraint files guide the implementation tools so that the critical paths always are within specification. Applications Xilinx provides Smart-IP constraint files for many device and package combinations. Constraint files for unsupported device and package combinations may be generated using the web-based constraint file generator. • Embedded applications in networking, industrial, and telecommunication systems • PCI-X add-in boards such as frame buffers, network adapters, and data acquisition boards • Hot swap CompactPCI-X boards Functional Description • Any applications that need a PCI-X interface The LogiCORE PCI-X Interface is partitioned into six major blocks and a user application as shown in Figure 1. General Description The LogiCORE PCI-X Interface is a preimplemented and fully tested module for Xilinx FPGAs. Critical paths are controlled by constraint and guide files to ensure predictable timing. This significantly reduces the engineering time required to implement the PCI-X portion of your design. Resources can instead be focused on your unique user application logic in the FPGA and on the system level design. As a result, LogiCORE PCI-X products minimize your product development time. 2 Datapath There are four datapaths, in and out for both target and initiator. To improve timing and ease of design, the four unidirectional datapaths are multiplexed inside the interface. All data transfers are register-to-register. Since fewer registers are on each datapath, loading is reduced and false timing paths are eliminated. www.xilinx.com 1-800-255-7778 DS 208 (v.1.2) June 28, 2002 Data Sheet, v3.0.99 LogiCORE PCI Interface v3.0 Table 1: PCI-X Configuration Space Header targ 31 Target Datapath In 16 15 0 data path mux init data path mux Initiator Datapath In data path mux Target Datapath Out Vendor ID 00h Status Command 04h Target State Machine Watchdog Target Status Target Control Initiator State Machine Rev ID 08h Cache Line Size 0Ch Class Code Initiator Datapath Out data path mux Config Space Device ID BIST Header Type Initiator Control Latency Timer Initiator Status Base Address Register 0 (BAR0) 10h Base Address Register 1 (BAR1) 14h Base Address Register 2 (BAR2) 18h Base Address Register 3 (BAR3) 1Ch Decode Base Address Register 4 (BAR5) 20h When an address is broadcast on the bus, the decode module compares it to the base address registers for a match. If one occurs, the target state machine is activated. Base Address Register 5 (BAR5) 24h Cardbus CIS Pointer 28h Decode Target Hit Figure 1: LogiCORE PCI-X Interface Block Diagram Subsystem ID PCI-X Configuration Space Three extended capabilities are provided in the interface: PCI-X Capability Item • Power Management Capability Item • Message Signalled Interrupt Capability Item Reserved CapPtr Min Gnt Interrupt Pin Interrupt Line 3Ch NxtCap PM Cap 40h Power Management Capability Data PMCSR BSE Message Control PMCSR NxtCap MSI Cap 44h 48h Message Address 4Ch Message Upper Address 50h Reserved These capability items may be linked or delinked from the capabilities list as required, and user functions can be integrated into the capabilities list. 34h 38h Reserved Max Lat 2Ch 30h Expansion ROM Base Address This block provides the first 64 bytes of Type 0, version 2.3 Configuration Space Header, and an additional 64 bytes reserved for extended capabilities, as shown in Table 1. The remaining 128 bytes of configuration space are available to the user for application specific registers. Together, these support software-driven “Plug-and Play” initialization and configuration. This includes information for Command, Status, Base Address Registers, and the extended capabilities required for PCI-X. • Subsystem Vendor ID Message Data PCI-X Command NxtCap PCI-X Cap PCI-X Status 54h 58h 5Ch Reserved 60h-7Fh Available User Configuration Space 80h-FFh Note: Shaded areas are not implemented and return zero. Watchdog The watchdog monitors various system conditions, including bus mode and bus width. This module also indicates if run-time reconfiguration is required for loading different bitstreams. Target State Machine This block controls the PCI-X and PCI interface for target functions. The controller is a high-performance state machine using one-hot encoding for maximum performance. DS 208 (v.1.2) June 28, 2002 Data Sheet, v3.0.99 www.xilinx.com 1-800-255-7778 3 LogiCORE PCI Interface v3.0 Initiator State Machine Table 2: PCI Bus Commands This block controls the PCI-X and PCI interface for initiator functions. The initiator control logic also uses one-hot encoding for maximum performance. User Interface The PCI-X interface provides a simplified user application interface which allows a user to create one design that handles both PCI-X and PCI transactions without design changes, and both 32-bit and 64-bit data transfers without external data width conversion. This eliminates the need for multiple designs to support PCI-X and PCI and varying bus widths. This streamlined interface also simplifies the amount of work needed to create a user application. The user interface can be designed as either a 32-bit or 64-bit interface and the PCI-X interface will automatically handle data conversions regardless of the width of the PCI-X or PCI bus. Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read1 Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple2 Dual Address Cycle Memory Read Line2 Memory Write Invalidate2 Initiator Yes Yes Yes Yes Ignore Ignore Yes Yes Ignore Ignore Yes Yes Yes Yes Yes Yes Target Yes No Yes Yes Ignore Ignore Yes Yes Ignore Ignore Yes Yes Yes Yes Yes Yes 1. This command can only be used for a single dword transfer. 2. These commands have fixed byte enables of 0h. Table 3: PCI-X Bus Commands Interface Configuration The LogiCORE PCI-X Interface can easily be configured to fit unique system requirements by using the Xilinx Web-based Configuration and Download Tool or by changing the HDL configuration file. The following customization options, among many others, are supported by the interface and are described in the product design guide. • Base Address Registers (number, size, and mode) • Expansion ROM BAR • Cardbus CIS pointer • Configuration Space Header ROM • Interrupt Connectivity • Extended Command Use • Capability Configuration Burst Transfer The PCI-X bus derives its performance from its ability to support burst transfers. The performance of any PCI-X application depends largely on the size of the burst transfer. Buffers to support PCI-X burst transfer can efficiently be implemented using on-chip RAM resources. Supported PCI Commands Table 2 lists the PCI bus commands supported by the LogiCORE PCI-X Interface, and Table 3 lists the supported PCI-X bus commands. 4 CBE [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CBE [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Dword Memory Write Alias to Memory Read Block Alias to Memory Write Block Configuration Read Configuration Write Split Completion Dual Address Cycle Memory Read Block Memory Write Block Initiator Yes Yes Yes Yes Ignore Ignore Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Target Yes No Yes Yes Ignore Ignore Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Bandwidth The LogiCORE PCI-X Interface supports fully compliant zero wait-state burst operations for both sourcing and receiving data. This interface supports a sustained bandwidth of up to 800 MBytes/sec. The design can be configured to take advantage of the ability of the LogiCORE PCI-X Interface to do very long bursts. The flexible user application interface, combined with support for many different PCI-X features, gives users a solution that lends itself to use in many high-performance applications. The user is not locked into one DMA engine, hence, an optimized design that fits a specific application can be designed. www.xilinx.com 1-800-255-7778 DS 208 (v.1.2) June 28, 2002 Data Sheet, v3.0.99 LogiCORE PCI Interface v3.0 Recommended Design Experience The LogiCORE PCI-X Interface is pre-implemented allowing engineering focus on the unique user application functions of a PCI-X design. Regardless, PCI-X is a high-performance design that is challenging to implement in any technology. Therefore, previous experience with building high-performance, pipelined FPGA designs using Xilinx implementation software, constraint files, and guide files is recommended. The challenge to implement a complete PCI-X design including user application functions varies depending on configuration and functionality of your application. Contact your local Xilinx representative for a closer review and estimation for your specific requirements. Information on additional Xilinx LogiCORE modules is available on the Xilinx IP Center. Table 4: Timing Parameters, 66MHz PCI-X Symbol Tcyc Thigh Tlow Tval Tval Ton Toff Tsu Timing Specifications Tsu The maximum speed at which your user design is capable of running can be affected by the size and quality of the design. The following tables show the key timing parameters for the LogiCORE PCI-X Interface. Timing Parameters in the 66MHz PCI-x are listed in Table 4. Timing Parameters in the 33MHz PCI are listed in Table 5. Th Trstoff Parameter CLK Cycle Time CLK High Time CLK Low Time CLK to Signal Valid Delay (bussed signals) CLK to Signal Valid Delay (point to point signals) Float to Active Delay Active to Float Delay Input Setup Time to CLK (bussed signals) Input Setup Time to CLK (point to point signals) Input Hold Time from CLK Reset Active to Output Float Min 151 6 6 0.72 Max 20 3.82 0.72 3.82 02 1.72 72 - 1.72 - 0.52 - 40 Min 301 11 11 22 Max 112 22 112 22 72 281 - 102 - 02 - 40 Notes: 1. Controlled by timespec constraints, included in product. 2. Controlled by SelectIO configured for PCIX. 3. Operation at 100 MHz requires Tsu of 1.2 and Tcyc of 10. Table 5: Timing Parameters, 33MHz PCI Ordering Information Symbol Tcyc This core may be downloaded from the Xilinx IP Center for use with the Xilinx CORE Generator System V4.1 and later. The Xilinx CORE Generator System tool is bundled with all Alliance and Foundation Series Software packages, at no additional charge. Thigh Tlow Tval Tval Part Numbers Ton DO-DI-PCIX64-VE Toff Tsu -PCI-X 64-bit 66/100 MHz IP only Core DX-DI-64IP-XVE Tsu - Upgrade from DO-DI-PCI64/DO-DI-PCI-AL/DO-DI-PCI64DK to DO-DI-PCIX64-VE Th Trstoff To order Xilinx’s PCI Core, please visit the Xilinx Silicon Xpresso Cafe or contact your local Xilinx sales representative. Parameter CLK Cycle Time CLK High Time CLK Low Time CLK to Signal Valid Delay (bussed signals) CLK to Signal Valid Delay (point to point signals) Float to Active Delay Active to Float Delay Input Setup Time to CLK (bussed signals) Input Setup Time to CLK (point to point signals) Input Hold Time from CLK Reset Active to Output Float Notes: 1. Controlled by timespec constraints, included in product. 2. Controlled by SelectIO configured for PCI33_3 or PCIX. Revision History The following table shows the revision history for this document. Date Version 06/28/02 1.0 DS 208 (v.1.2) June 28, 2002 Data Sheet, v3.0.99 Revision New template www.xilinx.com 1-800-255-7778 5