54ABT374 Octal D-Type Flip-Flop with TRI-STATE ® Outputs General Description The ’ABT374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. Features n n n n Edge-triggered D-type inputs Buffered positive edge-triggered clock TRI-STATE outputs for bus-oriented applications Output sink capability of 48 mA, source capability of 24 mA n Guaranteed multiple output switching specifications n Output switching specified for both 50 pF and 250 pF loads n Guaranteed simultaneous switching, noise level and dynamic threshold performance n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9314901 Ordering Code Military Package Package Description Number 54ABT374J/883 J20A 20-Lead Ceramic Dual-In-Line 54ABT374W/883 W20A 20-Lead Cerpack 54ABT374E/883 E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100207-2 DS100207-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100207 www.national.com 54ABT374 Octal D-Type Flip-Flop with TRI-STATE Outputs July 1998 Pin Descriptions Pin Functional Description The ’ABT374 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flip-flops. Description Names D0–D7 Data Inputs CP Clock Pulse Input (Active Rising Edge) OE TRI-STATE Output Enable Input (Active LOW) O0–O7 TRI-STATE Outputs Function Table Inputs Internal Outputs D Q O H L NC Z H H NC Z Hold H N L L Z Load H N H H Z Load L N L L L Data Available L N H H H L H L NC NC No Change in Data L H H NC NC No Change in Data OE CP H H Function Hold Data Available H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition NC = No Change Logic Diagram DS100207-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) DC Latchup Source Current: OE Pin (Across Comm Operating Range) Other Pins Over Voltage Latchup (I/O) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) −65˚C to +150˚C −55˚C to +125˚C −150 mA −500 mA 10V Recommended Operating Conditions −55˚C to +175˚C Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −0.5V to 5.5V −0.5V to VCC −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns 100mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. twice the rated IOL (mA) Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter ABT374 Min Units VCC VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH 54ABT 2.5 V Min Voltage 54ABT 2.0 V Min VOL Output LOW Voltage 54ABT IIH Input HIGH Current 2.0 V Recognized HIGH Signal 0.8 V −1.2 V Recognized LOW Signal IIN = −18 mA Min 0.55 V Min 5 µA Max 5 IBVI Input HIGH Current Breakdown Test 7 µA Max IIL Input LOW Current −5 µA Max V 0.0 −5 VID Input Leakage Test Conditions Typ Max 4.75 IOH = −3 mA IOH = −24 mA IOL = 48 mA VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 4) VIN = 0.0V IID = 1.9 µA All Other Pins Grounded VOUT = 2.7V; OE = 2.0V IOZH Output Leakage Current 50 µA 0 − 5.5V IOZL Output Leakage Current −50 µA 0 − 5.5V IOS Output Short-Circuit Current −275 mA Max ICEX Output High Leakage Current 50 µA Max IZZ Bus Drainage Test 100 µA 0.0 ICCH Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max ICCZ Power Supply Current 50 µA Max ICCT Additional ICC/Input Outputs Enabled 2.5 mA All Outputs LOW OE = VCC; All Others at VCC or GND VI = VCC − 2.1V Outputs TRI-STATE 2.5 mA Outputs TRI-STATE 2.5 mA −100 Max VOUT = 0.5V; OE = 2.0V VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Others VCC or GND Enable Input VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or GND 3 www.national.com DC Electrical Characteristics Symbol (Continued) Parameter ABT374 Min ICCD Dynamic ICC Units VCC mA/ Max Conditions Typ Max No Load (Note 4) 0.30 Outputs Open OE = GND, (Note 3) MHz One Bit Toggling, 50% Duty Cycle Note 3: For 8-bit toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Units CL = 50 pF Min fmax Max Clock Max 150 MHz Frequency tPLH Propagation Delay 1.4 6.6 tPHL CP to On 2.0 7.6 tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ 0.8 5.7 1.5 7.2 1.3 7.2 1.0 7.0 ns ns ns AC Operating Requirements Symbol 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Parameter Units CL = 50 pF Min ts(H) Setup Time, HIGH 2.5 ts(L) or LOW Dn to CP 2.5 th(H) Hold Time, HIGH 2.5 th(L) or LOW Dn to CP 2.5 tw(H) Pulse Width, CP 3.3 tw(L) HIGH or LOW 3.3 Max ns ns ns Capacitance Typ Units CIN Symbol Input Capacitance Parameter 5.0 pF COUT (Note 5) Output Capacitance 9.0 pF Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.national.com 4 Conditions (TA = 25˚C) VCC = 0V VCC = 5.0V Capacitance (Continued) tPLH vs Temperature (TA) CL = 50 pF, 1Output Switching Clock to Output tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching Clock to Output DS100207-12 tPZH vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output DS100207-13 tPZL vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output DS100207-14 tPHZ vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output DS100207-15 tPLZ vs Temperature (TA) CL = 50 pF, 1 Output Switching OE to Output DS100207-16 DS100207-17 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 5 www.national.com Capacitance (Continued) tSET LOW vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to Clock tSET HIGH vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to Clock DS100207-18 tHOLD HIGH vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to Clock DS100207-19 tHOLD LOW vs Temperature (TA) CL = 50 pF, 1 Output Switching Data to Clock DS100207-21 DS100207-20 tPLH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching Clock to Output tPHL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching Clock to Output DS100207-22 DS100207-23 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 6 Capacitance (Continued) tPZH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output tPZL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output DS100207-24 tPHZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output DS100207-25 tPLZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching OE to Output DS100207-26 tPLH vs Load Capacitance TA = 25˚C, 1 Output Switching Clock to Output DS100207-27 tPHL vs Load Capacitance TA = 25˚C, 1 Output Switching Clock to Output DS100207-28 DS100207-29 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. 7 www.national.com Capacitance (Continued) tPLH vs Load Capacitance TA = 25˚C, 8 Outputs Switching Clock to Output tPHL vs Load Capacitance TA = 25˚C, 8 Outputs Switching Clock to Output DS100207-31 DS100207-30 tPZH vs Load Capacitance TA = 25˚C, 8 Outputs Switching OE to Output tPZL vs Load Capacitance TA = 25˚C, 8 Outputs Switching OE to Output DS100207-32 tPLH and tPHL vs Number Outputs Switching CL = 50 pF, TA = 25˚C, VCC = 5.0V, Outputs in Phase Clock to Output DS100207-33 Typical ICC vs Output Switching Frequency CL = 0 pF, VCC = VIH = 5.5V, 1 Output Switching at 50% Duty Cycle Clock to Output DS100207-34 DS100207-35 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. www.national.com 8 AC Loading DS100207-8 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions DS100207-4 *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load DS100207-5 FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100207-6 FIGURE 2. VM = 1.5V Input Pulse Requirements Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements DS100207-7 FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times DS100207-9 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 9 www.national.com 10 Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line (D) NS Package Number J20A 11 www.national.com 54ABT374 Octal D-Type Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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