FSGL134R Data Sheet Radiation Hardened, SEGR Resistant N-Channel Power MOSFETs itle Fairchild Star*Power™ Rad Hard MOSFETs have been specifically developed for high performance applications in a commercial or military space environment. Star*Power MOSFETs offer the system designer both extremely low rDS(ON) and Gate Charge allowing the development of low loss Power Subsystems. Star*Power Gold FETs combine this electrical capability with total dose radiation hardness up to 100K RADs while maintaining the guaranteed performance for Single Event Effects (SEE) which the Fairchild FS families have always featured. July 2001 File Number 5011 Features • 10A, 150V, rDS(ON) = 0.125Ω • UIS Rated TM bjec tho yw s () eato OCI O mar ge de eO nes OC EW mar The Fairchild family of Star*Power FETs includes a series of devices in various voltage, current and package styles. The portfolio consists of Star*Power and Star*Power Gold products. Star*Power FETs are optimized for total dose and rDS(ON) while exhibiting SEE capability at full rated voltage up to an LET of 37. Star*Power Gold FETs have been optimized for SEE and Gate Charge combining SEE performance to 80% of the rated voltage for an LET of 82 with extremely low gate charge characteristics. This MOSFET is an enhancement-mode silicon-gate power field effect transistor of the vertical DMOS (VDMOS) structure. It is specifically designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, power distribution, motor drives and relay drivers as well as other power control and conditioning applications. As with conventional MOSFETs these Radiation Hardened MOSFETs offer ease of voltage control, fast switching speeds and ability to parallel switching devices. • Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) • Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 82MeV/mg/cm2 with VDS up to 80% of Rated Breakdown and VGS of 5V Off-Bias • Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IAS • Photo Current - 2nA Per-RAD (Si)/s Typically • Neutron - Maintain Pre-RAD Specifications for 1E13 Neutrons/cm2 - Usable to 1E14 Neutrons/cm2 Symbol D G S Packaging TO-205AF Reliability screening is available as either TXV or Space equivalent of MIL-PRF-19500. Formerly available as type TA45228W. Ordering Information RAD LEVEL SCREENING LEVEL PART NUMBER/BRAND 10K Engineering samples FSGL134D1 100K TXV FSGL134R3 100K Space FSGL134R4 ©2001 Fairchild Semiconductor Corporation 4-1 D G S FSGL134R Rev. A1 FSGL134R Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified FSGL134R UNITS Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 150 V Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 150 V Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID 10 A TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 6 A Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 40 A Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±30 V TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT 25 W TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT 10 W Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.20 W/ oC Maximum Power Dissipation Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . IAS 40 A Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS 10 A Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM 40 A Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) 300 oC 1.0 (Typical) g Weight (Typical) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS Drain to Source Breakdown Voltage BVDSS ID = 1mA, VGS = 0V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 1mA Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On-State Voltage Drain to Source On Resistance Turn-On Delay Time IDSS IGSS VDS(ON) rDS(ON)12 td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time VDS = 120V, VGS = 0V VGS = ±30V Qg(12) Gate Charge Source Qgs Gate Charge Drain Qgd UNITS - - V - - 5.5 V TC = 25oC 2.0 - 4.5 V TC = 125oC 1.0 - - V TC = 25oC TC = 125oC TC = 25oC TC = 125oC - - 25 µA - - 250 µA - - 100 nA - - 200 nA - - 1.30 V - 0.110 0.125 Ω - - 0.219 Ω TC = 25oC TC = 125oC VDD = 75V, ID = 10A, RL = 7.5Ω, VGS = 12V, RGS = 7.5Ω VGS = 0V to 12V MAX 150 tf Total Gate Charge TYP TC = -55oC VGS = 12V, ID = 10A ID = 6A, VGS = 12V MIN 75V < VDD < 120V, ID = 10A - - 20 ns - - 40 ns - - 35 ns - - 25 ns - 26 28 nC - 10 12 nC - 8 10 nC Gate Charge at 20V Qg(20) VGS = 0V to 20V - 40 - nC Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 3 - nC Plateau Voltage V(PLATEAU) Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance Junction to Case ©2001 Fairchild Semiconductor Corporation 4-2 RθJC ID = 10A, VDS = 15V - 7 - V VDS = 25V, VGS = 0V, f = 1MHz - 1200 - pF - 275 - pF - 16 - pF 5.0 oC/W - - FSGL134R Rev. A1 FSGL134R Source to Drain Diode Specifications PARAMETER SYMBOL Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge MIN TYP MAX ISD = 10A TEST CONDITIONS - - 1.5 V ISD = 10A, dISD/dt = 100A/µs - - 190 ns - 1.0 - µC QRR UNITS Electrical Specifications up to 100K RAD TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL MIN MAX VGS = 0, ID = 1mA 150 - V VGS(TH) VGS = VDS, ID = 1mA 2.0 4.5 V (Notes 2, 3) IGSS VGS = ±30V, VDS = 0V - 100 nA (Note 3) IDSS VGS = 0, VDS = 120V - 25 µA VGS = 12V, ID = 10A - 1.30 V VGS = 12V, ID = 6 - 0.125 Ω Drain to Source Breakdown Volts (Note 3) BVDSS Gate to Source Threshold Volts (Note 3) Gate to Body Leakage Zero Gate Leakage Drain to Source On-State Volts (Notes 1, 3) VDS(ON) Drain to Source On Resistance (Notes 1, 3) rDS(ON)12 TEST CONDITIONS UNITS NOTES: 1. Pulse test, 300µs Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . Single Event Effects (SEB, SEGR) Note 4 ENVIRONMENT (NOTE 5) TEST Single Event Effects Safe Operating Area TYPICAL RANGE (µ) APPLIED VGS BIAS (V) (Note 7) MAXIMUM VDS BIAS (V) 37 36 -20 150 60 32 -10 150 82 28 -5 120 82 28 -10 90 SYMBOL (Note 6) TYPICAL LET (MeV/mg/cm) SEESOA NOTES: 4. Testing conducted at Brookhaven National Labs or Texas A&M. 5. Fluence = 1E5 ions/cm2 (typical), T = 25oC. 6. Ion Species: LET = 37, Br or Kr; LET = 60, I or Xe; LET = 82, Au 7. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). Performance Curves Unless Otherwise Specified LET = 37MeV/mg/cm 2 , RANGE = 36µ LET = 60MeV/mg/cm 2 , RANGE = 32µ LET = 82MeV/mg/cm 2 , RANGE = 28µ 200 FLUENCE = 1E5 IONS/cm 2 (TYPICAL) LET = 37 160 150 V DS V D S (V ) 120 100 80 LET = 82 50 40 LET = 60 TEMP = 25 o C 0 0 -4 0 -8 -12 V G S (V) -16 -20 FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA ©2001 Fairchild Semiconductor Corporation 4-3 0 5 10 15 20 25 30 35 40 -24 NE GAT IVE V G S BIA S (V) FIGURE 2. TYPICAL SEE SIGNATURE CURVE FSGL134R Rev. A1 FSGL134R Performance Curves Unless Otherwise Specified (Continued) LIMITING INDUCTANCE (HENRY) 1E-3 12 10 1E-4 ILM = 10A ID , DRAIN (A) 8 30A 1E-5 100A 300A 6 4 1E-6 2 1E-7 30 10 100 0 -50 1000 300 0 50 150 100 T C , CA SE TEMPER ATU RE ( o C) DRAIN SUPPLY (V) FIGURE 3. TYPICAL DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO I AS FIGURE 4. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE 100 I D , DRAIN CURRENT (A) T C = 25 o C 10 12V QG 1 00µs .1 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 QGS VG 10ms 10 100 QGD 500 CHARGE VDS , DRAIN-TO-SOURCE VOLTAGE (V) 2.5 N OR M A LIZED r D S(O N ) PULSE DURATION = 250ms, V GS = 12V, I D = 6A 2.0 1.5 1.0 0.5 0 -80 FIGURE 6. BASIC GATE CHARGE WAVEFORM I D , DRAIN-TO-S OURCE CURRENT (A) FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 70 V GS = 14V 60 V GS = 12V V GS = 10V 50 V G S = 8V 40 30 20 0 -40 0 40 80 120 160 T J , JUNCTION TEMPERATURE ( o C) FIGURE 7. TYPICAL NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE ©2001 Fairchild Semiconductor Corporation 4-4 VGS = 6V 10 0 2 4 6 8 10 V D S , D R A IN -T O -S O U R C E V O LTA G E (V ) FIGURE 8. TYPICAL OUTPUT CHARACTERISTICS FSGL134R Rev. A1 FSGL134R NORMALIZED THERMAL RESPONSE (ZθJC) Performance Curves Unless Otherwise Specified (Continued) 10 1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 PDM SINGLE PULSE 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 0.001 10-5 10-4 10-3 10-2 10-1 t1 t2 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 9. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE I AS , AVA L A N C H E C U R R EN T (A ) 100 STA RTING T J = 25 o C STAR TIN G T J = 150 o C 10 IF R = 0 t AV = (L) (I A S ) / (1.3 RATED BV D SS - V D D ) IF R ≠ 0 t AV = (L/R) ln [(I A S *R ) / (1.3 RATED B V DSS - V DD ) + 1] 1 .001 .01 .1 1 10 t AV , TIME IN AVALAN CH E (ms) FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L BVDSS + CURRENT I TRANSFORMER AS tP - VARY tP TO OBTAIN REQUIRED PEAK I AS VDD DUT tP VDD + 50Ω VGS ≤ 20V 0V VDS I AS 50V-150V 50Ω tAV FIGURE 11. UNCLAMPED ENERGY TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation 4-5 FIGURE 12. UNCLAMPED ENERGY WAVEFORMS FSGL134R Rev. A1 FSGL134R Test Circuits and Waveforms tON VDD tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% VDS VGS = 12V 10% DUT 10% 0V 90% R GS 50% VGS 50% PULSE WIDTH 10% FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 14. RESISTIVE SWITCHING WAVEFORMS Screening Information Screening is performed in accordance with the latest revision in effect of MIL-PRF-19500, (Screening Information Table). Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) TC = 25oC, Unless Otherwise Specified MAX UNITS Gate to Source Leakage Current PARAMETER SYMBOL IGSS VGS = ±30V TEST CONDITIONS ±20 (Note 8) nA Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value ±25 (Note 8) µA Drain to Source On Resistance rDS(ON) TC = 25oC at Rated ID ±20% (Note 9) Ω Gate Threshold Voltage VGS(TH) ID = 1.0mA ±20% (Note 9) V NOTES: 8. Or 100% of Initial Reading (whichever is greater). 9. Of Initial Reading. Screening Information TEST JANTXV EQUIVALENT Unclamped Inductive Switching V GS(PEAK) = 20V, L = 0.1mH; Limit = 40A JANS EQUIVALENT VGS(PEAK) = 20V, L = 0.1mH; Limit = 40A Thermal Response tH = 10ms; VH = 25V; IH = 1A; LIMIT = 60mV tH = 10ms; VH = 25V; IH = 1A; LIMIT = 60mV Gate Stress V GS = 45V, t = 250µs VGS = 45V, t = 250µs Pind Optional Required Pre Burn-In Tests (Note 10) MIL-PRF-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-PRF-19500 Group A, Subgroup 2 (All Static Tests at 25oC) Steady State Gate Bias (Gate Stress) MIL-PRF-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours MIL-PRF-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 10) All Delta Parameters Listed in the Delta Tests and Limits Table All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-PRF-750, Method 1042, Condition A V DS = 80% of Rated Value, TA = 150oC, Time = 160 hours MIL-PRF-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours PDA 10% 5% Final Electrical Tests (Note 10) MIL-PRF-19500, Group A, Subgroup 2 MIL-PRF-19500, Group A, Subgroups 2 and 3 NOTE: 10. Test limits are identical pre and post burn-in. Additional Tests PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Safe Operating Area SOA VDS = 120V, t = 10ms 0.7 A Thermal Impedance ∆VSD tH = 500ms; VH = 25V; IH = 1A 230 mV ©2001 Fairchild Semiconductor Corporation 4-6 FSGL134R Rev. A1 FSGL134R Rad Hard Data Packages - Fairchild Power Transistors TXV Equivalent Class S - Equivalents 1. RAD HARD TXV EQUIVALENT - STANDARD DATA PACKAGE 1. RAD HARD “S” EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance A. Certificate of Compliance B. Assembly Flow Chart B. Serialization Records C. Preconditioning - Attributes Data Sheet C. Assembly Flow Chart D. Group A - Attributes Data Sheet D. SEM Photos and Report E. Group B - Attributes Data Sheet F. Group C - Attributes Data Sheet G. Group D - Attributes Data Sheet E. Preconditioning - Attributes Data Sheet - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data 2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet - Pre and Post Burn-In Read and Record Data D. Group A - Attributes Data Sheet E. Group B - Attributes Data Sheet - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3) - Bond Strength Data (Subgroup B3) - Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6) F. Group C - Attributes Data Sheet - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6) - Bond Strength Data (Subgroup C6) G. Group D - Attributes Data Sheet - Pre and Post RAD Read and Record Data F. Group A G. Group B - Attributes Data Sheet H. Group C - Attributes Data Sheet I. Group D - Attributes Data Sheet 2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Subgroups A2, A3, A4, A5 and A7 Data G. Group B - Attributes Data Sheet - Subgroups B1, B3, B4, B5 and B6 Data H. Group C - Attributes Data Sheet - Subgroups C1, C2, C3 and C6 Data I. Group D ©2001 Fairchild Semiconductor Corporation 4-7 - Attributes Data Sheet - Attributes Data Sheet - Pre and Post Radiation Data FSGL134R Rev. A1 FSGL134R TO-205AF 3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE INCHES ØD ØD1 P A SEATING PLANE h L Øb e e1 2 e2 1 90o 3 45o j k SYMBOL MIN MILLIMETERS MAX MIN MAX NOTES A 0.160 0.180 4.07 4.57 - Øb 0.016 0.021 0.41 0.53 2, 3 ØD 0.350 0.370 8.89 9.39 - ØD1 0.315 0.335 8.01 8.50 - e 0.095 0.105 2.42 2.66 4 e1 0.190 0.210 4.83 5.33 4 e2 0.095 0.105 2.42 2.66 4 h 0.010 0.020 0.26 0.50 - j 0.028 0.034 0.72 0.86 - k 0.029 0.045 0.74 1.14 - L 0.500 0.560 12.70 14.22 3 P 0.075 - 1.91 - 5 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC TO-205AF outline dated 11-82. 2. Lead dimension (without solder). 3. Solder coating may vary along lead length, add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.100 inches (2.54mm) from bottom of seating plane. 5. This zone controlled for automatic handling. The variation in actual diameter within this zone shall not exceed 0.010 inches (0.254mm). 6. Lead no. 3 butt welded to stem base. 7. Controlling dimension: Inch. 8. Revision 3 dated 6-94. ©2001 Fairchild Semiconductor Corporation 4-8 FSGL134R Rev. A1 FSGL134R TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. FAST® FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MICROWIRE™ OPTOLOGIC™ ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS™ Ensigna™ FACT™ FACT Quiet Series™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench ® QFET™ QS™ QT Optpelectronics™ Quiet Series™ SILENTSWITCHER® SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET® VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be which, (a) are intended for surgical implant into the body, reasonably expected to cause the failure of the life support or (b) support or sustain life, or (c) whose failure to perform device or system, or to affect its safety or effectiveness. when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. ©2001 Fairchild Semiconductor Corporation 4-9 FSGL134R Rev. A1