ADC12040 12-Bit, 40 MSPS, 340mW A/D Converter with Internal Sample-and-Hold General Description Features The ADC12040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per second (MSPS), minimum. This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. Operating on a single 5V power supply, this device consumes just 340 mW at 40 MSPS, including the reference current. The Power Down feature reduces power consumption to 40 mW. The differential inputs provide a full scale differential input swing equal to 2VREF with the possibility of a single-ended input, although full use of the differential input is required for optimum performance. For ease of use, the buffered, high impedance, single-ended reference input is converted onchip to a differential reference for use by the processing circuitry. Output data format is 12-bit offset binary. This device is available in the 32-lead LQFP package and will operate over the industrial temperature range of −40˚C to +85˚C. Single +5V supply operation Internal sample-and-hold Outputs 2.35V to 5V compatible Pin Compatible with ADC12010, ADC12020, ADC12L063, ADC12L066 n Power down mode n On-chip reference buffer n n n n Key Specifications n n n n n Supply Voltage DNL SNR (fIN = 10MHz) ENOB (fIN = 10MHz) Power Consumption, 40 MHz +5V ± 5% ± 0.4 LSB (typ) 69 dB (typ) 11.2 bits (typ) 340 mW (typ) Applications n n n n n n n n Ultrasound and Imaging Instrumentation Cellular Base Stations/Communications Receivers Sonar/Radar xDSL Wireless Local Loops/Cable Modems HDTV/DTV DSP Front Ends Connection Diagram 20014801 © 2006 National Semiconductor Corporation DS200148 www.national.com ADC12040 12-Bit, 40 MSPS, 340mW A/D Converter with Internal Sample-and-Hold January 2006 ADC12040 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) Package ADC12040CIVY 32 Pin LQFP ADC12040CIVYX 32 Pin LQFP Tape and Reel ADC12040EVAL Evaluation Board Block Diagram 20014802 www.national.com 2 ADC12040 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 2 VIN+ Non-Inverting analog signal Input. 3 VIN− Inverting analog signal Input. This pin may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. 1 VREF Reference input. This pin should be bypassed to ground with a 0.1 µF monolithic capacitor. 31 VRP 32 VRM 30 VRN These pins are high impedance reference bypass pins only. Connect a 0.1 µF capacitor from each of these pins to AGND. DO NOT connect anything else to these pins. DIGITAL I/O 10 CLK Digital clock input. The input is sampled on the rising edge of CLK. 11 OE OE is the output enable pin that, when low, enables the TRI-STATE™ data output pins. When this pin is high, the outputs are in a high impedance state. 8 PD PD is the Power Down input pin. When high, this input puts the converter into the power down mode. When this pin is low, the converter is in the active mode. 3 www.national.com ADC12040 Pin Descriptions and Equivalent Circuits Equivalent Circuit (Continued) Pin No. Symbol Description 14–19, 22–27 D0–D11 Digital data output pins that make up the 12-bit conversion results. D0 is the LSB, while D11 is the MSB of the offset binary output word. Output levels are TTL/CMOS compatible. 5, 6, 29 VA Positive analog supply pins. These pins should be connected to a quiet +5V voltage source and bypassed to ground with 0.1 µF monolithic capacitors located within 1 cm of these power pins, and with a 10 µF capacitor. 4, 7, 28 AGND ANALOG POWER The ground return for the analog supply. DIGITAL POWER 13 VD 9, 12 DGND 21 20 www.national.com Positive digital supply pin. This pin should be connected to the same quiet +5V source as is VA and bypassed to ground with a 0.1 µF monolithic capacitor in parallel with a 10 µF capacitor, both located within 1 cm of the power pin. The ground return for the digital supply. Positive digital supply pin for the ADC12040’s output drivers. This pin should be bypassed to ground with a 0.1 µF monolithic capacitor. If the supply for this pin is different from the supply used for VA and VD, it should also be bypassed with a 10 µF tantalum capacitor. VDR should never exceed the voltage on VD. All bypass capacitors should be located within 1 cm of the supply pin. VDR The ground return for the digital supply for the ADC12040’s output drivers. This pin should be connected to the system ground, but not be connected in close proximity to the ADC12040’s DGND or AGND pins. See Section 5 (Layout and Grounding) for more details. DR GND 4 Operating Ratings (Notes 1, 2) (Notes 1, 2) Operating Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VD) VA, VD, VDR Package Dissipation at TA = 25˚C 250V 235˚C Storage Temperature ≤100mV Package Thermal Resistances 2500V Soldering Temperature, Infrared, 10 sec. (Note 6) −0V to (VA − 1.0V) |AGND–DGND| ESD Susceptibility Machine Model (Note 5) −0.05V to (VD + 0.05V) VIN Input See (Note 4) Human Body Model (Note 5) 0.5V to 3.0V CLK, PD, OE ± 25 mA ± 50 mA Package Input Current (Note 3) 1.0V to 2.2V VCM Input −0.3V to (VA or VD +0.3V) Input Current at Any Pin (Note 3) +2.35V to VD VREF Input ≤ 100 mV Voltage on Any Input or Output Pin +4.75V to +5.25V Output Driver Supply (VDR) 6.5V |VA–VD| −40˚C ≤ TA ≤ +85˚C Package θJA 32-Lead LQFP 79˚C / W −65˚C to +150˚C Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR = +3.0V, PD = 0V, VREF = +2.0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) 12 Bits (min) ± 1.8 ± 1.0 ± 2.1 ± 0.9 LSB (max) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL Integral Non Linearity (Note 11) DNL Differential Non Linearity GE Gain Error ± 0.7 ± 0.4 ± 0.1 Offset Error (VIN+ = VIN−) −0.1 Under Range Output Code 0 0 Over Range Output Code 4095 4095 LSB (max) %FS (max) %FS (max) DYNAMIC CONVERTER CHARACTERISTICS FPBW Full Power Bandwidth SNR Signal-to-Noise Ratio SINAD Signal-to-Noise and Distortion ENOB Effective Number of Bits THD Total Harmonic Distortion SFDR Spurious Free Dynamic Range IMD Intermodulation Distortion 0 dBFS Input, Output at −3 dB 100 fIN 1 MHz, VIN −0.5 dBFS 70 fIN = 10 MHz, VIN = −0.5 dBFS 69.5 fIN = 1 MHz, VIN = −0.5 dBFS 69.5 fIN = 10 MHz, VIN = −0.5 dBFS 69 fIN = 1 MHz, VIN = −0,5 dBFS 11.2 fIN = 10 MHz, VIN = −0,5 dBFS 11.2 fIN = 1 MHz, VIN = −0,5 dBFS −82 fIN = 10 MHz, VIN = −0,5 dBFS −80 fIN = 1 MHz, VIN = −0,5 dBFS 86 fIN = 10 MHz, VIN = −0.5 dBFS 84 fIN = 9.5 MHz and 10.5 MHz, each = −8 dBFS −75 5 MHz dB 66.5 dB (min) 66 dB (min) 10.7 Bits (min) −67 dB (max) dB Bits dB dB 68 dB (min) dBFS www.national.com ADC12040 Absolute Maximum Ratings ADC12040 Converter Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR = +3.0V, PD = 0V, VREF = +2.0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Typical (Note 10) Conditions Limits (Note 10) Units (Limits) REFERENCE AND ANALOG INPUT CHARACTERISTICS VCM Common Mode Input Voltage CIN VIN Input Capacitance (each pin to GND) VREF VIN = 2.5 Vdc + 0.7 Vrms VA/2 V (CLK LOW) 8 pF (CLK HIGH) 7 Reference Voltage (Note 13) 2.00 Reference Input Resistance 100 pF 1.0 2.2 V (min) V (max) MΩ (min) DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR = +3.0V, PD = 0V, VREF = +2.0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) (Note 10) Units (Limits) CLK, PD, OE DIGITAL INPUT CHARACTERISTICS VIN(1) Logical “1” Input Voltage VD = 5.25V 2.0 V (min) VIN(0) Logical “0” Input Voltage VD = 4.75V 1.0 V (max) IIN(1) Logical “1” Input Current VIN = 5.0V 10 µA IIN(0) Logical “0” Input Current VIN = 0V −10 µA CIN Digital Input Capacitance 5 pF D0–D11 DIGITAL OUTPUT CHARACTERISTICS VOUT(1) Logical “1” Output Voltage IOUT = −0.5 mA VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA, VDR = 3V IOZ TRI-STATE Output Current +ISC −ISC VDR = 2.5V 2.3 VDR = 3V 2.7 V (min) V (min) 0.4 V (max) VOUT = 2.5V or 5V 100 nA VOUT = 0V −100 nA Output Short Circuit Source Current VOUT = 0V −20 mA (min) Output Short Circuit Sink Current VOUT = VDR 20 mA (min) POWER SUPPLY CHARACTERISTICS IA Analog Supply Current PD Pin = DGND, VREF = 2.0V PD Pin = VDR 59 8 66 mA (max) mA ID Digital Supply Current PD Pin = DGND PD Pin = VDR, fCLK = 0 6 0 7.3 mA (max) mA IDR Digital Output Supply Current PD Pin = DGND, CL = 0 pF (Note 14) PD Pin = VDR, fCLK = 0 3 0 Total Power Consumption PD Pin = DGND, CL = 0 pF (Note 15) PD Pin = VDR, fCLK = 0 340 40 PSRR1 Power Supply Rejection Rejection of Full-Scale Error with VA = 4.75V vs. 5.25V 58 dB PSRR2 Power Supply Rejection SNR Degradation w/10 MHz, 200 mVP-P riding on VA 50 dB www.national.com 6 mA (max) mA 366 mW mW Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR = +3.0V, PD = 0V, VREF = +2.0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C (Notes 7, 8, 9, 12) Symbol Parameter Conditions Typical Limits (Note 10) (Note 10) fCLK1 Maximum Clock Frequency 50 fCLK2 Minimum Clock Frequency 100 tCH Clock High Time 11.25 tCL Clock Low Time 11.25 ns (min) tCONV Conversion Latency 6 Clock Cycles VDR = 2.5V, −45˚C < TA < +85˚C tOD Data Output Delay after Rising CLK Edge VDR = 2.5V, TA = +25˚C MHz (min) kHz ns (min) 16.3 ns (max) 12 15.9 ns (max) 15.7 ns (max) 11 14.9 ns (max) VDR = 3.0V, −45˚C < TA < +85˚C VDR = 3.0V, TA = +25˚C 40 Units (Limits) tAD Aperture Delay 1.2 ns tAJ Aperture Jitter 1.2 ps rms tDIS Data outputs into TRI-STATE ™ Mode 4 ns tEN Data Outputs Active after TRI-STATE 4 ns tPD Power Down Mode Exit Cycle 20 tCLK Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. This note does not apply to any power or ground pin. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above 183˚C is allowed per reflow cycle. Note 7: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per (Note 3). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate conversions. 20014807 Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. Note 9: With the test condition for VREF = +2.0V (4VP-P differential input), the 12-bit LSB is 977 µV. Note 10: Typical figures are at TA = TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. Note 12: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. Note 13: Optimum performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4051CIM3-ADJ (SOT-23 package) is recommended for this application. 7 www.national.com ADC12040 AC Electrical Characteristics ADC12040 AC Electrical Characteristics (Continued) Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. Note 15: Excludes IDR. See note 14. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 11⁄2 LSB below the reference voltage. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC. CONVERSION LATENCY See PIPELINE DELAY. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. For the ADC12040, PSRR1 is the ratio of the change in Full-Scale Error that results from a change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding upon the power supply is rejected at the output. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It is the difference between the Positive Full Scale Error and the Negative Full Scale Error: Gain Error = Pos. Full Scale Error − Neg. Full Scale Error SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2 LSB below the first code transition) through positive full scale (1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12040 is guaranteed not to have any missing codes. NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of 1⁄2 LSB above negative full scale (−VREF). OFFSET ERROR is the difference between the two input voltages [ (VIN+) – (VIN−) ] required to cause a transition from code 2047 to 2048. www.national.com TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first nine harmonic components to the rms value of the input signal. THD is calculated as where F1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power of the first 9 harmonic frequencies in the output spectrum. 8 ADC12040 Timing Diagram 20014809 Output Timing Transfer Characteristic 20014810 FIGURE 1. Transfer Characteristic 9 www.national.com ADC12040 Typical Performance Characteristics VA = VD = 5V, VDR = 3V, fCLK = 40 MHz, fIN = 10 MHz unless otherwise stated DNL DNL vs. VA 20014818 20014821 DNL vs. Temperature DNL vs. Clock Duty Cycle 20014819 20014822 INL INL vs. VA 20014820 www.national.com 20014823 10 INL vs. Temperature INL vs. Clock Duty Cycle 20014824 20014827 SNR vs. Temperature THD vs. Temperature 20014828 20014826 SINAD vs. Temperature SNR vs. Clock Duty Cycle 20014825 20014831 11 www.national.com ADC12040 Typical Performance Characteristics VA = VD = 5V, VDR = 3V, fCLK = 40 MHz, fIN = 10 MHz unless otherwise stated (Continued) ADC12040 Typical Performance Characteristics VA = VD = 5V, VDR = 3V, fCLK = 40 MHz, fIN = 10 MHz unless otherwise stated (Continued) THD vs. Clock Duty Cycle SINAD and ENOB vs. Clock Duty Cycle 20014832 20014833 IMD @ F1 = 9.5MHz, F2 = 10.5MHz Spectral Response 20014829 www.national.com 20014834 12 ADC12040 Functional Description Operating on a single +5V supply, the ADC12040 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The reference input is buffered to ease the task of driving that pin and the output word rate is the same as the clock frequency. The analog input voltage is acquired at the rising edge of the clock and the digital data for a given sample is delayed by the pipeline for 6 clock cycles. A logic high on the power down (PD) pin reduces the converter power consumption to 40 mW. Applications Information 20014811 FIGURE 2. Expected Input Signal Range 1.0 OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC12040: 4.75V ≤ VA ≤ 5.25V VD = VA 2.35V ≤ VDR ≤ VD The ADC12040 performs best with a differential input with each input centered around a VCM. The peak-to-peak voltage swing at VIN+ and VIN− should EACH not exceed the value of the reference voltage or the output data will be clipped. The two input signals should be exactly 180˚ out of phase from each other and of the same amplitude. For single frequency inputs, angular errors result in a reduction of the effective full scale input. For a complex waveform, however, angular errors will result in distortion. For angular deviations of up to 10 degrees from these two signals being 180 out of phase, the full scale error in LSB can be described as approximately EFS = 4096 ( 1 - sin (90˚ + dev)) Where dev is the angular difference between the two signals having a 180˚ relative phase relationship to each other (see Figure 3). Drive the analog inputs with a source impedance less than 100Ω. 100 kHz ≤ fCLK ≤ 50 MHz 1.0V ≤ VREF ≤ 2.2V 0.5V ≤ VCM ≤ 3.0V 0V ≤ VIN ≤ (VA − 1.0V) VREF and VCM must be such that the signal swing remains within the limits of 0V to VA. 1.1 Analog Inputs The ADC12040 has two signal input pins, VIN+ and VIN−, forming a differential input pair, and one reference input pin, VREF. 1.2 Reference Pins The ADC12040 is designed to operate with a 2.0V reference, but performs well with reference voltages in the range of 1.0V to 2.2V. Lower reference voltages will decrease the signal-to-noise ratio (SNR). Increasing the reference voltage (and the input signal swing) beyond 2.2V will degrade THD for a full-scale input. It is important that all grounds associated with the reference voltage and the input signal make connection to the ground plane at a single point to minimize the effects of noise currents in the ground path. The three Reference Bypass Pins (VRP, VRM and VRN) are made available for bypass purposes only. These pins should each be bypassed to ground with a 0.1 µF capacitor. DO NOT LOAD these pins. 20014812 FIGURE 3. Angular Errors Between the Two Input Signals Will Reduce the Output Level For differential operation, each analog input signal should have a peak-to-peak voltage equal to the input reference voltage, VREF, and be centered around a VCM. 1.3 Signal Inputs The signal inputs are VIN+ and VIN−. The input signal, VIN, is defined as VIN = (VIN+) – (VIN−) Figure 2 shows the expected input signal range. Note that the common mode input voltage range is 1V to 3V with a nominal value of VA/2. The input signals should remain between ground and 4V. The Peaks of the individual input signals (VIN+ and VIN−) should each never exceed the voltage described as VIN+, VIN− = VREF/2 + VCM ≤ 4V to maintain THD and SINAD performance. TABLE 1. Input to Output Relationship – Differential Input 13 VIN+ VIN− Output VCM − VREF/2 VCM + VREF/2 0000 0000 0000 VCM − VREF/4 VCM + VREF/4 0100 0000 0000 VCM VCM 1000 0000 0000 VCM + VREF/2 VCM − VREF/4 1100 0000 0000 VCM + VREF/2 VCM − VRE/2F 1111 1111 1111 www.national.com ADC12040 Applications Information 2.1 The CLK Input (Continued) The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the range of 100 kHz to 50 MHz with rise and fall times of less than 3ns. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90˚. If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the lowest sample rate to 100 ksps. The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise duty cycle is difficult, the ADC12040 is designed to maintain performance over a range of duty cycles. While it is specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over a clock duty cycle range of 45% to 55% at 40 MHz. The clock line should be terminated at its source in the characteristic impedance of that line. It is highly desirable that the the source driving the ADC CLK input only drive that pin. However, if that source is used to drive other things, each driven pin should be a.c. terminated with a series RC to ground, as shown in Figure 4, such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is TABLE 2. Input to Output Relationship – Single-Ended Input VIN+ VIN− Output VCM − VREF VCM 0000 0000 0000 VCM − VREF/2 VCM 0100 0000 0000 VCM VCM 1000 0000 0000 VCM + VREF/2 VCM 1100 0000 0000 VCM +VREF VCM 1111 1111 1111 1.3.1 Single-Ended Operation Single-ended performance is lower than with differential input signals, so single-ended operation is not recommended. However, if single-ended operation is required and the resulting performance degradation can be tolerated, one of the analog inputs should be connected to the d.c. common mode voltage of the driven input. The peak-to-peak differential input signal should be twice the reference voltage to maximize SNR and SINAD performance (Figure 2b). For example, set VREF to 1.0V and bias VIN− to 1.0V and drive VIN+ with a signal range of 0V to 2.0V. Because very large input signal swings can degrade distortion performance, better performance with a single-ended input can be obtained by reducing the reference voltage while maintaining a full-range output. Table 1 and Table 2 indicate the input to output relationship of the ADC12040. 1.3.2 Driving the Analog Inputs The VIN+ and the VIN− inputs of the ADC12040 consist of an analog switch followed by a switched-capacitor amplifier. The capacitance seen at the analog input pins changes with the clock level, appearing as 8 pF when the clock is low, and 7 pF when the clock is high. Although this difference is small, a dynamic capacitance is more difficult to drive than is a fixed capacitance, so choose the driving amplifier carefully. The LMH6550, the LMH6702 and the LMH6628 are a good amplifiers for driving the ADC12040. The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving source tries to compensate for this, it adds noise to the signal. To prevent this, use an RC at each of the inputs, as shown in Figure 5 and Figure 6. These components should be placed close to the ADC because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter the input. The capacitor is for Nyquist applications and should be eliminated for undersampling applications. where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and tPD should be the same (inches or centimeters). Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 or AN-1113 for information on setting and determining characteristic impedance 2.2 The OE Input The OE input, when high, puts the output pins into a high impedance state. When this input is low the outputs are in the active state. The ADC12040 will continue to convert whether this input is high or low, but the output can not be read while the OE input is high. The OE input should NOT be used to multiplex devices together to drive a common bus as this will result in excessive capacitance on the data output pins, reducing SNR and SINAD performance of the converter. See Section 3.0. 1.3.3 Input Common Mode Voltage The input common mode voltage, VCM, should be in the range indicated in Section 1.0 and be of a value such that the peak excursions of the analog input signal do not go more negative than ground or more positive than the VA supply voltage. The nominal VCM should generally be equal to VREF/2, but VRM can be used as a VCM source as long as VRM need not supply any d.c. current. 2.3 The PD Input The PD input, when high, holds the ADC12040 in a powerdown mode to conserve power when the converter is not being used. The power consumption in this state is 70 mW with a 40MHz clock and 40mW if the clock is stopped. The output data pins are undefined in this mode. The data in the pipeline is corrupted while in the power down mode. The Power Down Mode Exit Cycle time is determined by the value of the capacitors on pins 30, 31 and 32. These capacitors loose their charge in the Power Down mode and must be charged by on-chip circuitry before conversions can be accurate. 2.0 DIGITAL INPUTS Digital inputs consist of CLK, OE and PD. www.national.com 14 analog circuitry, degrading dynamic performance. Adequate power supply bypassing and careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 20 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic performance. To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by connecting buffers (74AC541, for example) between the ADC outputs and any other circuitry. Only one driven input should be connected to each output pin. Additionally, inserting series 100Ω resistors at the digital outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4. While the ADC12040 will operate with VDR voltages down to 1.8V, tOD increases with reduced VDR. Be careful of external timing when using reduced VDR. (Continued) 3.0 DATA OUTPUTS The ADC12040 has 12 TTL/CMOS compatible Data Output pins and the output format is offset binary. Valid offset binary data is present at these outputs while the OE and PD pins are low. While the tOD time provides information about output timing, a simple way to capture a valid output is to latch the data on the edge of the conversion clock (pin 10). Which edge to use will depend upon the clock frequency and duty cycle. If the rising edge is used, the tOD time can be used to determine maximum hold time acceptable of the driven device data inputs. If the falling edge of the clock is used, care must be taken to be sure that adequate setup and hold times are allowed for capturing the ADC output data. Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can cause on-chip noise that can couple into the 20014813 FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer 20014814 FIGURE 5. Differential Drive Circuit of Figure 4 15 www.national.com ADC12040 Applications Information ADC12040 Applications Information (Continued) 20014815 FIGURE 6. Driving the Signal Inputs with a Transformer process. To prevent this from happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the ADC12040’s other ground pins. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families. In high speed circuits, however, it is often necessary to use these higher speed devices. Best performance requires careful attention to PC board layout and to proper signal integrity techniques. The effects of the noise generated from the ADC output switching can be minimized through the use of 47Ω to 100Ω resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible. 4.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor within a centimeter of each power pin. Leadless chip capacitors are preferred because they have low series inductance. As is the case with all high-speed converters, the ADC12040 is sensitive to power supply noise. Accordingly, the noise on the analog supply pin should be kept below 150 mVP-P. No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be especially careful of this during turn on and turn off of power. The VDR pin provides power for the output drivers and may be operated from a supply in the range of 2.35V to VD (nominal 5V). This can simplify interfacing to 3V devices and systems. DO NOT operate the VDR pin at a voltage higher than VD. 5.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate analog and digital areas of the board, with the ADC12040 between these areas, is required to achieve specified performance. The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output current can exhibit high transients that could add noise to the conversion www.national.com 16 ADC12040 Applications Information (Continued) 20014816 FIGURE 7. Example of a Suitable Layout Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. Generally, analog and digital lines should cross each other at 90˚ to avoid crosstalk. To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the generally accepted 90˚ crossing should be avoided with the clock line as even a little coupling can cause problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to degradation of SNR. Also, the high speed clock can introduce noise into the analog chain. Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the signal path through all components should form a straight line wherever possible. Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies beside each other. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. Figure 7 gives an example of a suitable layout. A single ground plane is recommended with separate analog and digital power planes. The analog and digital power planes should NOT overlap each other. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed over the analog power plane. All digital circuitry and I/O lines should be placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the ground plane at a single point. All ground connections should have a low inductance path to ground. 6.0 DYNAMIC PERFORMANCE To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 8. As mentioned in Section 5.0, it is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90˚ crossings have capacitive coupling, so try to avoid even these 90˚ crossings of the clock line. 20014817 FIGURE 8. Isolating the ADC Clock from other Circuitry with a Clock Tree 17 www.national.com ADC12040 Applications Information by adding series resistors at each digital output, close to the ADC12040, which reduces the energy coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors is 100Ω. (Continued) 7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 300 mV beyond the supply rails (more than 300 mV below the ground pins or 300 mV above the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot that goes above the power supply or below ground when their output lines are not properly terminated. A resistor of about 33Ω to 47Ω in series with any offending digital input, close to the signal source, should eliminate the problem. Using an inadequate amplifier to drive the analog input. As explained in Section 1.3, the capacitance seen at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is more difficult to drive than is a fixed capacitance. If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade performance. A small series resistor and shunt capacitor at each amplifier output (as shown in Figure 5 and Figure 6) will improve performance. The LMH6550 , the LMH6702 and the LMH6628 have been successfully used to drive the analog inputs of the ADC12040. Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180o out of phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will affect the effective phase between these two signals. Remember that an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same device operating in the inverting configuration. Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, VREF should be in the range of 1.0V ≤ VREF ≤ 2.2V Operating outside of these limits could lead to performance degradation. Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or power down. Be careful not to overdrive the inputs of the ADC12040 with a device that is powered from supplies outside the range of the ADC12040 supply. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem. Additionally, bus capacitance beyond that specified will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could, again, be an apparent reduction in dynamic performance. The digital data outputs should be buffered (with 74AC541, for example). Dynamic performance can also be improved www.national.com Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR and SINAD performance. 18 inches (millimeters) unless otherwise noted 32-Lead LQFP Package Ordering Number ADC12040CIVY NS Package Number VBE32A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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