ETC HE84G761(S)

KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE84G761
HE80004 Series
- Table of Contents 1.
General Description ___________________________________________________________________3
2.
Features _____________________________________________________________________________3
3.
Functional Block Diagram ______________________________________________________________4
4.
Pin Description _______________________________________________________________________4
5.
ROM Map Configurations______________________________________________________________6
6.
External RAM/Flash Memory___________________________________________________________9
7.
LCD Display RAM Map ______________________________________________________________10
8.
LCD driver configurations_____________________________________________________________11
8.1.
16 Gray Scale LCD Display RAM Map ________________________________________________12
8.2.
4 Gray Scale LCD Display RAM Map _________________________________________________18
8.3.
Black and White LCD Display RAM Map______________________________________________21
9.
LCD Power Supply ___________________________________________________________________24
10.
LCDC Control register _____________________________________________________________25
11.
Oscillators ________________________________________________________________________26
12.
General Purpose I/O _______________________________________________________________27
13.
Timer1 ___________________________________________________________________________29
14.
Timer2 ___________________________________________________________________________30
15.
Time Base ________________________________________________________________________31
16.
Watch Dog Timer __________________________________________________________________32
17.
Voice Output ______________________________________________________________________33
18.
Low Voltage Detection/Reset _________________________________________________________37
19.
Infrared output____________________________________________________________________38
20.
Universal Asynchronous Receiver/Transmitter__________________________________________40
20.1.
Interface Registers _________________________________________________________________41
20.2.
Baud Rate Configuration Register ____________________________________________________41
20.3.
Interrupt & Identification Register ___________________________________________________42
20.4.
Line Control Register_______________________________________________________________43
June 30, 2003
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This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE84G761
HE80004 Series
20.5.
Line Status Register ________________________________________________________________44
21.
Extension Register Access ___________________________________________________________45
22.
Summary of Registers and Mask Options ______________________________________________45
23.
Absolute Maximum Rating __________________________________________________________48
24.
Recommended Operating Conditions _________________________________________________48
25.
AC/DC Characteristics _____________________________________________________________48
26.
Application Circuit_________________________________________________________________50
27.
Important Note ____________________________________________________________________52
28.
Updated History ___________________________________________________________________52
June 30, 2003
2
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE84G761
HE80004 Series
1. General Description
HE84G761 is a member of 8-bit Micro-controller series developed by King Billion Electronics. External
address and data buses are provided to access external memory. This chip has 4096 pixel, 16 gray-scale
LCD driver built-in with 4 different configurations, and up to 34-bit general purpose I/O ports. The
built-in OP comparator can be used with light, voice, temperature and humility sensor or used to detect
the battery low. The 7/8 bits current-type D/A converter and PWM driver output provides the complete
speech output solutions. The 384K bytes ROM and 5K bytes RAM can be used for the storage of large
speech data, image and text, etc. An UART is included to provide the serial communication capability. IR
output makes it suitable for remote control applications.
The instruction sets of HE80000 series is easy to learn and simple to use. There are only thirty-two
instructions and four addressing modes. Most of instructions take only 3 oscillator clocks to complete.
The performance and low power consumption make it suitable for battery-powered applications such as
translator, data bank, educational toy, digital voice recorder, etc.
2. Features
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Operation Voltage:
Dual Clock System:
2.4V ~ 3.6V
Fast clock
32768 Hz ~ 8 MHz
Slow clock
32768 Hz
Four operation modes: Fast, Slow, Idle, Sleep modes.
Internal Program ROM: 384K bytes
Internal RAM:
5 K bytes
External memory buses to interface external Mask ROM, EPROM, NOR FLASH memory, etc.
22 ~ 34 bi-directional general-purpose I/O ports with push-pull or Open-Drain output type
selectable for each I/O pin by mask option.
Up to 4096 pixels 16, 4 gray-scale or Black/White LCD driver.
Segment extender interface with KDGS80 and KDGS80.
4 LCD configurations (COM X SEG): 32 COM x 96 SEG, 48 COM x 80 SEG, 64 COM x 64
SEG, 80 COM x 48 SEG.
Built-in LCD power supply with regulator and 3, 4, and 5 times charge pump circuit.
One 7/8-bit current-type D/A converter.
One 7/8-bit PWM output.
One built-in OP comparator.
Built-in UART for serial communication.
IR output.
Low voltage reset: 2.2V
Low voltage detection: 2.4V, 2.6V, 2.8V and 3.0V
Two external interrupts, three internal timer interrupts and extension UART interrupt
Watch dog timer to prevent deadlock condition.
Two 16-bit timers and one time-base timer.
Instruction set: 32 instructions, 4 addressing mode.
June 30, 2003
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V1.01
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COM[31..0]
LVL1
LVL2
LVL3
LVL4
LVL5
Pin Name
June 30, 2003
3 ~ 34
35
36
37
38
39
O
P
P
P
P
P
TC2
I/O Port
WDT
UART
LVR
PRT17[1]/SEG1
PRT17[0]/SEG0
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
Pin # I/O
4
IR
PRTD[2]/WKUP[0]
PRTD[1]/SIN
PRTD[0]/SOUT
PRTC[7]
PRTC[6]
PRTC[5]
PRTC[4]
PRTC[3]
PRTC[2]
PRTC[1]
PRTC[0]
VDD_RAM
IRO
PWM
GND_PWM
TC1
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
384 KB ROM
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
SIN, SOUT
8 Bit CPU
CMSG74
CMSG73
CMSG72
CMSG71
CMSG70
CMSG69
CMSG68
CMSG67
CMSG66
CMSG65
CMSG64
CMSG63
CMSG62
CMSG61
CMSG60
CMSG59
CMSG58
CMSG57
CMSG56
CMSG55
CMSG54
CMSG53
CMSG52
PRTC, PRTD, PRT10,
PRT17
VO
RSTP_N
FXO
FXI
TSTP_P
SXO
SXI
VX
VDD
PRT10[7]
PRT10[6]
PRT10[5]
PRT10[4]
PRT10[3]
PRT10[2]
PRT10[1]
PRT10[0]
PRTD[7]/INT2/WKUP[5]
PRTD[6]/INT1/WKUP[4]
PRTD[5]/WKUP[3]
PRTD[4]/WKUP[2]
PRTD[3]/WKUP[1]
Ext. Memory
Interface
DAO
Segment Ext.
Interface
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
LCD Power
Supply
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
SEGA, SEGD
LCD
Driver
57
U14
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
SEG
COM
SEG27/A[11]
SEG28/A[12]
SEG29/A[13]
SEG30/A[14]
SEG31/A[15]
SEG32/A[16]
SEG33/A[17]
SEG34/A[18]
SEG35/A[19]
SEG36/A[20]
SEG37/A[21]
SEG38/A[22]
SEG39/A[23]
SEG40/D[0]
SEG41/D[1]
SEG42/D[2]
SEG43/D[3]
SEG44/D[4]
SEG45/D[5]
SEG46/D[6]
SEG47/D[7]
CMSG79
CMSG78
CMSG77
CMSG76
CMSG75
PRT17[2]/SEG2
PRT17[3]/SEG3
PRT17[4]/SEG4
PRT17[5]/SEG5
PRT17[6]/SEG6
PRT17[7]/SEG7
PRT15[0]/SEG8
PRT15[1]/SEG9
SEG10/CS3
SEG11/CS2
SEG12/CS1
SEG13/CS0
SEG14/WE
SEG15/OE
SEG16/A[0]
SEG17/A[1]
SEG18/A[2]
SEG19/A[3]
SEG20/A[4]
SEG21/A[5]
SEG22/A[6]
SEG23/A[7]
SEG24/A[8]
SEG25/A[9]
SEG26/A[10]
OLFR, OCCK
LVL1
LVL2
LVL3
LVL4
LVL5
LGS2
LVP
LCAP4A
LCAP2B
LCAP2A
LCAP1A
LCAP1B
LCAP3A
LVREG
LGS1
LVAG
OLFR
OCCK
GND
OPO
OPIP
OPIN
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
LVP, LVL[5..1], LGS1,
LGS2, LCAP?A, LCAP?B
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
21
22
23
24
25
26
27
28
29
30
31
32
33
34
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE84G761
HE80004 Series
3. Functional Block Diagram
Fast Clock
OSC.
Slow Clock
OSC
OP Amp
FXI, FXO
SXI, SXO
5 KB RAM
PWM
PWM
DAC
VO, DAO
TBI
OPO,OPIN, OPIP
IRO
LVD
4. Pin Description
HE84G763
CMSG51
CMSG50
CMSG49
CMSG48
CMSG47
CMSG46
CMSG45
CMSG44
CMSG43
CMSG42
CMSG41
CMSG40
CMSG39
CMSG38
CMSG37
CMSG36
CMSG35
CMSG34
CMSG33
CMSG32
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
LCD COMMON Driver pads.
LCD Bias Voltage 1.
LCD Bias Voltage 2
LCD Bias Voltage 3
LCD Bias Voltage 4
LCD Bias Voltage 5.
Description
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KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Pin Name
Pin # I/O
LGS2
LVP
LCAP4A
LCAP2B
LCAP2A
LCAP1A
LCAP1B
LCAP3A
40
41
42
43
44
45
46
47
I
P
O
O
O
O
O
O
LVREG
48
O
LGS1
LVAG
OLFR
OCCK
GND
OPO
OPIP
OPIN
DAO
VO
49
50
51
52
53
54
55
56
57
58
I
O
O
O
P
O
I
I
O
O
RSTP_N
59
I
FXO,
FXI
60,
61
O,
B
TSTP_P
62
I
SXO,
SXI
63,
64
O,
I
VX
65
I
VDD
66
P
PRT10[7..0]
67~74
B
PRTD[7..2]
PRTD[1]/SIN
PRTD[0]/SOUT
75~82
B
PRTC[7:0]
83~90
B
VDD_RAM
IRO
91
92
P
O
PWM
93
O
GND_PWM
94
P
June 30, 2003
HE84G761
HE80004 Series
Description
LCD Drive Voltage Setting
Charge Pump Output.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns
pumped to LVP. Adjust resistor between LGS1 and LVREG to set LVREG voltage.
Regulator Voltage Setting
Reference Voltage Output. Fixed 0.9 Volt DC reference voltage
LCD frame signal for interfacing with LCD segment extender KDGS80.
LCD data load pin for interfacing with LCD segment extender KDGS80.
Power ground Input.
Output of OP Amp.
Non-inverting input of OP Amp.
Inverting input of OP Amp.
Alternate output of DAC.
DAC Output.
System Reset input pin. Level trigger, active low on this pin will put the chip in reset
state.
External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (‘0’ for
RC type and ‘1’ for crystal type). For RC type oscillator, one resistor needs to be
connected between FXI and GND. For crystal oscillator, one crystal needs to be placed
between FXI and FXO. Please refer to application circuit for details.
Test input pin. Please bond this pad and reserve a test point on PCB for debugging. But
for improving ESD, please connect this point with zero Ohm resistor to GND.
External slow clock pins. Slow clock is clock source for LCD display, TIMER1,
Time-Base and other internal blocks. Both crystal and RC oscillator are provided. The
slow clock type can be selected by mask option MO_SXTAL. Choose ‘0’ for RC type
and ‘1’ for crystal oscillator.
Input pin for x32 PLL circuit. Connect to external resistor and capacitors as shown in
application circuit.
Positive power Input. A 0.1 µF decoupling capacitors should be placed as close to IC
VDD and GND pads as possible for best decoupling effect.
8-bit bi-directional I/O port 10. The output type of I/O pad can also be selected by mask
option MO_10PP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
pad as input pad, “1” must be outputted before reading.
8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by mask
option MO_DPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
input, ‘1’ must be outputted before reading the pin.
PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt
sources.
PRTD[1] shares pad with UART Receiver SIN pin.
PRTD[0] shares pad with UART transmitter SOUT pin.
8-bit bi-directional I/O port C. The output type of I/O pad can also be selected by mask
option MO_CPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
input, ‘1’ must be outputted before reading the pin.
Dedicated power input for RAM
The Infrared output.
The PWM output can drive speaker or buzzer directly. Using VDD & PWM to drive
output device.
Dedicated Ground for PWM output.
5
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KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Pin Name
Pin # I/O
HE84G761
HE80004 Series
Description
COM[32..79] pads are shared with SEG[95..48] outputs. The functions of the pads to be
CMSG[32..79]
95~142 O COM drivers or SEG drivers can be selected by mask option MO_COM[1..0]. Please
refer to LCD driver configuration for details.
143~
SEG[47..40]/D[7..0]
O LCD segment SEG[47..40] outputs share pads with data bus D[7..0] of external memory.
150
LCD segment SEG[39..16] outputs share pads with address bus A[23..0] of external
151~
O
SEG[39..16]/A[23..0]
memory.
174
Output Enable control of external memory shares pad with SEG[15]. The function of the
pin is selected by mask option MO_EXMEM.
OE/SEG15
175
O
When used as Output Enable control pin, this pin control the tri-state buffer of external
memory data bus.
Write Enable control of external memory shares pad with SEG[14]. The function of the
pin is selected by mask option MO_ EXMEM.
WE/SEG14
176
O
When used as Write Enable control pin, this pin controls Write Enable input of the
external memory device.
Chip Select 0 of external memory shares pad with SEG[13]. The function of the pin is
selected by mask option MO_ EXMEM.
CS0/SEG13
177
O
When used as Chip Enable control pin, this pin select or de-select the external memory
device based on the address been accessed.
Chip Select 1 of external memory shares pad with SEG[12]. The function of the pin is
selected by mask option MO_ EXMEM.
CS1/SEG12
178
O
When used as Chip Enable control pin, this pin select or de-select the external memory
device based on the address been accessed.
Chip Select 2 of external memory shares pad with SEG[11]. The function of the pin is
selected by mask option MO_ EXMEM.
CS2/SEG11
179
O
When used as Chip Enable control pin, this pin select or de-select the external memory
device based on the address been accessed.
Chip Select 3 of external memory shares pad with SEG[10]. The function of the pin is
selected by mask option MO_ EXMEM.
CS3/SEG10
180
O
When used as Chip Enable control pin, this pin select or de-select the external memory
device based on the address been accessed.
2-bit bi-directional I/O port 15 is shared with LCD segment pads SEG[9..8]. The function
of the pad can be selected individually by mask options MO_LIO15[1..0]. (‘1’ for LCD
and ‘0’ for I/O).
181~ B/
PRT15[1..0]/SEG[9..8]
The output type of I/O pad can also be selected by mask option MO_15PP[1..0] (1 for
182
O
push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
input, “1” must be outputted before reading.
8-bit bi-directional I/O port 17 is shared with LCD segment pads SEG[7..0]. The function
of the pad can be selected individually by mask options MO_LIO17[7..0]. (‘1’ for LCD
and ‘0’ for I/O).
183~
B/
PRT17[7..0]/SEG[7..0] 188, 1,
The output type of I/O pad can also be selected by mask option MO_17PP[7..0] (1 for
O
push-pull and ‘0’ for open-drain).
2
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
input, “1” must be outputted before reading.
I: Input, O: Output, B: Bidirectional, P: Power.
5. ROM Map Configurations
The chip has built-in 384K bytes internal ROM. In addition, address and data buses are provided to access
External ROM. The MCU can access up to 4M bytes program ROM and up to 16M bytes data space
through external buses. The SEG[47..40], SEG[39..16] pads are used as either data and address buses for
external ROM or LCD segment driver pads depending on the mask option MO_EXMEM. When the
external ROM mask option is selected, the MCU will retrieve the instructions and data from external
June 30, 2003
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KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE84G761
HE80004 Series
ROM through the address and data buses.
The bit 14 ~ 15 bit of 16-bit logical program address can be mapped to any one (16K bytes per page) of
256 pages through mapping registers PSA1, PSA2, PSA3. As logical page 0 can not be moved and is
always physical page 0, the PSA1 ~ PSA3 contain the physical page addresses of logical pages 1 ~ 3.
Logical Address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Page Addr. A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A[15..14]
00
01
10
11
Register Address
PSA1
0x2C
PSA2
0x2D
PSA3
0x2E
Type
R/W
R/W
R/W
Logical Page Physical Page Address
0
0
1
PSA1
2
PSA2
3
PSA3
A21
A21
A21
A20
A20
A20
A19
A19
A19
Physical Address
00A[13..0]
PSA1+A[13..0]
PSA2+A[13..0]
PSA3+A[13..0]
Bits Definition
A18
A17
A18
A17
A18
A17
A16
A16
A16
A15
A15
A15
A14
A14
A14
Reset
0x01
0x02
0x03
There are four configurations for external memory as determined by mask option MO_PMODE. For
example, when option 0 is selected, 384K bytes of internal ROM will occupy the address range from
0x000000 ~ 0x05FFFF of memory space, while CS1 controls external memory device whose address
ranges from 0x200000 to 3FFFFF, etc.
MO_ PMODE [1..0] Configuration
00
Option 0
01
Option 1
June 30, 2003
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HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
10
11
Option0
Int. PROM
(384KB)
Unused
CS0
Address
000000
060000
100000
Option 2
Option 3
Option1
Address
000000
Address
000000
060000
100000
CS0
200000
Option2
Int. PROM
(384KB)
Unused
CS0
200000
CS1
100000
CS1
Int. PROM
(384KB)
Unused
360000
3FFFFF
400000
CS2
CS0
300000
CS1
3FFFFF
400000
Option3
Address
000000
2FFFFF
CS1
3FFFFF
400000
HE80004 Series
400000
Unused
CS2
600000
CS2
7FFFFF
800000
7FFFFF
800000
7FFFFF
800000
CS3
CS2
FFFFFF
CS3
FFFFFF
Legend:
Int. Program
Ext. Bus Interface
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
CS3
CS2
CS1
CS0
WE
OE
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
7FFFFF
800000
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FFFFFF
Int. Data
VCC
A18
A17
A14
A13
A8
A9
A11
OE/VPP
A10
CE
Q7
Q6
Q5
Q4
Q3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FFFFFF
Ext. Program
VDD
8 MB EPROM
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
A18
A17
A14
A13
A8
A9
A11
C89
0.1uF
A10
CS0
Q7
Q6
Q5
Q4
Q3
A16
A15
A14
A13
A12
A11
A9
A8
WE
A18
A7
A6
A5
A4
A3
A2
A1
M27C801
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A19
A18
A8
A7
A6
A5
A4
A3
A2
A1
CS1
D0
Q1
Q2
Q3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CS3
16 MB EPROM
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BY TE
VSS
Q15A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Ext. Data
Intel NOR FLASH
1
2 A16
3 A15
4 A14
5 A13
6 A12
7 A11
8 A9
9 A8
10 WE
11 RP
12 VPP
13 WP
14 A18
15 A7
16 A6
17 A5
18 A4
19 A3
20 A2
A1
A17
GND
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCCQ
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE
GND
CE
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE
CE
A0
28F320-TSOP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A20
A9
A10
A11
A12
A13
A14
A15
A16
A17
A11
A9
A8
A13
WE
A17
A15
VDD
A0
Q7
Q6
Q5
Q4
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
512KB x 8 SRAM
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
IO7
IO6
IO5
IO4
IO3
GND
IO2
IO1
IO0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS3
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
LP62S4096-TSOP
VDD
M27C160
June 30, 2003
8
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE80004 Series
6. External RAM/Flash Memory
The external memory devices can be mask ROM, static RAM, or NOR type FLASH memory. Most NOR
type FLASH memory and RAM can be used as external storage for both program and data, so program
can be downloaded to external memory devices for future execution. However, there are some limitations.
When the data is to be written to external devices, the loader must reside in internal program space. In
other words, the loader program must be in internal ROM. When download is completed, the program in
the external memory can be run.
The data written to external memory devices is through a command interface composed of AC, EXMC
and EXMD registers for setting up the memory addresses, switching memory buses, generating read/write
pulse, read/write memory contents, etc. When writing finishes, external memory can be switched back the
external address and data bus for CPU to fetch data and instructions.
Writing to address registers is through a common register AC. Writing to AC will write data to ACL, ACH,
and then ACP in cyclic order. The sequence will be reset by an access to EXMD register. Therefore, it is
advisable to make a dummy read to EXMD register before writing to AC, so that the first write will be
made to ACL.
AC
Mode
Description
ACL
R/W Address Counter Low for AC7 ~ AC0
ACH
R/W Address Counter High for AC15 ~ AC8
ACP
R/W Address Counter Page for AC23 ~ AC16
ACL: Lowest Significant Byte of Address Counter.
ACH: 2nd Byte of Address Counter.
ACP: Most Significant Byte of Address Counter.
Register Mode Description
EXMC
W
DNLD: Switch the bus to download bus.
RD: Read pulse control.
WR: Write pulse control.
-
-
Reset Value
“--------“
“--------“
“--------“
DNLD
RD
WR
Reset Value
“-----011”
After address setup, the data can be written to address device through EXMD register. Program must
generate the required write pulse by firmware. The address counter AC will automatically increment with
each read/write access.
Register
EXMD
Type
R/W
D7
D6
D5
Description
D4
D3
D2
D1
D0
Reset Value
“--------“
The procedure for downloading data from I/O or any other sources, i.e. command mode ROM device is as
follows:
1.
Switch the external memory to download bus by setting the DNLD bit of EXMC register.
June 30, 2003
9
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
2.
3.
4.
5.
6.
HE80004 Series
Make a dummy read to EXMD register to reset the AC pointer.
Set up the address for transferring data by first writing to ACL, and then ACH and ACP with the first
3 writes to register.
Start writing to addressed device by first writing 1 byte of data to EXMD register, clear WR bit of
CMD register and set it again, the AC will increment with each write pulse.
To read addressed device, clear RD bit of EXMC register, read EXMD register and set RD bit again.
The AC will also increment with each read pulse. Read back for verification is optional. Please note
that read back can also be made through external address and data bus when the bus is switched back
to program bus.
Switch back to normal bus for program execution and data access by clearing the DNLD bit of
EXMC register.
Please note that NOR FLASH memory from different manufacturers such as Intel, AMD, SST, etc.
requires various command sequence to set up. Programmer still needs to follow the respective
specifications of the vendors.
7. LCD Display RAM Map
The gray-scale LCD driver can be configured to be a 16 gray-scale, 4 gray-scales or black and white
display by mask option MO_GRAY_MODE.
MO_GRAY_MODE[1..0]
00
01
10
11
Gray levels
16
4
2 (B/W)
2 (B/W)
For 4 gray-scale display, 2-bit of RAM is required for each pixel and 4 bit for 16 gray-scale display, 1-bit
for black and white display. For different LCD configuration, the LCD display RAM is arranged
differently. The following figure shows one byte of RAM in different LCD configurations:
0F
xx
0E
xx
0D
xx
Black/White
4 Gray scales
16 Gray scales
0C
xx
0B
xx
0A
xx
09
xx
08
xx
07
xx
Bit 7
Bit 6
Bit 5
Bit 4
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
06
xx
05
xx
04
xx
03
xx
02
xx
01
xx
00
xx
Bit 3
Bit 2
Bit 1
Bit 0
SEG3
SEG2
SEG1
SEG0
SEG1
SEG0
SEG0
The 16 Gray Scale register GRAY0 ~ GRAYF is the mapping register between the levels selected in
RAM and the real gray scale. In other words, if the content of GRAY0 is 0x03, when value of a certain
June 30, 2003
10
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE84G761
HE80004 Series
pixel is 0, the displayed effect will correspond to actual gray level 3. The 16 gray scale display use all 16
registers GRAY0 ~ GRAYF to select among 32 available gray levels to correspond to level 0 ~ 15, while
4 gray scale display utilizes registers GRAY0 ~ GRAY3 to select among 32 gray levels to correspond to
level 0 ~ 3. Thus user can pick the gray levels which give the best and most linear effect.
16 Gray Scale registers share a common register address GRAY16. When writing is made to the register,
it will step down to next register in order. The writing sequence can be reset by clearing bit 5 of LCDC
register.
GRAY16
Seq.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Bit4
Bit3
Field
Bit2
Bit1
Bit0
GRAY0
GRAY1
GRAY2
GRAY3
GRAY4
GRAY5
GRAY6
GRAY7
GRAY8
GRAY9
GRAYA
GRAYB
GRAYC
GRAYD
GRAYE
GRAYF
Reset
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
8. LCD driver configurations
There are 4 LCD configurations selectable by mask option MO_COM[1..0] for this chip. The function of
CMSG[79..64] in each configuration is listed in the following table.
MO_COM[1..0]
00
01
10
11
June 30, 2003
Configuration
COM x SEG
32 x 96
48 x 80
64 x 64
80 x 48
CMSG[79..64]
Function
SEG[48..63]
SEG[48..63]
SEG[48..63]
COM[79..64]
11
CMSG[63..48]
Function
SEG[64..79]
SEG[64..79]
COM[63..48]
COM[63..48]
CMSG[47..32]
Function
SEG[80..95]
COM[47..32]
COM[47..32]
COM[47..32]
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
COMXSEG
CMSG32
CMSG33
CMSG34
CMSG35
CMSG36
CMSG37
CMSG38
CMSG39
CMSG40
CMSG41
CMSG42
CMSG43
CMSG44
CMSG45
CMSG46
CMSG47
CMSG48
CMSG49
CMSG50
CMSG51
CMSG52
CMSG53
CMSG54
CMSG55
CMSG56
CMSG57
CMSG58
CMSG59
CMSG60
CMSG61
CMSG62
CMSG63
CMSG64
CMSG65
CMSG66
CMSG67
CMSG68
CMSG69
CMSG70
CMSG71
CMSG72
CMSG73
CMSG74
CMSG75
CMSG76
CMSG77
CMSG78
CMSG79
32X96
48X80
64X64
80X48
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
HE80004 Series
Since there are 4 LCD driver configurations available for selection by mask option, the RAM map of
LCD drivers is listed below for all configurations. Any unused RAM as marked with ‘*’ sign can be
used as general purposed RAM by application programs
8.1. 16 Gray Scale LCD Display RAM Map
Page
1
Cnf
Loc.
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
32x96
F
June 30, 2003
48x80
0
F
S31 ~ S00
S63 ~ S32
S95 ~ S64
64x64
0
F
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
*
S79 ~ S64
80x48
0
F
0
S31 ~ S00
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
12
*
COM0
COM1
COM2
COM3
S47 ~ S32
*
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Page
2
3
4
5
Cnf
Loc.
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
32x96
F
June 30, 2003
48x80
0
F
64x64
0
F
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
80x48
0
*
HE80004 Series
F
0
*
S31 ~ S00
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
13
*
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
S47 ~ S32
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Page
6
7
8
Cnf
Loc.
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
32x96
F
June 30, 2003
48x80
0
S95 ~ S64
F
64x64
0
*
F
S79 ~ S64
HE80004 Series
80x48
0
F
0
*
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
14
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Page
9
10
11
12
Cnf
Loc.
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
32x96
F
June 30, 2003
48x80
0
F
S63 ~ S32
S95 ~ S64
64x64
0
F
S63 ~ S32
S79 ~ S64
F
0
*
S47 ~ S32
*
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
80x48
0
S63 ~ S32
HE80004 Series
*
S79 ~ S64
S31 ~ S00
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
*
S79 ~ S64
S47 ~ S32
*
*
S95 ~ S64
*
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
*
S79 ~ S64
*
15
COM33
COM34
S31 ~ S00
*
S31 ~ S00
S63 ~ S32
COM32
*
S47 ~ S32
*
*
*
*
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Page
13
14
15
Cnf
Loc.
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
32x96
F
June 30, 2003
48x80
0
F
S31 ~ S00
S63 ~ S32
S95 ~ S64
64x64
0
F
S31 ~ S00
S63 ~ S32
S63 ~ S32
*
S79 ~ S64
80x48
0
S31 ~ S00
HE80004 Series
F
0
S31 ~ S00
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
*
S79 ~ S64
S47 ~ S32
*
*
S95 ~ S64
*
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
*
S79 ~ S64
S47 ~ S32
*
*
S95 ~ S64
*
*
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
*
S79 ~ S64
*
16
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
S31 ~ S00
*
S31 ~ S00
S95 ~ S64
COM46
S31 ~ S00
*
S31 ~ S00
S63 ~ S32
COM45
*
COM57
COM58
S47 ~ S32
*
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Page
16
17
18
19
Cnf
Loc.
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
32x96
F
June 30, 2003
48x80
0
F
64x64
0
F
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
80x48
0
*
HE80004 Series
F
0
*
S31 ~ S00
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
17
*
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
S47 ~ S32
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Page
20
Cnf
Loc.
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
32x96
F
48x80
0
F
S95 ~ S64
64x64
0
*
F
S79 ~ S64
HE80004 Series
80x48
0
F
0
*
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
S47 ~ S32
*
*
*
*
*
S31 ~ S00
S31 ~ S00
S31 ~ S00
S31 ~ S00
S63 ~ S32
S63 ~ S32
S63 ~ S32
S95 ~ S64
*
S79 ~ S64
*
*
*
S47 ~ S32
*
*
*
*
COM73
COM74
COM75
COM76
COM77
COM78
COM79
8.2. 4 Gray Scale LCD Display RAM Map
Page
1
2
Cnf
Loc.
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
32x96
F
June 30, 2003
48x80
0
S63 ~ S00
F
S95 ~ S64
*
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
*
S95 ~ S64
*
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
*
S95 ~ S64
*
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
*
F
*
0
S47 ~ S00
S80 ~
S64
*
S63 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S80 ~
S64
*
*
S63 ~ S00
*
*
S47 ~ S00
S80 ~
S64
*
S63 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S80 ~
S64
*
*
S63 ~ S00
*
80x48
0
S63 ~ S00
S63 ~ S00
*
*
F
S63 ~ S00
*
*
64x64
0
S63 ~ S00
*
*
S47 ~ S00
S80 ~
S64
*
S63 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S80 ~
S64
*
*
S63 ~ S00
S63 ~ S00
18
*
*
S47 ~ S00
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Page
3
4
5
Cnf
Loc.
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
32x96
F
June 30, 2003
48x80
0
*
S95 ~ S64
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
F
*
*
*
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
S63 ~ S00
S63 ~ S00
*
*
S95 ~ S64
*
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S95 ~ S64
*
*
S63 ~ S00
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S95 ~ S64
*
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
S95 ~ S64
*
S63 ~ S00
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S95 ~ S64
*
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
S95 ~ S64
*
S63 ~ S00
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S95 ~ S64
*
S63 ~ S00
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
*
S95 ~ S64
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S80 ~
S64
*
*
S63 ~ S00
*
*
S47 ~ S00
S80 ~
S64
*
S63 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S80 ~
S64
*
*
S63 ~ S00
S80 ~
S64
*
*
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S47 ~ S00
*
*
S47 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S47 ~ S00
*
*
S47 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S47 ~ S00
*
*
S47 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S47 ~ S00
*
*
S47 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S47 ~ S00
*
*
S47 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
19
S47 ~ S00
*
*
S47 ~ S00
*
*
S47 ~ S00
*
*
*
S80 ~
S64
S47 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S80 ~
S64
S63 ~ S00
*
*
*
S63 ~ S00
*
*
S63 ~ S00
0
*
S80 ~
S64
S63 ~ S00
*
F
*
S63 ~ S00
*
*
S63 ~ S00
S80 ~
S64
S63 ~ S00
*
80x48
0
*
S63 ~ S00
*
*
S80 ~
S64
S63 ~ S00
S95 ~ S64
S95 ~ S64
F
S63 ~ S00
*
*
64x64
0
HE80004 Series
S47 ~ S00
*
*
S47 ~ S00
*
*
S47 ~ S00
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Page
6
7
8
9
Cnf
Loc.
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
32x96
F
June 30, 2003
48x80
0
*
S95 ~ S64
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
F
*
*
*
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
S63 ~ S00
S63 ~ S00
*
*
S95 ~ S64
*
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S95 ~ S64
*
*
S63 ~ S00
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S95 ~ S64
*
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
S95 ~ S64
*
S63 ~ S00
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S95 ~ S64
*
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
S95 ~ S64
*
S63 ~ S00
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S95 ~ S64
*
S63 ~ S00
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
*
S95 ~ S64
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S80 ~
S64
*
*
S63 ~ S00
*
*
S47 ~ S00
S80 ~
S64
*
S63 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S80 ~
S64
*
*
S63 ~ S00
S80 ~
S64
*
*
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S47 ~ S00
*
*
S47 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S47 ~ S00
*
*
S47 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S47 ~ S00
*
*
S47 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S47 ~ S00
*
*
S47 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
S47 ~ S00
*
*
S47 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
20
S47 ~ S00
*
*
S47 ~ S00
*
*
S47 ~ S00
*
*
*
S80 ~
S64
S47 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S80 ~
S64
S63 ~ S00
*
*
*
S63 ~ S00
*
*
S63 ~ S00
0
*
S80 ~
S64
S63 ~ S00
*
F
*
S63 ~ S00
*
*
S63 ~ S00
S80 ~
S64
S63 ~ S00
*
80x48
0
*
S63 ~ S00
*
*
S80 ~
S64
S63 ~ S00
S95 ~ S64
S95 ~ S64
F
S63 ~ S00
*
*
64x64
0
HE80004 Series
S47 ~ S00
*
*
S47 ~ S00
*
*
S47 ~ S00
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Page
A
Cnf
Loc.
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
32x96
F
48x80
0
*
0
S95 ~ S64
S63 ~ S00
*
*
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
S95 ~ S64
*
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
S63 ~ S00
*
*
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
S63 ~ S00
*
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
*
S63 ~ S00
*
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
S63 ~ S00
S95 ~ S64
S63 ~ S00
*
S63 ~ S00
*
S95 ~ S64
*
S63 ~ S00
S63 ~ S00
*
COM69
S47 ~ S00
*
S63 ~ S00
*
*
S80 ~
S64
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
COM70
*
*
COM71
COM72
*
S63 ~ S00
*
S47 ~ S00
*
COM73
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
*
S47 ~ S00
*
*
S47 ~ S00
COM74
COM75
*
S63 ~ S00
*
S47 ~ S00
*
COM76
*
S63 ~ S00
S80 ~
S64
*
S63 ~ S00
S80 ~
S64
*
*
S47 ~ S00
*
*
S47 ~ S00
COM77
COM78
*
S63 ~ S00
S80 ~
S64
*
COM68
*
S80 ~
S64
S63 ~ S00
S95 ~ S64
COM67
*
*
S80 ~
S64
*
*
*
S63 ~ S00
*
S63 ~ S00
S95 ~ S64
S47 ~ S00
S80 ~
S64
S80 ~
S64
*
*
*
S63 ~ S00
S95 ~ S64
COM66
*
S63 ~ S00
S80 ~
S64
*
S47 ~ S00
S80 ~
S64
S63 ~ S00
*
*
*
S80 ~
S64
*
0
*
S63 ~ S00
S63 ~ S00
S95 ~ S64
F
*
S80 ~
S64
*
80x48
0
S63 ~ S00
S95 ~ S64
*
*
F
S80 ~
S64
*
S63 ~ S00
*
64x64
F
HE80004 Series
*
S47 ~ S00
*
COM79
*
8.3. Black and White LCD Display RAM Map
Page
1
2
Cnf
Loc.
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
32x96
F
48x80
0
*
S63 ~ S00
*
F
64x64
0
S63 ~ S00
S63 ~ S00
*
*
*
S63 ~ S00
*
S63 ~ S00
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
F
80x48
0
F
0
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
*
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
*
*
June 30, 2003
21
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Page
3
4
5
Cnf
Loc.
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
32x96
F
48x80
0
F
64x64
0
F
HE80004 Series
80x48
0
F
0
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
*
S63 ~ S00
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
*
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
June 30, 2003
*
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
*
S63 ~ S00
*
S47 ~ S00
*
*
S63 ~ S00
*
S47 ~ S00
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S63 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
*
22
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
Page
Cnf
Loc.
B0
C0
D0
E0
F0
32x96
F
June 30, 2003
48x80
0
F
64x64
0
F
23
HE80004 Series
80x48
0
F
0
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
*
S47 ~ S00
COM75
COM76
COM77
COM78
COM79
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE80004 Series
9. LCD Power Supply
The built-in LCD power supply is equipped with input voltage regulator, voltage multiplier and bias
voltage generating circuit with active buffer instead of passive resistor voltage dividing network. The
input voltage is regulated to LVREG using the internally generated LVAG as reference voltage. LVREG
can be adjusted by resistor between LGS1 and LVREG.
LVREG adjustment guideline: First, the level of VDD must be 0.3 volt higher than LVREG even at the
end of battery life for the regulator to function properly. For example, if the VDD is expected to drop to
2.2 volts when battery is low, then the level of LVREG can only be set at 1.9 volts max. Secondly, the
higher the level of LVREG, the less multiples it requires pumping LVP to same level. For example, to
pump the 2.25 volts to 9 volts requires 4 times multiplier; to pump the 3 volts to 9 volts requires only 3
time multiplier which consumes less power. So it is advisable not to adjust the LVREG to an unnecessary
low level.
Voltage multiplication: The LVREG is then multiplied by 3, 4, or 5 times, depending on external
capacitors configurations as shown below, to generate LVP. Please note that LVP must be lower than 9
volts to prevent chip from breaking down.
x3 multiplier
x4 multiplier
x5 multiplier
4.7uF
LVL1
4.7uF
LVL1
4.7uF
LVL1
0.1uF
LVL2
0.1uF
LVL2
0.1uF
LVL2
0.1uF
LVL3
0.1uF
LVL3
0.1uF
LVL3
4.7uF
LVL4
4.7uF
LVL4
4.7uF
LVL4
4.7uF
LVL5
4.7uF
LVL5
4.7uF
LVL5
LGS2
4.7uF
R
LVP
LGS2
R
4.7uF
LCAP4A
LCAP2B
LGS2
LVP
4.7uF
LCAP4A
0.1uF
R
LVP
LCAP4A
LCAP2B
LCAP2B
0.1uF
LCAP2A
0.1uF
LCAP2A
0.1uF
LCAP2A
0.1uF
LCAP1A
0.1uF
LCAP1A
0.1uF
LCAP1A
LCAP1B
0.1uF
LCAP1B
LCAP3A
0.1uF
LCAP3A
0.1uF
LCAP3A
LVREG
0.1uF
LVREG
0.1uF
LVREG
LGS1
0.1uF
R
LCAP1B
LVAG
LGS1
R
0.1uF
LVAG
LGS1
0.1uF
R
LVAG
The LVP is then regulated to generated LVL1 ~ LVL5. LVL5 can be adjusted by the resistor between
LGS2 and LV5. Be sure to leave at least 0.3 volt between LVP and LV5 for the regulator circuit to
function properly. The formula is:
LVL5 = (1 + R2/80K) x 0.9V
Different duties require different bias settings. There is some theoretical correspondence between the
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HE80004 Series
Duty and Bias Setting. However, it is better to use it as starting point and adjust it with real LCD panel
connected to it to determine the final setting. The theoretic relationship between the duty and bias setting
as following:
Duty Cycle Normal Bias Alternative Bias
32 duty
1/7
1/7.5
48 duty
1/8
1/7.5, 1/8.5
64 duty
1/9
1/8.5, 1/9.5
80 duty
1/10
1/9.5, 1/10.5
The bias setting is made by mask option MO_LBSR[2..0].
MO_LBSR[2..0]
000
001
010
011
100
101
110
111
Bias Setting
1/7
1/7.5
1/8
1/8.5
1/9
1/9.5
1/10
1/5
10. LCDC Control register
LCD Control Register LCDC controls the functions of LCD driver.
LCDC
Field
Mode
Reset
bit 7
-
Field
Value
0
1
000
CLR_GP
GRAY
.
.
.
111
0
BLANK
LCDE
1
0
1
bit 6
-
bit 5
CLR_GP
W
1
bit 4
bit 3
GRAY
W
xxx
bit 2
bit 1
BLANK
W
1
bit 0
LCDE
W
0
Function
Reset GRAY palette register pointer by write ‘0’ to CLR_GP bit.
No effect on GRAY palette register pointer.
LCD is darkest.
LCD display contrast adjustment.
LCD is lightest.
normal display.
LCD display blanked. The COM signals of LCD driver output inactive levels
(LVL4 and LVL1) while SEG signals output normal display patterns.
LCD driver disabled, LCD driver has no output signal and LVL1 ~ LR4 is pulled
up to LV3
LCD driver Enabled.
Please note that LCD driver must be turned off before the system goes into "sleep" mode. That means
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HE84G761
HE80004 Series
user must clear the bit 0 of LCDC to turn off LCD driving circuit before setting bit6 of OP1 to enter sleep
mode. Large current might happen if the procedure is not followed.
Please note that LCD driver uses slow clock as clock source. The LCD display will not display normally
if it works in Fast clock only mode because the LCD refresh action is too fast.
11. Oscillators
The MCU is equipped with two clock sources with a variety of selections on the types of oscillators to
choose from. The system designer can select oscillator types based on the cost target, timing accuracy
requirements etc. Crystal, Resonator or the RC oscillator can be used as fast clock source, components
should be placed as close to the pins as possible. The type of oscillator used is selected by mask option
MO_FXTAL.
MO_FXTAL
Fast clock type
0
RC Oscillator.
1
Crystal Oscillator.
FXI
FXI
FXO
FXO
Crystal Osc.
RC Osc.
The RC oscillator has a built-in capacitor. An external resistor is needed to connect from FXI to GND to
determine the oscillation frequency. The capacitance of internal RC oscillator is selected by mask option
MO_RCAP[2..0].
MO_RCAP[2:0]
000
001
010
011
100
101
110
111
Internal RC Cap. (pF)
2
4
7
14
20
40
50
60
The following table shows the combinations of R and C, and the resulting frequency. Please note that
oscillation frequency in the table only represents oscillation frequencies of certain samples. The actual
oscillation frequency may vary up to ±15% from lot to lot due to process parameter variations. User must
take this into consideration when using this chip in applications.
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HE84G761
HE80004 Series
Ring Oscillator Frequency Table
C (pF)
R (KΩ)
30.20
19.92
9.98
40
20
14
7
4
0.8
1.2
2.3
1.5
2.2
4.0
2.0
2.8
5.1
3.0
4.4
7.5
4.0
5.6
9.4
2
5.0 MHz
7.0 MHz
11.4 MHz
Two types of oscillator, crystal and RC, can be used as slow clock selectable by mask option
MO_SXTAL. If used time keeping function or other applications that required the accurate timing, crystal
oscillator is recommended. If the timing accuracy is not important, then RC type oscillator can be used to
reduce cost.
MO_SXTAL
Slow clock type
0
R/C oscillator
1
Crystal oscillator
SXI
SXI
SXO
SXO
Crystal Osc.
RC Osc.
With two clock sources available, the system can switch among operation modes of Normal, Slow, Idle,
and Sleep modes by the setting of OP1 and OP2 registers as shown in tables below to suit the needs of
application such as high speed or low power, etc.
OP1
Field
Mode
Reset
Bit 7
DRDY
R/W
1
Bit 6
STOP
R/W
0
Bit 5
SLOW
R/W
0
Bit 4
INTE
R/W
0
Bit 3
T2E
R/W
0
Bit 2
T1E
R/W
0
Bit 1
Z
R/W
-
Bit 0
C
R/W
-
OP2
Field
Mode
Reset
Bit 7
IDLE
R/W
0
Bit 6
PNWK
R
-
Bit 5
TCWK
R
-
Bit 4
TBE
R/W
0
Bit 3
Bit 2
Bit 1
TBS[3..0]
W
W
-
Bit 0
W
-
W
-
If the dual clock mode is used, the LCD display, Timer1 and Timer Base will derive its clock source from
slow clock while the other blocks will operate with the fast clock.
12. General Purpose I/O
There are three dedicated general purpose I/O port, PRTC, PRTD and PRT10, while PRT15[1..0] and
PRT17 are multiplexed with LCD segment driver pins. All the I/O Ports are bi-directional and of nonJune 30, 2003
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tri-state output structure. The output has weak sourcing (50 µA) and stronger sinking (1 mA) capability
and each can be configured as push-pull or open-drain output structure individually by mask option.
When the I/O port is used as input, the weakly high sourcing can be used as weakly pull-up. Open drain
can be used if the pull-up is not required and let the external driver to drive the pin. Please note that a
floating pad could cause more power consumption since the noise could interfere with the circuit and
cause the input to toggle. A ‘1’ needs to be written to port first before reading the input data from the I/O
pin. If the PMOS is used as pull-up, care should be taken to avoid the constant power drain by DC path
between pull-up and external circuit.
The input port has built-in Schmidt trigger to prevent it from chattering. The hysteresis level of Schmidt
trigger is 1/3 VDD.
VDD
DOUT
VDD
Q
LATCH
Q'
MO_?PP
PAD
DIN
SCHMIDT Trigger input
As pads of PRT15 and PRT17 are shared with LCD segment driver, the function of the pad is determined
by mask options. Following table is the setting for MO_LIO?[...] and MO_?PP[...] and others related to
LCD display setting and pin assignment features.
MO_LIO?[…] MO_?PP[...]
I/O Port
LCD Pin
0
0
Open-drain output
-0
1
Push-pull output
-1
0
-xx
1
1
-LCD Display
--: Function not available.
xx: Displayable, but may have abnormal leakage current, do not use.
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13. Timer1
The Timer1 consists of two 8-bit write-only preload registers T1H and T1L and 16-bit down counter. If
Timer1 is enabled, the counter will decrement by one with each incoming clock pulse. Timer1 interrupt
will be generated when the counter underflows - counts down to FFFFH. And the counter will be
automatically reloaded with the value of T1H and T1L.
The clock source of Timer1 is derived from slow clock “SCK” at dual clock or slow clock only mode.
And it comes from the fast clock “FCK” at fast clock only mode.
Please note that the interrupt is generated when counter counts from 0000H to FFFFH. If the value of
T1H and T1L is N, and count down to FFFFH, the total count is N+1. The content of counter is zero
when system resets. Once it is enabled to count at this moment, interrupt will be generated immediately
and value of T1H and T1L will be loaded since it counts to FFFFH. So the T1H and T1L value should be
set before enabling Timer1.
T1H
The contents of
T1H and T1L are
almost loaded into
Timer1 immediately
when Timer1 is
enabled after reset.
T1L
Auto reload
when Timer1
is underflow
< Timer1 Counter >
Decreases 1
No
Count To
0xFFFFh
Yes
Timer1
Interrupt
Request
T1_INT
The Timer1 related control registers are list as below:
Register Address
Field
Bit position Mode
IER
0x02
TC1_IER
2
T1L
T1H
0x03
0x04
T1L[7:0]
T1H[7:0]
7~0
7~0
OP1
0x09
TC1E
2
June 30, 2003
Description
0: TC1 interrupt is disabled. (default)
R/W
1: TC1 interrupt is enabled.
W Low byte of TC1 pre-load value
W High byte of TC1 pre-load value
0: TC1 is disabled. (default)
R/W
1: TC1 is enabled.
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14. Timer2
Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock
“Fsys”/1.5. The system clock “Fsys” varies depending on the operation modes of the MCU.
The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If
Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will
be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded
with the value of T2H and T2L.
Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value
of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when
system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and
value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value
should be set before enabling Timer2.
The Timer2 related control registers are list as below:
Register Address
Field
Bit position Mode
IER
0x02
TC2_IER
1
T2L
T2H
0x05
0x06
T2L[7:0]
T2H[7:0]
7~0
7~0
OP1
0x09
TC2E
3
June 30, 2003
Description
0: TC2 interrupt is disabled. (default)
R/W
1: TC2 interrupt is enabled.
W Low byte of TC2 pre-load value
W High byte of TC2 pre-load value
0: TC2 is disabled. (default)
R/W
1: TC2 is enabled.
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T2H
The contents of
T2H and T2L are
almost loaded into
Timer2 immediately
when Timer2 is
enabled after reset.
T2L
HE84G761
HE80004 Series
Auto reload
when Timer2
is underflow
< Timer2 Counter >
Decreases 1
No
Count To
0xFFFFh
Timer2
Interrupt
Request
Yes
T2_INT
15. Time Base
The TB timer is used to generate time-out interrupt at fixed period. The time-out frequency of TB is
determined by dividing slow clock with a factor selected in OP2[3..0]. TBE (Time Base Enable) bit
controls enable or disable of the circuit.
OP2
Field
Mode
Reset
Bit 7
IDLE
R/W
0
Bit 6
PNWK
R
-
Bit 5
TCWK
R
-
Bit 4
TBE
R/W
0
Bit 3
R/W
-
Bit 2
Bit 1
TBS[3..0]
R/W
R/W
-
Bit 0
R/W
-
TBE
Function
0
Disable Time Base
1
Enable Time Base
For example, if the slow clock is 32768 Hz, then the interrupt frequency is as shown in following table.
TBS[3..0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
June 30, 2003
Interrupt Frequency
16.384 KHz
8.192 KHz
4.096 KHz
2.048 KHz
1.024 KHz
512 Hz
256 Hz
128 Hz
64 Hz
32 Hz
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TBS[3..0]
1010
1011
1100
1101
1110
1111
HE84G761
HE80004 Series
Interrupt Frequency
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
0.5 Hz
16. Watch Dog Timer
Watch Dog Timer (WDT) is designed to reset system automatically and prevents system dead lock caused
by abnormal hardware activities or program execution. The WDT needs to be enabled in Mask Option.
MO_WDTE
0
1
Function
WDT disable
WDT enable
Using the WDT function, the “CLRWDT” instruction needs to be executed in every possible program
path when the program runs normally in order to clears the WDT counter before it overflows, so that the
program can operate normally. When abnormal conditions happen to cause the MCU to divert from
normal path, the WDT counter will not be cleared and reset signal will be generated to reset the system.
The WDT clock source is the same as TC1 (Timer1 clock), and the WDT reset signal is generated when
the counter had counted 32768 clock. The WDT can function in Normal, Slow and Idle Mode. However,
WDT will not function during Sleep Mode (as the TC1 clock has stopped).
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HE80004 Series
17. Voice Output
There are 7 or 8 bits DAC/PWM voice output available for user. The 7 bits DAC/PWM output format and
configuration are the same as the previous IC of HE80000 series. The 8 bits DAC/PWM format and
configuration are new designed and controlled by the VOC and PWMC registers. The selection of 7/8 bits
DAC/PWM output is by mask option MO_8BVOC.
MO_8BVOC
0
1
Function
7-bit DAC/PWM output
8-bit DAC/PWM output
8-Bit DAC/PWM Output:
The Digital-to-Analog converter converts the 8-bit unsigned speech data which is written into PWMC
data register to proportional current output.
PWMC
Field
address
0x0E
Reset
--
bit 7
DA7
bit 6
DA6
bit 5
DA5
bit 4
DA4
bit 3
DA3
bit 2
DA2
bit 1
DA1
bit 0
DA0
There are two output paths for the DAC. Either VO or DAO can be selected as output port of DAC by
VOC register when it is enabled. The VO output is primarily intended for speech generation, although it
is not necessary so, while the DAO output path can be used in conjunction with built-in OP comparator to
function as an Analog-to-Digital Converter as required in applications such as speech recording, speech
recognition or sensor interfaces.
OPO
OP
+
-
PWMC[DATA]
DAC
OPIP
OPIN
1
DAO
0
VO
R
VOC[DAC]
VOC[OP]
The DAC is enabled by DAC bit of VOC register. When DAC is enabled, the DAC output path can be
selected to output to DAO or VO pin by OP bit of VOC register.
VOC
Field
Reset
address
0x13
June 30, 2003
Bit 7
-
Bit 6
Bit 5
Bit 4
PWM O/P driver
0
0
0
33
Bit 3
PWME
0
Bit 2
PWM
0
Bit 1
DAC
0
Bit 0
OP
0
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Bit
Name
Value
1
VOC[3] PWME
0
1
VOC[2] PWM
0
1
VOC[1] DAC
0
1
VOC[0]
OP
0
HE84G761
HE80004 Series
Function description
PWM Output Driver Enable
PWM Output Driver Disable
PWM Module Enable
PWM Module Disable
Digital-to-Analog Converter Enable
Digital-to-Analog Converter Disable
DAC output to DAO pin
DAC output to VO pin
The pulse-width modulator (PWM) converts 8-bit unsigned speech data which is written into PWMC data
register to proportional duty cycle of PWM output. PWM module shares the same digital input register
PWMC with Digit-to-Analog Converter. So PWM and DA output can exist at the same time. When PWM
circuit is enabled, it generates signal with duty ratio in proportion to the value of PWMC register.
DA = 0x20
DA = 0x80
DA = 0xE0
1 subframe
PWMC
Field
VOC
address
0x0E
bit 7
DA7
bit 6
DA6
bit 5
DA5
bit 4
DA4
VOC
Field
Reset
address
0x13
Bit 7
-
Bit 6
Bit 5
Bit 4
PWM O/P driver
0
0
0
bit 3
DA3
bit 2
DA2
bit 1
DA1
bit 0
DA0
Bit 3
PWME
0
Bit 2
PWM
0
Bit 1
DAC
0
Bit 0
OP
0
The PWM bit of VOC controls the enable/disable of the PWM circuit and output driver. When PWM bit
of VOC is ‘0’, PWME bit and output drivers are both cleared. To use PWM as voice output, PWM bit has
to be set to ‘1’ first, then set PWME bit and enable output driver by setting the driver number. If PWM bit
is disabled and enabled again, the setting for driver and PWME bit will be clear.
The Fast Clock is gated through PWME bit of VOC register to provide the clock source of PWM circuit
when it is enabled. As PWM needs higher frequency to operate, it cannot generate correct PWM signal in
Slow clock only mode.
When the program enters into sleep mode or idle mode, it will automatically turn off all voice outputs by
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HE80004 Series
clearing VOC[6:0] to ”0000000”. To activate voice output again when returning to normal mode, the
VOC register needs to be set again.
The PWM output volume can be adjusted by command register VOC[6..4]. The bit 6 and 5 control 2
time driver, while bit 4 controls 1 time driver, thus it has 5 levels of driver output. By turning on/off the
internal drivers, the sound level of PWM output can be turned up and down. Please note that this
adjustment apply only to PWM, but not DA output.
PWM output driver selection
VOC[6..4]
Number of Driver
000
off
001
1
010
2
011
3
100
2
101
3
110
4
111
5
7-Bit DAC/PWM Output:
The 7-bit DAC/PWM voice generator is another scenario and the definitions of PWMC and VOC
registers are different from the 8-bit DAC/PWM format. These register are described as following.
The 7-bit voice output is controlled by PWMC and VOC register, and the PWMC is a command/data
register which is determined by PWMC[7] bit.
PWMC register
DA & PWM Data
Control
Bit 7
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
DA and PWM output value
PWM O/P driver
Reserved
Bit 1
Bit 0
PWME
When users write data into the PWMC register, the PWMC[7] bit will determines the data written into
PWM command register or 7-bit data register and the data register is also sent to the DA converter shown
as the below diagram. The definitions of “PWME” bit and “PWM O/P driver” bits are the same as VOC
register definition of 8-bit output mode.
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_____
reset
VOC[2]
PWMC[6..0]
Register.write.strobe
PWMC[7]
PWMC_REG[6..4]
PWM
command
register
CLK
PWMC_REG[3..1]
HE80004 Series
PWM
Driver
_____
reset
PWMC
_REG[0]
PWMP
PWMN
cp
Fast clock
PWMC[6..0]
7 bit data
register
PWM_O[6..0]
DAC
CLK
The fast clock is used to provide as PWM driver time base, and user shall set the PWMC[7]=’1’ and
VOC[2]=’1’ to enable the PWM output. When the system enters into sleep or idle mode, it will
automatically turn off the voice device by clearing VOC[2:0] to ”000”. In order to activate voice output
again when the system returns and enter into normal mode, the related bits of VOC register need to be set
again.
PWM
Data=0x40h
Data=0x10h
Data=0x70h
subframe
When the DAC is used as sound generator, the bias & filter circuit is used for bias voltage setting and
waveform filter regulation and the DAC is output to the VO (Voice Output) pin and please see application
notes for detailed calculation example and application. The driving capability of DAC is shown below.
VO/DAO
June 30, 2003
Condition
VDD=3V;VO=0~2V;Data=7Fh
36
Min.
2.5
Typ.
3
Max.
Unit
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HE84G761
HE80004 Series
VDD
CPU
VO(DAO)
bias &
filter
circuit
SPEAKER
The VOC is a three bit voice control register in the 7-bit mode.
VOC
address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Field
0x13
PWM
Reset
0
PWM: ‘1’ PWM output enabled; ‘0’ PWM output disabled.
DAC: ‘1’ DAC enabled; ‘0’ DAC disabled.
OP: ‘1’ DAC uses DAO pin as output pin; ‘0’ DAC uses VO pin as output pin.
Bit 1
DAC
0
Bit 0
OP
0
18. Low Voltage Detection/Reset
The low voltage detection is used to detect low battery or low power condition. There are 4 options on the
detection level selectable by mask option MO_DLVL. The low voltage detection circuit can be turned off
by clearing LVDE bit, and the status of supply power can be read out at bit LVDO of LVDC register
(extension register 0x17h).
MO_DLVL
00
01
10
11
Detection voltage
2.4 volts
2.6 volts
2.8 volts
3.0 volts
LVDC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Field LVDO
LVDE
Mode
R
W
Reset
0
LVDO: ‘0’ Æ Battery level low; ‘1’ Æ Battery level high
LVDE: ‘0’ Æ Disable voltage Detection; ‘1’ Æ Enable voltage Detection
Low voltage reset circuit prevents the CPU from operating below its physical limit. When the supply
voltage drops below VDET (2.2Volt), the CPU will be held in reset state until the supply voltage rises to
VRLS. Then CPU will be released from reset state. VRLS will be higher than VDET by 5% to provide
hysteresis and prevent CPU from bouncing back and forth between reset and operating state. The low
voltage reset function can be enabled or disabled by mask option MO_LVRE.
MO_LVRE
June 30, 2003
Function
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HE80004 Series
0
Disable LVR
1
Enable LVR
The voltage detection circuit is temperature compensated to prevent the detection voltage from drifting
with temperature variation.
Vrst
Vdet
VDD
Vrls
19. Infrared output
To achieve an IR output with programmable frequency and duty cycle, two 7-bit registers are employed
here. The IRH register represents the period (on FCK clock number) of output high, while IRL register
represents the period of output low. With this mechanism, the output IR frequency is equal to
FCK/(IRH+IRL), and the high duty cycle ratio is equal to IRH/(IRH+IRL). To make the IRO as output
pin alone, either IRH or IRL can be set as 0. When IRH is 0, the IRO output is a DC low. On the contrary,
if IRL is 0, the output is a DC high. Special care in hardware implementation is also taken according to
the MO_IRO (mask option to determine the default state of the IRO) to avoid glitch when PWM output is
disabled.
IRO
IRO
MUX
IR
generator
Compare
Counter+1
Fck
D Counter Q
CK
7-bit
R
IRO
IRL=0?
IRL
IRH=0?
1
0
MO_IRO
IRH
Toggle signal
reset
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HE84G761
HE80004 Series
To avoid unexpected IR output, users should firstly load the content of IRH and IRL before turn on IR by
set IROE bits to ‘1’.
The access of all the registers of IR is through the extension register. They are list as below:
Extension register
Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
0x15h IRL* IROE
IR PWM LOW DURATION
0x16h IRH
IR PWM HIGH DURATION
* IRL[7] is read/write, and IRL[6..0] is write only.
Bit0 Mode
R/W
W
Reset value
0xxx xxxx
-xxx xxxx
IROE: ‘0’ Æ IR is disabled (default); ‘1’ Æ IR is enabled.
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20.
HE84G761
HE80004 Series
Universal Asynchronous Receiver/Transmitter
The UART (Universal Asynchronous Receiver/Transmitter) interface provides serial communication
capabilities with other devices such as PC. Features include:
9
9
9
9
9
9
9
9
9
Full duplex Asynchronous communication
Programmable transmission rate with internal baud rate generator with selectable bit rates
Double buffered Transmitter and Receiver.
Programmable Data length (from 5 to 8 bits)
Programmable stop bits (1, 1.5 or 2-stop bit) generation and detection
Programmable parity type (odd, even or no parity)
Error (parity, overrun and framing errors) detection
Fully prioritized interrupt system control
Line break generation and detection.
Example – 8-bit UART Frame Format: (1 Start Bit, 8 Data Bits, 1 Parity Bit, 1 Stop Bit)
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Trans Hoding Reg
HE80004 Series
Trans Shift Reg
SOUT
TRANSMIT
MACHINE
Data
Bus
Buffer
EX_PT[7:0]
“Transmitter
control signal"
TRANSMITTER
TIMING
AND
CONTROL
Line Control Reg
“Transmitter
status"
Div Latch (MS)
ADS_N
BAUD-RATE
GENERATOR
XRD_N
Div Latch (LS)
XWR_N
BrgClk
MCLK
MCU
I/F
CTRL
LOGIC
“Receive status"
Line Status Reg
RECEIVE
TIMING
AND
CONTROL
“Receiver
control signal"
Rec Buffer Reg
RESET
RECEIVE
MACHINE
Interrupt Id Reg
Interrupt
Arbitrator
Interrupt En Reg
INTR
Rec Shift Reg
SIN
20.1. Interface Registers
Addressable extension register used to interface with MCU
Address
00H
01H
02H
03H
04H
05H
06H
Name
RBR
THR
IEIR
LCR
BRL
BRH
LSR
0
BRGE
0
Function
UART RECEIVER BUFFER
UART TRANSMITTER HOLDING REGISTER
RLSI
THRI
RBRI
0
ID2
ID1
SB
SP
EPS
PEN
STB
WLS1
UART LSB of Baud Rate Register
UART MSB of Baud Rate Register
TEMT
THRE
BI
FE
PE
OE
ID0
WLS0
DR
Mode
R
R/W
R/W
R/W
R/W
R/W
R
RESET
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0110 0000
IEIR: Interrupt enable/disable identification register.
LCR: Line control register.
LSR: Line status register.
20.2.Baud Rate Configuration Register
The BRH and BRL registers hold the upper and lower bytes of 16 bit baud rate divisor and which are
readable/writable. The baud rate of UART is calculated as following:
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BAUD _ RATE _ DIVISOR =
HE84G761
HE80004 Series
FCK
, (FCK: fast clock of system)
16 * BAUD _ RATE
The contents of BRH and BRL are calculated by the following two formulas:
BRL = BAUD _ RATE _ DIVISOR % 256
BRH = ( BAUD _ RATE _ DIVISOR – BRL) / 256
The “%” symbol is the modulus operation (reminder of division). For example, if the FCK is 1.8432M Hz
and the desired baud rate is 2400 baud, then
BAUD _ RATE _ DIVISOR =
1843200
= 48
16 * 2400
The BRL register shall be set to 0x30 and BRH set to 0x00. The setting of baud_rate_divisor is not
updated until the BRH register is written. Thus user is strongly recommended to write BRL first, then
BRH.
In order to obtain good communication quality, the same time base shall be used in the both sides of
transmitting and receiving. The following table shows the most common baud rate setting used in the PC
UART communication.
BRL and BRH: Baud Rate Control Registers
FCK(Hz) Baud Rate (bps) Divisor
BRL
1.8432M
50
2304
0x00
1.8432M
300
384
0x80
1.8432M
1200
96
0x60
1.8432M
2400
48
0x30
1.8432M
4800
24
0x18
1.8432M
9600
12
0x0C
1.8432M
19200
6
0x06
1.8432M
38400
3
0x03
1.8432M
57600
2
0x02
1.8432M
115200
1
0x01
BRH
0x09
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
20.3. Interrupt & Identification Register
This high nibble of IEIR register allows to enable/disable interrupt generation by the UART, the low
nibble ID[2..0] of IEIR register is used to identify the source of interrupts.
Address
0x02h
Bit 7 Bit 6 Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Value
0
RLSI THRI RBRI
0
ID2
ID1
ID0
“0000_0000”
R/W
R/W
R/W
R
R
R
RBRI: Receiver Buffer Register Interrupt (1 = Enable, 0 = Disable), related to ID[1] bit.
THRI: Transmitter Hold Register Interrupt (1 = Enable, 0 = Disable), related to ID[0] bit.
RLSI: Receiver Line Status Interrupt (1 = Enable, 0 = Disable), related to ID[2] bit.
June 30, 2003
Name
IEIR
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HE84G761
HE80004 Series
The following table shows the related interrupt sources, user can read the ID[2:0] to retrieve what is the
current highest priority of pending interrupts. The ID[2:0] bits will be cleared when user read the related
registers. For example, when an interrupt happened and the content of ID[2:0] is “101”, this means that
LRS error and THR empty happen; user can read the LSR register to clear the ID[2] bit and ID[0] bit can
also be cleared by reading the IEIR or writing data into THR register.
Level
None
Highest
Second
IEIR Bit [2:0]
Source of Interrupt
000
None
100
LSR error flags (OE/PE/FE/BI)
010
LSR receiver data ready flag (DR)
Third
001
LSR flag THR Empty (THRE)
Interrupt Reset Control
None
Reading LSR register to clear ID[2]
Reading RBR register to clear ID[1]
Reading IEIR register or Writing
THR register to clear ID[0]
20.4.Line Control Register
The line control register allows user to configure the asynchronous data transfer format and set the UART
function. Reading from the register is allowed to check the current settings of the communication.
Bit 7
BRGE
Bit 6
SB
Bit 5
SP
Bit 4
EPS
Bit 3
PEN
Bit 2
STB
Bit 1
WLS1
Bit 0
WLS0
Name
Description
Word Length Select
“00”: word length = 5
“00”: word length = 6
WLS[1..0]
“00”: word length = 7
“00”: word length = 8
Stop Bit Length
‘0’: Stop bit length = 1
STB
‘1’: Stop bit length = 1.5 when WLS[1..0]=”00”, else Stop bit length = 2
Parity Selection
“xx0”: No Parity
“001”: odd Parity
[SP, EPS, PEN]
“011”: even Parity
“101”: Stick Parity 1
“111”: Stick parity 0
Set Break
When enable the break control bit causes a break condition to be transmitted (SOUT is
forced to a logic 0 state). This condition exists until disabled by resetting this bit to
SB
logic 0.
‘0’: disable break; ‘1’: enable break
Baud Rate Generator
‘0’: disable baud rate clock generator
BRGE
‘1’: enable baud rate clock generator
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HE84G761
HE80004 Series
20.5.Line Status Register
Bit 7
0
Name
DR
OE
PE
FE
Bit 6
TEMT
Bit 5
THRE
Bit 4
BI
Bit 3
FE
Bit 2
PE
Bit 1
OE
Bit 0
DR
Description
Receiver Data Ready
DR indicates status of RBR. It will be set to logic 1 when RBR data is valid and will
be reset to logic 0 when RBR is empty. When line errors (OE/PE/FE/BI) happen, DR
will also be set to logic 1 and RBR will be updated to reflect the Data bits portion of
the frame.
Overrun Error
This bit will be set when the next character is transferred into RBR before the
previous RBR data is read by the CPU. Even though DR will still be 1 when OE is set
to logic 1, the previous frame data stored in RBR which is not read by the CPU is
trashed and can‘t be recovered.
Parity Error
This bit will be set to logic 1 only when the Parity is enabled and the Parity bit is not
at the logic state it should be. For Even Parity, the Parity bit should be 1 if an odd
number of 1s in the Data bits is received; otherwise, the Parity bit should be 0. For
Odd Parity, the Parity bit should be 1 if an even number of 1s in the Data bits is
received; otherwise, the Parity bit should be 0. For Stick Parity '1', the Parity bit
should be 1. For Stick Parity '0', the Parity bit should be 0.
Framing Error
FE will be reset to logic 0 whenever SIN is sampled high at the center of the first
Stop bit, regardless of how many Stop bits the UART is configured to.
Break Interrupt
BI will be set to logic 1 whenever SIN is low for longer than the whole frame (the
time of Start bit + Data bits + Parity bit + Stop bits), not at the SIN rising edge where
BI
Break is negated. If SIN is still low after BI is reset to logic 0 by reading LSR, BI will
not be set to logic 1 again. Since Break is also a Framing error, FE will also be set to
1 when BI is set.
THR Empty
THRE will be set to logic 1 whenever THR is empty which indicates that the
THRE
transmitter is ready to accept new data to transmit.
Both THR and TSR are Empty
This bit will be set to logic 1 when THRE is set to 1 and the last Data bit in the TSR
TEMT
is shifted out through SOUT.
* The four error flags (OE, PE, FE and BI) of LSR will be reset to logic 0 after a LSR read.
Since the SIN and SOUT of UART pins are shared with PRTD[1..0], users can use the mask option to
enable the UART function and select PRTD[1..0] function.
MO_UART
June 30, 2003
0
1
PRTD[1:0] = I/O Pin
PRTD[1:0] = UART Pin
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HE80004 Series
21. Extension Register Access
The extension registers can be accessed through the extension port control registers EXTAS and
EXTDA. User can read/write the extension register easily and the control timing is generated by
hardware automatically. The following code shows how to access the extension registers.
Read Extension Register:
LDA
#0x00h ; load #0x00h data to A Register
STA
EXTAS
; store A register data to the extension port address register.
LDA
EXTDA ; store the extension register (0x00h) data to A Register.
Write Extension Register:
LDA
#0x03h ; load #0x03h data to A Register
STA
EXTAS
; store A register data to the extension port address register.
LDA
#0x18h ; load #0x18h data to A Register
STA
EXTDA ; store A register data to the extension port data register.
22. Summary of Registers and Mask Options
All the registers and mask options used in this chip are listed in the following tables.
Address NAME
00H
TPL
01H
TPH
02H
IER
03H
T1L
04H
T1H
05H
T2L
06H
T2H
07H
SP
08H
DP
09H
DRDY
OP1
0AH
IDLE
OP2
0BH
PP
0CH
PRTC
0DH
PRTD
0EH
PWMC*
0FH
LCDC
10H
PRT10
11H
PRT11
12H
DTMF
13H
VOC*
14H
PRT14
15H
PRT15
16H
TPP
June 30, 2003
Field
Table pointer low byte
Table pointer high byte
INT_EX
TB
INT1
T1
T2
Timer 1 low byte
Timer 1 high byte
Timer 2 low byte
Timer 2 high byte
stack pointer
data RAM pointer
STOP
SLOW
INTE
T2E
T1E
Z
PNWK TCWK
TBE
TBS[3..0]
RAM page pointer
I/O port C
I/O port D
PWM data
CLR_GP
GRAY
BLANK
I/O port 10
Reserved
Reserved
PWM O/P driver
PWME
PWM
DAC
Reserved
I/O port 15
ROM table page pointer
45
INT2
C
LCDE
OP
Mode
R/W
R/W
R/W
W
W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R/W
R/W
R/W
W
R/W
R/W
R/W
RESET
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
1111 1111
xxxx xxxx
1000 00xx
0xx- ---0000 0000
1111 1111
1111 1111
0000 0000
xx1x xx10
1111 1111
xxxx xxxx
xxxx xxxx
x000 0000
xxxx xxxx
---- --11
0000 0000
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Address NAME
17H
PRT17
18~1FH
20H
EXTAS
21H
EXTDA
22~2AH
2BH GRAY16
GRAY0
GRAY1
GRAY2
GRAY3
GRAY4
GRAY5
GRAY6
GRAY7
GRAY8
GRAY9
GRAYA
GRAYB
GRAYC
GRAYD
GRAYE
GRAYF
2CH
PSA1
2DH
PSA2
2EH
PSA3
2FH
30H
AC
ACL
ACH
ACP
31H
EXMD
32H
EXMC
AC7
AC15
AC23
-
Field
I/O port 17
Reserved
Extension port address register
Extension port data register
Reserved
32 to 16 Gray Level Palette Register
Gray level 0 mapping register
Gray level 1 mapping register
Gray level 2 mapping register
Gray level 3 mapping register
Gray level 4 mapping register
Gray level 5 mapping register
Gray level 6 mapping register
Gray level 7 mapping register
Gray level 8 mapping register
Gray level 9 mapping register
Gray level A mapping register
Gray level B mapping register
Gray level C mapping register
Gray level D mapping register
Gray level E mapping register
Gray level F mapping register
Physical page address mapping register for logical page 1
Physical page address mapping register for logical page 2
Physical page address mapping register for logical page 3
Reserved
Download bus address counter
AC6
AC5
AC4
AC3
AC2
AC1
AC14
AC13
AC12
AC11
AC10
AC9
AC22
AC21
AC20
AC19
AC18
AC17
Download bus data port
WR
RD
HE84G761
HE80004 Series
Mode
R/W
R/W
R/W
R/W
R/W
w
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R/W
R/W
R/W
R/W
R/W
AC0
R/W
AC8
R/W
AC16 R/W
R/W
DNLD R/W
RESET
1111 1111
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx0 0000
xxx0 0010
xxx0 0100
xxx0 0110
xxx0 1000
xxx0 1010
xxx0 1100
xxx0 1110
xxx1 0000
xxx1 0010
xxx1 0100
xxx1 0110
xxx1 1000
xxx1 1010
xxx1 1100
xxx1 1110
0000 0001
0000 0010
0000 0011
xxxx xxxx
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx x011
* The definitions of PWMC and VOC are different for 7-bit and 8-bit voice output. Please refer to voice
output section for the detailed description.
Extension registers:
Address
00H
01H
02H
03H
04H
05H
06H
15H
16H
17H
Name
RBR
THR
IEIR
LCR
BRL
BRH
LSR
IRL
IRH
LVDC
0
BRGE
0
IROE
-
LVDO
Function
UART RECEIVER BUFFER
UART TRANSMITTER HOLDING REGISTER
RLSI
THRI
RBRI
0
ID2
ID1
SB
SP
EPS
PEN
STB
WLS1
UART LSB of Baud Rate Register
UART MSB of Baud Rate Register
TEMT
THRE
BI
FE
PE
OE
IR PWM LOW DURATION
IR PWM HIGH DURATION
-
Mode
R
R/W
ID0
R/W
WLS0 R/W
R/W
R/W
DR
R
R/W
W
LVDE R/W
RESET
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0110 0000
0xxx xxxx
-xxx xxxx
x--- ---0
Mask Options:
NAME
MO_LVRE
June 30, 2003
VALUE
0
1
NOTE
low voltage reset disable
low voltage reset enable
46
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NAME
MO_FXTAL
MO_SXTAL
MO_FCK/SCKN
MO_WDTE
MO_CPP[7:0]
MO_DPP[7:0]
MO_10PP[7:0]
MO_15PP[1:0]
MO_17PP[7:0]
MO_LIO15[1:0]
MO_LIO17[7:0]
MO_COM[1:0]
MO_LBSR[2:0]
MO_RCAP[2:0]
MO_8BVOC
MO_GRAY_MODE[1:0]
MO_EXMEM
MO_DLVL[1:0]
June 30, 2003
VALUE
0
1
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00
01
10
11
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
0
1
00
01
10
11
0
1
00
01
10
11
HE84G761
HE80004 Series
NOTE
R/C oscillator For fast clock
Crystal oscillator For fast clock
R/C oscillator For 32k clock
Crystal oscillator For 32k clock
slow clock only
illegal
dual clock
fast clock only
WDT disable
WDT enable
open-drain output
push-pull output
open-drain output
push-pull output
open-drain output
push-pull output
open-drain output
push-pull output
open-drain output
push-pull output
IO pin
LCD pin
IO pin
LCD pin
32x96
48x80
64x64
80x48
1/7 bias
1/7.5 bias
1/8 bias
1/8.5 bias
1/9 bias
1/9.5 bias
1/10 bias
1/5 bias
Ring-osc internal cap. Select C=2P
Ring-osc internal cap. Select C=4P
Ring-osc internal cap. Select C=7P
Ring-osc internal cap. Select C=14P
Ring-osc internal cap. Select C=20P
Ring-osc internal cap. Select C=40P
Ring-osc internal cap. Select C=50P
Ring-osc internal cap. Select C=60P
7-bit DAC/PWM output
8-bit DAC/PWM output
16 Gray Level
4 Gray Level
2 Level(B/W)
2 Level(B/W)
internal MEMORY
external MEMORY
LVD level voltage detect is 2.4V
LVD level voltage detect is 2.6V
LVD level voltage detect is 2.8V
LVD level voltage detect is 3.0V
47
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NAME
VALUE
0
1
00
01
10
11
0
1
MO_IRO
MO_PMODE[1:0]
MO_UART
HE80004 Series
NOTE
Default State of the IRO is ‘0’
Default State of the IRO is ‘1’
ROM map option 0
ROM map option 1
ROM map option 2
ROM map option 3
PRTD[1:0] = I/O Pin
PRTD[1:0] = UART Pin
23. Absolute Maximum Rating
Item
Symbol
Rating
Condition
Supply Voltage
VDD
-0.5V ~ 4.0V
Input Voltage
VIN
-0.5V ~ VDD+0.5V
Output Voltage
VO
-0.5V ~ VDD+0.5V
Operating Temperature
TOP
0°C ~ 70°C
Storage Temperature
TST
-50°C ~ 100°C
24. Recommended Operating Conditions
Item
Supply Voltage
Symbol
Rating
Condition
VDD
2.4V ~ 3.6V
VIH
0.9 VDD ~ VDD
Input Voltage
VIL
0.0V ~ 0.1VDD
8M Hz
VDD =3.0V
Operating Frequency
FMAX.
6M Hz
VDD =2.4V
°
°
Operating Temperature
TOP
0 C ~ 70 C
Storage Temperature
TST
-50°C ~ 100°C
25. AC/DC Characteristics
Testing Condition : TEMP=25℃, VDD=3V±10%
Parameters
Symbol
Power consumption
NORMAL Mode Current
SLOW Mode Current
IDLE Mode Current
Sleep Mode Current
IFAST
ISLOW
IIDLE
ISLEEP
Additional Current if LCD
ON
VIH
VIL
Input Hysteresis Width
VHYS
Typ.
Max.
Unit
Condition
1
15
10
1.5
25
20
1
220
275
330
mA
µA
µA
µA
2M external R/C fast clock
32768 Hz slow clock with LCD disabled
32768 Hz slow clock with LCD disabled
200
250
300
ILCD
I/O specification
Input High Voltage
Input Low Voltage
June 30, 2003
Min.
0.8
0.2
1/3
µA
VDD
VDD
VDD
48
LVP=3xLVREG
LVP=4xLVREG
LVP=5xLVREG
Input Pins
Input Pins
I/O, RSTP_N Threshold = 2/3 VDD
(Input from low to high), Threshold = 1/3
VDD (Input from high to low)
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Output Source Current
Output Sink Current
IOH
IOL1
50
1.0
µA
mA
Input Low Current
IIL1
20
µA
Input Low Current
IIL2
100
µA
14
8
5
mA
mA
mA
3
mA
2.2
2.31
Volts
Volts
PWM and DAC
PWM Output Current
IPWM
10
6
4
DAC Output Current
IoVO
2.5
Low voltage Reset
LVR detection voltage
LVR release voltage
VDET
VRLS
HE84G761
HE80004 Series
Output drive high*1, VOL=2.0V
Output drive low, VOL=0.4V
RSTP_N, VIL = GND, Pull high
Internally
I/O, VIL=GND, if pull high Internally by
user
PWM *2 With 32Ω Loading
With 64Ω Loading
With 100Ω Loading
VO, DAO@ VDD=3V,VO=0~2V,
Data =FF
Notes:
1. The “Output Source Current” specification is applicable only to the Push-Pull I/O type.
2. This Specification indicates only one PWM driving capability, and there are totally five built-in
drivers, user can multiply the actual number of driver to get the total amount of current. (IPWM x N;
N=0, 1, 2, 3, 4, 5)
June 30, 2003
49
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
June 30, 2003
41
42
43
44
45
46
47
48
49
50
SEG159
SEG158
SEG157
SEG156
SEG155
SEG154
SEG153
SEG152
SEG151
SEG150
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
SEG132
SEG133
SEG134
SEG135
SEG136
SEG137
SEG138
SEG139
SEG140
SEG141
79
78
77
76
75
74
71
73
72
70
69
68
67
66
65
64
63
62
61
60
59
2
1
4.7uF
0.1uF
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
VDD
0.1uF
1uF
22p
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
0.1uF
260K
0.1uF
4 MHz
22p
50
33p
VDD
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
1
2
3
4
5
6
7
8
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
10uF
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
32768Hz
0.1uF
KDGS80H
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
VO
RSTP_N
FXO
FXI
TSTP
SXO
SXI
VX
VDD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
PRTD7
PRTD6
PRTD5
PRTD4
PRTD3
0.1uF
+
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
58
57
56
55
54
53
52
51
IRO
PRTD2
PRTD1
PRTD0
PRTC7
PRTC6
PRTC5
PRTC4
REN
RWN
DCN
STBN
80
81
82
83
84
85
86
87
88
89
90
VDD 91
92
PWM 93
94
57
DAO
OPO
OPIP
OPIN
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
LVL1
LVL2
LVL3
LVL4
LVL5
LGS2
LVP
LCAP4A
LCAP2B
LCAP2A
LCAP1A
LCAP1B
LCAP3A
LVREG
LGS1
LVAG
LFR
CCK
PRTD[2]/WKUP[0]
PRTD[1]/SIN
PRTD[0]/SOUT
PRTC[7]
PRTC[6]
PRTC[5]
PRTC[4]
PRTC[3]
PRTC[2]
PRTC[1]
PRTC[0]
VDD_RAM
IRO
PWM
GND_PWM
VO
RSTP_N
FXO
FXI
TSTP_P
SXO
SXI
VX
VDD
PRT10[7]
PRT10[6]
PRT10[5]
PRT10[4]
PRT10[3]
PRT10[2]
PRT10[1]
PRT10[0]
PRTD[7]/INT2/WKUP[5]
PRTD[6]/INT1/WKUP[4]
PRTD[5]/WKUP[3]
PRTD[4]/WKUP[2]
PRTD[3]/WKUP[1]
DAO
LVL1
LVL2
LVL3
LVL4
LVL5
LGS2
LVP
LCAP4A
LCAP2B
LCAP2A
LCAP1A
LCAP1B
LCAP3A
LVREG
LGS1
LVAG
OLFR
OCCK
GND
OPO
OPIP
OPIN
PRT17[1]/SEG1
PRT17[0]/SEG0
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
GND
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RES_N
VDD
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
4.7uF
30
31
32
33
34
35
36
37
38
39
40
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
0.1uF
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RSTP_N
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
LVP
LVL5
LVL3
LVL2
LFR
CCK
REN
R_WN
D_CN
STBN
0.1uF
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
4.7uF
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
LVP
LVL5
LVL3
LVL2
LFR
CCK
REN
RWN
DCN
STBN
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
PRT170
PRT171
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
CMSG74
CMSG73
CMSG72
CMSG71
CMSG70
CMSG69
CMSG68
CMSG67
CMSG66
CMSG65
CMSG64
CMSG63
CMSG62
CMSG61
CMSG60
CMSG59
CMSG58
CMSG57
CMSG56
CMSG55
CMSG54
CMSG53
CMSG52
SEG27/A[11]
SEG28/A[12]
SEG29/A[13]
SEG30/A[14]
SEG31/A[15]
SEG32/A[16]
SEG33/A[17]
SEG34/A[18]
SEG35/A[19]
SEG36/A[20]
SEG37/A[21]
SEG38/A[22]
SEG39/A[23]
SEG40/D[0]
SEG41/D[1]
SEG42/D[2]
SEG43/D[3]
SEG44/D[4]
SEG45/D[5]
SEG46/D[6]
SEG47/D[7]
CMSG79
CMSG78
CMSG77
CMSG76
CMSG75
PRT17[2]/SEG2
PRT17[3]/SEG3
PRT17[4]/SEG4
PRT17[5]/SEG5
PRT17[6]/SEG6
PRT17[7]/SEG7
PRT15[0]/SEG8
PRT15[1]/SEG9
SEG10/CS3
SEG11/CS2
SEG12/CS1
SEG13/CS0
SEG14/WE
SEG15/OE
SEG16/A[0]
SEG17/A[1]
SEG18/A[2]
SEG19/A[3]
SEG20/A[4]
SEG21/A[5]
SEG22/A[6]
SEG23/A[7]
SEG24/A[8]
SEG25/A[9]
SEG26/A[10]
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
PRT150
PRT151
CS3
CS2
CS1
CS0
WE
OE
SEGA16
SEGA17
SEGA18
SEGA19
SEGA20
SEGA21
SEGA22
SEGA23
SEGA24
SEGA25
SEGA26
SEGA27
SEGA28
SEGA29
SEGA30
SEGA31
SEGA32
SEGA33
SEGA34
SEGA35
SEGA36
SEGA37
SEGA38
SEGA39
SEGD40
SEGD41
SEGD42
SEGD43
SEGD44
SEGD45
SEGD46
SEGD47
CMSG79
CMSG78
CMSG77
CMSG76
CMSG75
CMSG74
CMSG73
CMSG72
CMSG71
CMSG70
CMSG69
CMSG68
CMSG67
CMSG66
CMSG65
CMSG64
CMSG63
CMSG62
CMSG61
CMSG60
CMSG59
CMSG58
CMSG57
CMSG56
CMSG55
CMSG54
CMSG53
CMSG52
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE84G761
HE80004 Series
26. Application Circuit
HE84G761
115K
1uF
CMSG51
CMSG50
CMSG49
CMSG48
CMSG47
CMSG46
CMSG45
CMSG44
CMSG43
CMSG42
CMSG41
CMSG40
CMSG39
CMSG38
CMSG37
CMSG36
CMSG35
CMSG34
CMSG33
CMSG32
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
CMSG51
CMSG50
CMSG49
CMSG48
CMSG47
CMSG46
CMSG45
CMSG44
CMSG43
CMSG42
CMSG41
CMSG40
CMSG39
CMSG38
CMSG37
CMSG36
CMSG35
CMSG34
CMSG33
CMSG32
VDD
0
BUZZER
560K
VDD
VDD
RSTP_N
R
47uF
3.0V
33p
0.1uF
This application assumes 48COM X 80SEG configuration,
and 80 SEG Extender KDGS80.
SEG142
SEG143
SEG144
SEG145
SEG146
SEG147
SEG148
SEG149
2.7K~10K
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G761
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE80004 Series
Note: Options for LCD, Osc. and external memory
COMXSEG
CMSG32
CMSG33
CMSG34
CMSG35
CMSG36
CMSG37
CMSG38
CMSG39
CMSG40
CMSG41
CMSG42
CMSG43
CMSG44
CMSG45
CMSG46
CMSG47
CMSG48
CMSG49
CMSG50
CMSG51
CMSG52
CMSG53
CMSG54
CMSG55
CMSG56
CMSG57
CMSG58
CMSG59
CMSG60
CMSG61
CMSG62
CMSG63
CMSG64
CMSG65
CMSG66
CMSG67
CMSG68
CMSG69
CMSG70
CMSG71
CMSG72
CMSG73
CMSG74
CMSG75
CMSG76
CMSG77
CMSG78
CMSG79
OE
WE
CS0
CS1
CS2
CS3
PRT151
PRT150
PRT177
PRT176
PRT175
PRT174
PRT173
PRT172
PRT171
PRT170
32X96
48X80
64X64
80X48
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
Ext. Bus Interface
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
CS3
CS2
CS1
CS0
WE
OE
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
Q1
Q2
Q3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
x3 multiplier
FXO
Crystal Osc.
A10
CS0
Q7
Q6
Q5
Q4
Q3
A18
A7
A6
A5
A4
A3
A2
A1
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE
CE
A0
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A20
A9
A10
A11
A12
A13
A14
A15
A16
A17
512KB x 8 SRAM
A11
A9
A8
A13
WE
A17
A15
VDD
A0
Q7
Q6
Q5
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Q4
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
IO7
IO6
IO5
IO4
IO3
GND
IO2
IO1
IO0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS3
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
LP62S4096-TSOP
VDD
x4 multiplier
x5 multiplier
LVL1
4.7uF
LVL1
4.7uF
LVL1
0.1uF
LVL2
0.1uF
LVL2
0.1uF
LVL2
0.1uF
LVL3
0.1uF
LVL3
0.1uF
LVL3
4.7uF
LVL4
4.7uF
LVL4
4.7uF
LVL4
4.7uF
LVL5
4.7uF
LVL5
4.7uF
LVL5
4.7uF
R2
LGS2
4.7uF
R2
LGS2
LGS2
LVP
4.7uF
LCAP4A
LCAP4A
0.1uF
LCAP2B
LCAP2B
LVP
R2
LVP
LCAP4A
LCAP2B
0.1uF
LCAP2A
0.1uF
LCAP2A
0.1uF
LCAP2A
0.1uF
LCAP1A
0.1uF
LCAP1A
0.1uF
LCAP1A
LCAP1B
0.1uF
FXO
0.1uF
A17
4.7uF
SXO
FXI
C89
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
M27C160
0.1uF
FXI
A18
A17
A14
A13
A8
A9
A11
A17
GND
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCCQ
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE
GND
CE
A0
28F320-TSOP
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BY TE
VSS
Q15A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
SXI
RC Osc.
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Intel NOR FLASH
1
2 A16
3 A15
4 A14
5 A13
6 A12
7 A11
8 A9
9 A8
10 WE
11 RP
12 VPP
13 WP
14 A18
15 A7
16 A6
17 A5
18 A4
19 A3
20 A2
A1
16 MB EPROM
A19
A18
A8
A7
A6
A5
A4
A3
A2
A1
CS1
SXI
Crystal Osc.
VCC
A18
A17
A14
A13
A8
A9
A11
OE/VPP
A10
CE
Q7
Q6
Q5
Q4
Q3
M27C801
OE
WE
CS0
CS1
CS2
CS3
PRT151
PRT150
PRT177
PRT176
PRT175
PRT174
PRT173
PRT172
PRT171
PRT170
SXO
A16
A15
A14
A13
A12
A11
A9
A8
WE
VDD
8 MB EPROM
AVSS
R1
LCAP1B
LCAP1B
LCAP3A
0.1uF
LCAP3A
0.1uF
LCAP3A
LVREG
0.1uF
LVREG
0.1uF
LVREG
LGS1
0.1uF
LVAG
AVSS
R1
LGS1
LGS1
0.1uF
LVAG
R1
LVAG
AVSS
RC Osc.
June 30, 2003
51
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE84G761
HE80004 Series
27. Important Note
1.
2.
3.
4.
5.
6.
Please note the ICE is a superset of HE80000 series IC. Each member of the family only has parts of
all resources. Do not use any hardware resource that your target chip doesn’t have, for example,
RAM and register. KBIDS and compiler can’t prevent user from using some hardware resources that
don’t exist in your target chip.
To access “Data ROM”, users must update TPP first, TPH, and then TPL. Only follow this order, the
pre-charge circuit of ROM will work correctly. The 5µs waiting is also necessary before LDV
instruction is executed since Data ROM is a low speed ROM. User can’t emulate this accessing
process in ICE, so 5µs delay should be added by firmware.
LCD driving circuit must be turned off before the system goes into sleep mode.
Please bond the TSTP_P, RSTP_N and PRTD [7:0] with test points on PCB (can be soldered and
probed) as you can, then some testing can be performed on PCB when it’s necessary. The TSTP_P is
suggested to connect to ground by a 0 ohm resistor.
The LVP must be lower than 8.5 volts; otherwise permanent damages to the IC might be incurred.
Please refer to the application note “AN025E” for the detailed LCD power system adjustment.
28. Updated History
Version
V0.80
V0.90
V0.91
V0.92
V0.93
V1.0
V1.01
Date
Update History
04/29/03
05/05/03
05/06/03
05/13/03
Modify application circuit
Update mask options and register table
Max. 34 I/O
Add LDVC register to list
Add 7-bit DAC/PWM description
05/27/03 Combine DAC and PWM section together
Add the extension register access section
Add the application note “AN025E” reference for LCD power system.
06/30/03
Add a resistor to pull up the STBN pin of KDGS80.
June 30, 2003
52
V1.01
This specification is subject to change without notice. Please contact sales person for the latest version before use.

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