HN58X2408I/HN58X2416I HN58X2432I/HN58X2464I Two-wire serial interface 8k EEPROM (1-kword × 8-bit)/16k EEPROM (2-kword × 8-bit) 32k EEPROM (4-kword × 8-bit)/64k EEPROM(8-kword × 8-bit) ADE-203-1108C (Z) Rev. 3.0 Aug. 9, 2002 Description HN58X24xxI series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). The y re alize high spee d, low powe r consumption and a high leve l of re lia bility by employing adva nce d MNOS memory tec hnology and C MOS proc ess and low voltage cir cuitry tec hnology. The y also have a 32-byte page programming function to make their write operation faster. Note: Hitac hi’s ser ia l EEP RO M ar e author iz ed for using consume r applica tions such as ce llula r phone, ca mcorde rs, audio equipment. The ref ore, plea se conta ct Hitac hi’s sale s off ic e bef ore using industrial applications such as automotive systems, embedded controllers, and meters. Features • • • • • • • • Single supply: 1.8 V to 5.5 V Two-wire serial interface (I 2C TM serial bus*1) Clock frequency: 400 kHz Power dissipation: Standby: 3 µA(max) Active (Read): 1 mA(max) Active (Write): 3 mA(max) Automatic page write: 32-byte/page Write cycle time: 10 ms (2.7 V to 5.5 V)/15ms (1.8 V to 2.7 V) Endurance: 105 Cycles (Page write mode) Data retention: 10 Years HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I • Small size packages: TSSOP-8pin , SOP-8pin and SON-8pin (HN58X2416) • Shipping tape and reel TSSOP 8-pin: 3,000 IC/reel SOP 8-pin: 2,500 IC/reel SON 8-pin: 3,000 IC/reel • Temperature range: –40 to +85°C Note: 1. I2C is a trademark of Philips Corporation. Ordering Information Type No. Internal organization Operating voltage Frequency Package HN58X2408FPI 8k bit (1024 × 8-bit) HN58X2416FPI 16k bit (2048 × 8-bit) HN58X2432FPI 32k bit (4096 × 8-bit) HN58X2464FPI 64k bit (8192 × 8-bit) HN58X2408TI 8k bit (1024 × 8-bit) HN58X2416TI 16k bit (2048 × 8-bit) HN58X2432TI 32k bit (4096 × 8-bit) 1.8 V to 5.5 V 400 kHz 150 mil 8-pin plastic SOP (FP-8DB) 1.8 V to 5.5 V 400 kHz 8-pin plastic TSSOP (TTP-8DA) HN58X2464TI 64k bit (8192 × 8-bit) HN58X2416NIR 16k bit (2048 × 8-bit) 1.8 V to 5.5 V 400 kHz 8-pin plastic SON (TNP-8DA) Pin Arrangement 8-pin TSSOP 8-pin SOP 8-pin SON A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA (Top view) 2 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Pin Description Pin name Function A0 to A2 Device address SCL Serial clock input SDA Serial data input/output WP Write protect VCC Power supply VSS Ground Block Diagram High voltage generator Control logic A0, A1, A2 SCL X decoder WP Address generator VSS Memory array Y decoder VCC Y-serect & Sense amp. SDA Serial-parallel converter Absolute Maximum Ratings Parameter Symbol Value Supply voltage relative to VSS VCC –0.6 to +7.0 Vin 2 –0.5* to +7.0* V Topr –40 to +85 ˚C Tstg –65 to +125 ˚C Input voltage relative to VSS Operating temperature range* Storage temperature range 1 Unit V 3 Notes: 1. Including electrical characteristics and data retention. 2. Vin (min): –3.0 V for pulse width ≤ 50 ns. 3. Should not exceed VCC + 1.0 V. 3 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 1.8 — 5.5 V VSS 0 0 0 V VIH VCC × 0.7 — VCC + 1.0 V Input high voltage Input low voltage VIL –0.3* — VCC × 0.3 V Operating temperature Topr –40 — 85 ˚C Note: 1 1. VIL (min): –1.0 V for pulse width ≤ 50 ns. DC Characteristics (Ta = –40 to +85˚C, VCC = 1.8 V to 5.5 V) Parameter Symbol Min Typ Max Unit Test conditions Input leakage current I LI — — 2.0 µA VCC = 5.5 V, Vin = 0 to 5.5 V Output leakage current I LO — — 2.0 µA VCC = 5.5 V, Vout = 0 to 5.5 V Standby VCC current I SB — 1.0 3.0 µA Vin = VSS or VCC Read VCC current I CC1 — — 1.0 mA VCC = 5.5 V, Read at 400 kHz Write VCC current I CC2 — — 3.0 mA VCC = 5.5 V, Write at 400 kHz Output low voltage VOL2 — — 0.4 V VCC = 4.5 to 5.5 V, I OL = 1.6 mA VCC = 2.7 to 4.5 V, I OL = 0.8 mA VCC = 1.8 to 2.7 V, I OL = 0.4 mA VOL1 — — 0.2 V VCC = 1.8 to 2.7 V, I OL = 0.2 mA Capacitance (Ta = 25˚C, f = 1 MHz) Min Typ Max Unit Test conditions Input capacitance (A0 to A2, SCL, WP) Cin*1 — — 6.0 pF Vin = 0 V 1 — — 6.0 pF Vout = 0 V Parameter Output capacitance (SDA) Note: 4 Symbol CI/O * 1. This parameter is sampled and not 100% tested. HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I AC Characteristics (Ta = –40 to +85˚C, VCC = 1.8 to 5.5 V) Test Conditions • Input pules levels: VIL = 0.2 × VCC VIH = 0.8 × VCC • Input rise and fall time: ≤ 20 ns • Input and output timing reference levels: 0.5 × VCC • Output load: TTL Gate + 100 pF Parameter Symbol Min Typ Max Unit Clock frequency f SCL — — 400 kHz Clock pulse width low t LOW 1200 — — ns Clock pulse width high t HIGH 600 — — ns Noise suppression time tI — — 50 ns Access time t AA 100 — 900 ns Bus free time for next mode t BUF 1200 — — ns Start hold time t HD.STA 600 — — ns Start setup time t SU.STA 600 — — ns Data in hold time t HD.DAT 0 — — ns Data in setup time t SU.DAT 100 — — ns Input rise time tR — — 300 ns 1 Input fall time tF — — 300 ns 1 Stop setup time t SU.STO 600 — — ns Data out hold time t DH 50 — — ns VCC = 2.7 V to 5.5 V t WC — — 10 ms 2 VCC = 1.8 V to 2.7 V t WC — — 15 ms 2 Write cycle time Notes 1 Notes: 1. This parameter is sampled and not 100% tested. 2. t WC is the time from a stop condition to the end of internally controlled write cycle. 5 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Timing Waveforms Bus Timing tF tHIGH 1/fSCL tLOW tR SCL tSU.STA tHD.DAT tSU.DAT tHD.STA tSU.STO SDA (in) tBUF tAA tDH SDA (out) Write Cycle Timing Stop condition Start condition SCL SDA D0 in Write data (Address (n)) 6 ACK tWC (Internally controlled) HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Pin Function Serial Clock (SCL) The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into EEP RO M devic e and nega tive edge cloc k data out of ea ch devic e. Maximum cloc k ra te is 400 kHz. Serial Input/Output Data (SDA) The S DA pin is bidirec tiona l for ser ia l data tra nsf er . The S DA pin nee ds to be pulled up by re sistor as that pin is open-drain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed during SCL low period. Data Validity (SDA data change timing waveform) SCL SDA Data change Note: Data change High-to-low and low-to-high chang of SDA should be done during SCL low periods. 7 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Device Address (A0, A1, A2) Eight devic es ca n be wire d for one common data bus line as maximum. De vic e addr ess pins ar e used to distinguish ea ch devic e and devic e addr ess pins should be conne cte d to VCC or VSS . Whe n devic e addr ess code provide d fr om S DA pin matche s cor re sponding har d-wire d devic e addr ess pins A0 to A2, that one device can be activated. As for 8k to 16k EEPROM, whole or some device address pins don't need to be fixed since device address code provided from the SDA pin is used as memory address signal. Pin Connections for A0 to A2 Pin connection Max connect Memory size number A2 8k bit 2 VCC/V SS * ×* 16k bit 1 × 32k bit 8 64k bit 8 A1 A0 Notes × Use A0, A1 for memory address a8 and a9 × × Use A0, A1, A2 for memory address a8, a9 and a10 VCC/V SS VCC/V SS VCC/V SS VCC/V SS VCC/V SS VCC/V SS 1 2 Notes: 1. “VCC/V SS ” means that device address pin should be connected to VCC or VSS . 2. × = Don’t care (Open is also approval.) Write Protect (WP) When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following table. When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated irrespective of the WP pin status. WP should be fixed high or low during operations since WP does not provide a latch function. Write Protect Area Write protect area WP pin status 8k bit 16k bit 32k bit 64k bit VIH Upper 1/2 (4k bit) Upper 1/2 (8k bit) Upper 1/4 (8k bit) Upper 1/4 (16k bit) VIL Normal read/write operation 8 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation. (See start condition and stop condition) Stop Condition A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in a internally-timed write cycle to the memories. After the internally-timed write cycle which is specified as tWC , the device enters a standby mode. (See write cycle timing) Start Condition and Stop Condition SCL SDA (in) Start condition Stop condition 9 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to ac knowledge that it has re ce ive d ea ch wor d. This happe ns during ninth cloc k cyc le. The tra nsmitter kee ps bus open to re ce ive ac knowledgme nt fr om the re ce ive r at the ninth cloc k. In the wr ite oper ation, EEP RO M sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to ac knowledge af ter re ce iving the devic e addr ess wor d. Af te r sending re ad data , the EEP RO M wa its acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge, it sends read data of next addr ess. If the EEP RO M re ce ive s ac knowledgme nt "1" (no ac knowledgme nt) and a following stop condition, it stops the re ad oper ation and ente rs a stand-by mode. If the EEP RO M re ce ive s neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending read data. Acknowledge Timing Waveform SCL SDA IN SDA OUT 10 1 2 8 9 Acknowledge out HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Device Addressing The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish devic e type and this EEP RO M uses “1010” fixe d code . The devic e addr ess wor d is followe d by the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device out of all devices which ar e conne cte d to the bus. This mea ns that the devic e is sele cted if the inputte d 3-bit devic e addr ess code is equa l to the cor re sponding har d-wire d A2- A0 pin status. As for the 8kbit and 16kbit EEP RO Ms, whole or some bits of their device address code may be used as the memory address bits. For example, A0 and A1 ar e used as a8 and a9 for the 8kbit. The 16kbit doesn't use the devic e addr ess code inste ad all 3 bits ar e used as the memory addr ess bits a8, a9 and a10. The eighth bit of the devic e addr ess wor d is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read operation is initiated if this bit is high. Upon a compa re of the devic e addr ess wor d, the EEP RO M ente rs the re ad or wr ite oper ation af ter outputting the ze ro as an ac knowledge . The EEP RO M turns to a stand-by state if the devic e code is not “1010” or device address code doesn’t coincide with status of the correspond hard-wired device address pins A0 to A2. Device Address Word Device address word (8-bit) Device address code* 1 Device code (fixed) R/W code* 2 32k, 64k 1 0 1 0 A2 A1 A0 R/W 8k 1 0 1 0 A2 a9 a8 R/W 16k 1 0 1 0 a10 a9 a8 R/W Notes: 1. A2 to A0 are device address and a10 to a8 are memory address. 2. R/W=“1” is read and R/W = “0” is write. 11 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Write Operations Byte Write: A wr ite oper ation re quires an 8-bit devic e addr ess wor d with R /W = “0”. The n the EEP RO M sends ac knowledgme nt "0" at the ninth cloc k cyc le. Af te r these , the 8kbit to 16kbit EEP RO Ms re ce ive 8-bit memory address word, on the other hand the 32kbit and 64kbit EEPROMs receive 2 sequence 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit wr ite data . Af te r re ce ipt of wr ite data , the EEP RO M outputs ac knowledgme nt "0". If the EEP RO M re ce ive s a stop condition, the EEP RO M ente rs an interna lly- timed wr ite cyc le and ter mina te s re ce ipt of S CL, S DA inputs until completion of the wr ite cyc le. The EEP RO M re turns to a standby mode after completion of the write cycle. 1010 W Start 1010 W Stop 1st Memory address (n) 2nd Memory address (n) Write data (n) ACK R/W Notes: 1. Don‘t care bits for 32k and 64k. 2. Don‘t care bit for 32k. 12 ACK D7 D6 D5 D4 D3 D2 D1 D0 Device address ACK a7 a6 a5 a4 a3 a2 a1 a0 ACK R/W Start 32k to 64k Write data (n) *1 *1 *1 a12 *2 a11 a10 a9 a8 8k to 16k Memory address (n) D7 D6 D5 D4 D3 D2 D1 D0 Device address a7 a6 a5 a4 a3 a2 a1 a0 Byte Write Operation ACK ACK Stop HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Page Write: The EEPROM is capable of the page write operation which allows any number of bytes up to 32 bytes to be written in a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The page write is initiated by a start condition, device address word, memory address(n) and wr ite data (Dn) with eve ry ninth bit ac knowledgme nt. The EEP RO M ente rs the page wr ite oper ation if the EEPROM receives more write data(Dn+1) instead of receiving a stop condition. The a0 to a4 address bits are automatica lly incr emented upon re ce iving wr ite data (Dn+ 1). The EEP RO M ca n continue to re ce ive wr ite data up to 32 bytes. If the a0 to a4 addr ess bits re ac hes the last addr ess of the page , the a0 to a4 addr ess bits will roll over to the first addr ess of the same page and pre vious wr ite data will be over written. Upon receiving a stop condition, the EEPROM stops receiving write data and enters internally-timed write cycle. Device address 32k to 64k Start 1010 1st Memory address (n) W ACK R/W ACK D5 D4 D3 D2 D1 D0 Stop ACK ACK 2nd Memory address (n) Write data (n) ACK ACK Write data (n+m) D5 D4 D3 D2 D1 D0 ACK R/W Start Write data (n+m) D7 D6 D5 D4 D3 D2 D1 D0 W D7 D6 D5 D4 D3 D2 D1 D0 1010 Write data (n) *1 *1 *1 a12 *2 a11 a10 a9 a8 8k to 16k Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 Device address a7 a6 a5 a4 a3 a2 a1 a0 Page Write Operation ACK ACK Stop Notes: 1. Don‘t care bits for 32k and 64k. 2. Don‘t care bit for 32k. 13 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not. This fe ature s is initia te d by the stop condition af ter inputting wr ite data . This re quires the 8-bit devic e addr ess wor d following the start condition during a interna lly- timed wr ite cyc le. Ac knowledge polling will oper ate R /W code = “0”. Ac knowledgment “1” (no ac knowledgme nt) shows the EEP RO M is in a interna lly- timed wr ite cyc le and ac knowledgme nt “0” shows that the interna lly- timed wr ite cyc le has complete d. S ee Wr ite Cycle Polling using ACK. Write Cycle Polling Using ACK Send write command Send stop condition to initiate write cycle Send start condition Send device address word with R/W = 0 ACK returned No Yes Next operation is addressing the memory No Yes Proceed write operation 14 Send memory address Send start condition Proceed random address read operation Send stop condition Send stop condition HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Read Operation There are three read operations: current address read, random read, and sequential read. Read operations are initiated the same way as write operations with the exception of R/W = “1”. Current Address Read: The internal address counter maintains the last address accessed during the last read or write operation, with incr emented by one. C urre nt addr ess re ad ac ce sses the addr ess kept by the interna l addr ess counte r. Af te r re ce iving a start condition and the devic e addr ess wor d(R /W is “1”), the EEP RO M outputs the 8-bit cur re nt addr ess data fr om the most signif icant bit following ac knowledgme nt “0”. If the EEP RO M re ce ive s ac knowledgme nt “1” (no ac knowledgme nt) and a following stop condition, the EEP RO M stops the re ad oper ation and is turne d to a standby state. In ca se the EEP RO M have ac ce ssed the last addr ess of the last page at pre vious re ad oper ation, the cur re nt addr ess will roll over and re turns to ze ro addr ess. In ca se the EEPROM have accessed the last address of the page at previous write operation, the current address will roll over within page addr essing and re turns to the first addr ess in the same page . The cur re nt addr ess is valid while powe r is on. The cur re nt addr ess af ter powe r on will be indef inite. The ra ndom re ad oper ation described below is necessary to define the memory address. Current Address Read Operation Device address Start 1010 R D7 D6 D5 D4 D3 D2 D1 D0 *1 *2 *3 8k to 64k Read data (n+1) ACK R/W No ACK Stop Notes: 1. Don‘t care bit for 16k. 2. Don‘t care bits for 8k and 16k. 3. Don‘t care bits for 4k, 8k and 16k. 15 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEP RO M re ce ive s a start condition, devic e addr ess wor d(R /W =0) and memory addr ess (8- bit for 8kbit to 16kbit EEP RO Ms, 2 × 8-bit for 32kbit and 64kbit EEP RO Ms) seque ntia lly. The EEP RO M outputs acknowledgment “0” after receiving memory address then enters a current address read with receiving a start condition. The EEP RO M outputs the re ad data of the addr ess which wa s def ined in the dummy wr ite oper ation. Af te r re ce iving ac knowledgme nt “1”(no ac knowledgme nt) and a following stop condition, the EEPROM stops the random read operation and returns to a standby state. Random Read Operation W ACK R/W Start 1010 Start W ACK R/W 2nd Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 1010 1st Memory address (n) @@@ ACK No ACK Stop R/W Currect address read *1 *1 *1 a12 *2 a11 a10 a9 a8 32k to 64k R Start ACK Dummy write Device address Read data (n) # # # ACK Device address 1010 Start ACK Dummy write Notes: 1. Don‘t care bits for 32k and 64k. 2. Don‘t care bit for 32k. 3. 2nd device address code (#) should be same as 1st (@). 16 Read data (n) # # # R R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 1010 @@@ Device address D7 D6 D5 D4 D3 D2 D1 D0 8k to 16k Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 Device address No ACK Stop Currect address read HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Sequential Read: S equential re ads ar e initia te d by either a cur re nt addr ess re ad or a ra ndom re ad. If the EEP RO M re ce ive s ac knowledgme nt “0” af ter 8-bit re ad data , the re ad addr ess is incr emented and the next 8-bit re ad data ar e coming out. This oper ation ca n be continued as long as the EEP RO M re ce ive s ac knowledgme nt “0”. The addr ess will roll over and re turns addr ess ze ro if it re ac hes the last addr ess of the last page . The seque ntia l re ad ca n be continued af ter roll over . The seque ntia l re ad is ter mina te d if the EEP RO M re ce ive s acknowledgment “1” (no acknowledgment) and a following stop condition. Sequential Read Operation ACK R/W ACK ACK ACK D5 D4 D3 D2 D1 D0 R Read data (n+1) Read data (n+2) Read data (n+m) D7 D6 D5 D4 D3 D2 D1 D0 Start 1010 Read data (n) D7 D6 D5 D4 D3 D2 D1 D0 8k to 64k D7 D6 D5 D4 D3 D2 D1 D0 Device address No ACK Stop 17 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Notes Data Protection at VCC On/Off When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may ac t as a trigger and turn the EEP RO M to unintentional progr am mode. To pre vent this unintentional progr amming, this EEP RO M have a powe r on re set func tion. B e ca re ful of the notices desc ribed below in order for the power on reset function to operate correctly. • SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition during VCC on/off may cause the trigger for the unintentional programming. • VCC should be turned off after the EEPROM is placed in a standby state. • VCC should be turned on from the ground level(VSS ) in order for the EEPROM not to enter the unintentional programming mode. • VCC turn on speed should be longer than 10 us. Write/Erase Endurance and Data Retention Time The endur anc e is 105 cyc les in ca se of page progr amming and 104 cyc les in ca se of byte progr amming (1% cumulative fa ilur e ra te). The data re tention time is more than 10 yea rs whe n a devic e is page -pr ogrammed less than 104 cycles. Noise Suppression Time This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be careful not to allow noise of width more than 50 ns. 18 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Package Dimensions HN58X2408FPI/HN58X2416FPI/HN58X2432FPI/HN58X2464FPI (FP-8DB) As of January, 2002 Unit: mm 3.90 4.89 5.15 Max 5 8 0.69 Max 0.034 *0.22 +– 0.017 0.20 ± 0.03 4 1.73 Max 1 6.02 ± 0.18 1.06 *0.42 +0.063 –0.064 0.40 ± 0.06 0.114 0.14 +– 0.038 0˚ – 8˚ 1.27 0.289 0.60 +– 0.194 0.10 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC JEITA Mass (reference value) FP-8DB — — 0.08 g 19 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I HN58X2408TI/HN58X2416TI/HN58X2432TI/HN58X2464TI (TTP-8DA) As of January, 2002 Unit: mm 4.40 3.00 3.30 Max 8 5 1 4 0.65 *0.22 +0.08 –0.07 0.20 ± 0.06 1.00 0.13 M 6.40 ± 0.20 *Dimension including the plating thickness Base material dimension 20 0.07 +0.03 –0.04 0.10 *0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.805 Max 0˚ – 8˚ 0.50 ± 0.10 Hitachi Code JEDEC JEITA Mass (reference value) TTP-8DA — — 0.034 g HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I HN58X2416NIR (TNP-8DA) Unit: mm 3.00 3.10 Max + 0.08 0.22 – 0.07 0.65 4.06 ± 0.1 + 0.055 *0.145 – 0.045 0.125 ± 0.02 0.675 Max 0.80 Max 3.60 *0.18 ± 0.05 0.16 ± 0.025 0.23 0.10 0.08 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC JEITA Mass (reference value) TNP-8DA — — 0.022 g 21 HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 URL http://www.hitachisemiconductor.com/ For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585200 Hitachi Europe GmbH Electronic Components Group Dornacher Strasse 3 D-85622 Feldkirchen Postfach 201,D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright C Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 6.0 22