August 1992 11C06 750 MHz D-Type Flip-Flop General Description The 11C06 is a high-speed ECL D-Type Master-Slave FlipFlop capable of toggle rates over 750 MHz. Designed primarily for high-speed prescaling, it can also be used in any application which does not require preset inputs. The circuit is voltage-compensated, which makes input thresholds and Logic Symbol output levels insensitive to VEE variations. Complementary Q and Q outputs are provided, as are two Data inputs, Clock and Clock Enable inputs. The 11C06 is pin-compatible with the Motorola MC1690L but is a higher-frequency replacement. Connection Diagrams 16-Pin DIP 16-Pin Flatpak TL/F/9890–3 TL/F/9890 – 2 TL/F/9890 – 1 Truth Table Pin Names Dn CP CE Q, Q Description CE CP D Qn Data Input Clock Input Clock Enable (Active LOW) Outputs L L L L H L H L L X X X L H X Qnb1 Qnb1 L H Qnb1 H e HIGH Voltage Level L e LOW Voltage Level X e Don’t Care L e LOW to HIGH Transition Qnb1 e Previous State C1995 National Semiconductor Corporation TL/F/9890 RRD-B30M115/Printed in U. S. A. 11C06 750 MHz D-Type Flip-Flop Not Intended For New Designs Absolute Maximum Ratings Above which the useful life may be impaired Operating Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65§ C to a 150§ C Storage Temperature Maximum Junction Temperature (TJ) Supply Voltage Range Input Voltage (DC) Output Current (DC Output HIGH) b 5.7V to b 4.7V 300§ C Lead Temperature (Soldering, 10 sec.) Recommended Operating Conditions a 150§ C b 7.0V to GND VEE to GND b 50 mA Supply Voltage (VEE) Ambient Temperature (TA) Min Typ Max b 5.7V b 5.2V b 4.7V a 75§ C 0§ C DC Electrical Characteristics VEE e b5.2V, VCC e GND Parameter Min Max Units TA VOH Symbol Output Voltage HIGH b 1000 b 960 b 900 b 840 b 810 b 720 mV mV mV 0§ C a 25§ C a 75§ C VOL Output Voltage LOW b 1870 b 1850 b 1830 b 1635 b 1620 b 1595 mV mV mV a 25§ C a 75§ C mV mV mV a 25§ C a 75§ C b 1615 b 1600 b 1575 mV mV mV a 25§ C a 75§ C b 1135 b 1095 b 1035 b 840 b 810 b 720 mV mV mV a 25§ C a 75§ C b 1870 b 1850 b 1830 b 1500 b 1485 b 1460 mV mV mV a 25§ C a 75§ C 250 270 mA mA a 25§ C a 25§ C mA a 25§ C VIN e VIH (Min) mA a 25§ C All Inputs Open VOHC VOLC VIH Output Voltage HIGH Input Voltage LOW IIH b 1020 b 980 b 920 Output Voltage LOW Input Voltage HIGH VIL Typ Input Current HIGH Clock Input Data Input IIL Input Current LOW IEE Power Supply Current Conditions VIN e VIH (Max) or VIL (Min) per Truth Table Loading 50X to b2V 0§ C 0§ C VIN e VIH (Min) or VIL (Max) for Dn Inputs Loading 50X to b2V 0§ C 0§ C 0§ C Guaranteed Input Voltage HIGH for All Inputs Guaranteed Input Voltage LOW for All Inputs VIN e VIH (Max) 0.5 b 59 b 40 AC Electrical Characteristics VEE e b5.2V, VCC e GND, TA e a 25§ C Min Typ Max Units tPHL tPLH Symbol Propagation Delay (CP-Q) Propagation Delay (CP-Q) Parameter 0.7 0.7 1.0 1.0 1.2 1.2 ns ns tTLH tTHL Transition Time 20% to 80% Transition Time 80% to 20% 0.5 0.5 0.8 0.8 1.0 1.0 ns ns tS Set-up Time 0.2 tH Hold Time 0.2 ns fTOG (MAX) Toggle Frequency (CP) 750 MHz 650 See Figure 1 ns Note: The device is guaranteed for fTOG (CP) t 600 MHz, fTOG(CE) t 550 MHz over the 0§ C to a 75§ C temperature range. 2 Conditions See Figure 2 , Note Functional Description master-slave changes when the clock has slow rise or fall times. While the clock is LOW, the slave is held steady and the information on the D input is permitted to enter the master. The next transition from LOW to HIGH locks the master in its present state making it insensitive to the D input. This transition simultaneously connects the slave to the master causing the new information to appear on the outputs. Master and slave clock thresholds are internally offset in opposite directions to avoid race conditions or simultaneous The CP and CE inputs are logically identical, but physical constraints associated with the Dual-In-Line package make the CE input slower at the upper end of the toggle range. To prevent new data from entering the master on the next CP LOW cycle, CE should go HIGH while CP is still HIGH. TL/F/9890 – 4 RT e 50X termination of scope L1 e 50X impedance lines All input transition times are 2.0 ns g 0.2 ns FIGURE 1. Propagation Delay (CP to Q) TL/F/9890 – 5 RT e 50X termination of scope L1 e 50X impedance lines Adjust VBIAS for a 0.7V baseline of 800 mV peak-to-peak sinewave input. All input transition times are 2.0 ns g 0.2 ns FIGURE 2. Toggle Frequency Test Circuit 3 Typical Waveforms TL/F/9890 – 6 Horizontal Scale e 1.0 ns/div Vertical Scale e 200 mV/div Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 11C06 Device Number (basic) D C QR Special Variations QR e Commercial grade device with burn-in Package Code D e Ceramic Dual-In-Line F e Flatpak Temperature Range C e Commercial (0§ C to a 85§ C) 4 Physical Dimensions inches (millimeters) 16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 5 11C06 750 MHz D-Type Flip-Flop Physical Dimensions inches (millimeters) (Continued) 16 Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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