MM54HC620/MM74HC620 Inverting Octal TRI-STATEÉ Transceiver MM54HC623/MM74HC623 True Octal TRI-STATE Transceiver General Description These TRI-STATE bi-directional buffers utilize advanced silicon-gate CMOS technology and are intended for two-way asynchronous communication between data buses. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power consumption and high noise immunity usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending on the logic levels at the enable inputs. Both buses can be isolated from each other with proper logic levels at the enable inputs. When GAB is taken high and GBA is taken low, these devices store the states presently appearing at the data inputs. The 8-bit codes appearing on the two sets of buses will be indentical for the 623 option or complimentary for the 620 option. These devices can drive up to 15 LS-TTL loads. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features Y Y Y Y Y Typical propagation delays: 13 ns Wide power supply range: 2V – 6V Low quiescent supply current: 80 mA maximum (74HC series) TRI-STATE outputs for connection to system buses High output drive: 6 mA (minimum) Connection Diagrams Dual-In-Line Package Dual-In-Line Package TL/F/9393 – 1 Top View Order Number MM54HC623 or MM74HC623 TL/F/9393 – 2 Top View Order Number MM54HC620 or MM74HC620 Truth Table Enable Inputs GBA Operation GAB L L B data to A bus B data to A bus H H A data to B bus A data to B bus H L Isolation Isolation L B data to A bus, A data to B bus B data to A bus, A data to B bus L TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9393 RRD-B30M105/Printed in U. S. A. MM54HC620/MM74HC620 Inverting Octal TRI-STATE Transceiver MM54HC623/MM74HC623 True Octal TRI-STATE Transceiver March 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) b 0.5V to a 7.0V Supply Voltage (VCC) DC Input Voltage DIR and G pins (VIN) b1.5V to VCC a 1.5V b 0.5 to VCC a 0.5V DC Output Voltage (VIN, VOUT) g 20 mA Clamp Diode Current (ICD) g 35 mA DC Output Current, per pin (IOUT) g 70 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (TL) (Soldering, 10 seconds) 260§ C Operating Temp. Range (TA) MM74HC MM54HC Min 2 Max 6 Units V 0 VCC V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise/Fall Times (tr, tf) VCC e 2.0V VCC e 4.5V VCC e 6.0V DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC TA e 25§ C 74HC 54HC TA e b40§ C to a 85§ C TA e b55§ C to a 125§ C Units Typ Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s6.0 mA lIOUTl s7.8 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA g 0.5 g 5.0 g 10 mA 8.0 80 160 mA VIN e VIH or VIL lIOUTl s6.0 mA lIOUTl s7.8 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Input Leakage Current (G and DIR) IOZ Maximum TRI-STATE VOUT e VCC or GND 6.0V Output Leakage Enable G e VIH Current ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power dissipation temperature deratingÐplastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, tr e tf e 6 ns Symbol Parameter Conditions Typ Guaranteed Limit Units tPHL, tPLH Maximum Propagation Delay CL e 45 pF 15 ns tPZH, tPZL Maximum Output Enable Time RL e 1 kX CL e 45 pF 31 ns tPHZ, tPLZ Maximum Output Disable Time RL e 1 kX CL e 5 pF 18 ns AC Electrical Characteristics VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns unless otherwise specified Symbol Parameter Conditions VCC TA e 25§ C Typ tPHL, tPLH tPZH, tPZL 74HC 54HC TA e b40§ C to a 85§ C TA e b55§ C to a 125§ C Units Guaranteed Limits Maximum Propagation CL e 50 pF Delay CL e 150 pF 2.0V 2.0V 85 105 105 130 130 160 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 17 21 21 26 26 32 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 14 18 18 22 22 27 ns ns CL e 50 pF CL e 150 pF 2.0V 2.0V 170 195 215 245 255 295 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 34 39 43 49 51 59 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 29 33 37 42 43 50 ns ns Maximum Output Enable RL e 1 kX tPHZ, tPLZ Maximum Output Disable Time RL e 1 kX CL e 50 pF 2.0V 4.5V 6.0V 130 26 22 165 33 28 195 39 33 ns ns ns tTHL, tTLH Output Rise and Fall Time CL e 50 pF 2.0V 4.5V 6.0V 60 12 10 75 15 13 90 18 15 ns ns ns CPD Power Dissipation Capacitance (Note 5) GBA, GAB e VIL GBA e VIH, GAB e VIL CIN Maximum Input Capacitance CIN/OUT Maximum Input/Output Capacitance, A or B 120 12 pF pF 5 10 10 10 pF 15 20 20 20 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 MM54HC620/MM74HC620 Inverting Octal TRI-STATE Transceiver MM54HC623/MM74HC623 True Octal TRI-STATE Transceiver Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54HC620, MM54HC623, MM74HC620 or MM74HC623 NS Package Number J20A Molded Dual-In-Line Package (N) Order Number MM54HC620, MM54HC623, MM74HC620 or MM74HC623 NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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