DM54LS502/DM74LS502 8-Bit Successive Approximation Register General Description The LS502 is an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Complete (CC) signal coincident with storage of the eighth bit. An active LOW Start (S) input performs synchronous initialization which forces Q7 LOW and all other outputs HIGH. Subsequent clocks shift this Q7 LOW signal downstream which simultaneously backfills the register such that the first serial data (D input) bit is stored in Q7, the second bit in Q6, the third in Q5, etc. The serial input data is also synchronized by an auxiliary flip-flop and brought out on QD. Connection Diagram Designed primarily for use in the successive approximation technique for analog-to-digital conversion, the LS502 can also be used as a serial-to-parallel converter ring counter and as the storage and control element in recursive digital routines. Features Y Y Y Low power Schottky version of 2502 Storage and control for successive approximation A to D conversion Performs serial-to-parallel conversion Logic Symbol Dual-In-Line Package TL/F/10189 – 2 VCC e Pin 16 GND e Pin 8 TL/F/10189 – 1 Order Number DM54LS502J, DM54LS502W, DM74LS502WM or DM74LS502N See NS Package Number J16A, M16B, N16E or W16A C1995 National Semiconductor Corporation Pin Names Description D S CP QD CC Q0–Q7 Q7 Serial Data Input Start Input (Active LOW) Clock Pulse Input (Active Rising Edge) Synchronized Serial Data Output Conversion Complete Output (Active LOW) Parallel Register Outputs Complement of Q7 Output TL/F/10189 RRD-B30M105/Printed in U. S. A. DM54LS502/DM74LS502 8-Bit Successive Approximation Register April 1992 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS DM74LS 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol DM54LS502 Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage DM74LS502 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 2 2 V V 0.7 0.8 V b 0.4 mA 8 mA 70 §C IOH High Level Output Current b 0.4 IOL Low Level Output Current 4 TA Free Air Operating Temperature ts(H) ts(L) Setup Time HIGH or LOW S to CP 5 5 16 16 ns th(H) th(L) Hold Time HIGH or LOW S to CP 5 5 0 0 ns ts(H) ts(L) Setup Time HIGH or LOW D to CP 5 5 8 8 ns th(H) th(L) Hold Time HIGH or LOW D to CP 5 5 10 10 ns tw(H) tw(L) CP Pulse Width HIGH or LOW 20 20 46 46 ns b 55 125 0 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max, VIL e Max DM54 2.5 DM74 2.7 Low Level Output Voltage VCC Min, IOL e Max, VIH e Min DM54 0.4 DM74 0.5 IOL e 4 mA, VCC e Min DM74 0.4 DM74 DM54 0.1 VOL V V II Input Current @ Max Input Voltage VCC e Max, VI e 7V VI e 10V IIH High Level Input Current VCC e Max, VI e 2.7V 20 mA IIL Low Level Input Current VCC e Max, VI e 0.4V b 0.8 mA IOS Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max ICC DM54 b 20 b 100 DM74 b 20 b 100 65 Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Note more than one output should be shorted at a time, and the duration should not exceed one second. 2 mA mA mA Switching Characteristics VCC e a 5.0V, TA e a 25§ C DM54LS502 Symbol Parameter Min fmax Maximum Clock Frequency tPLH tPHL Propagation Delay CP to Qn or CC DM74LS502 Units RL e 2 kX, CL e 15 pF Max 25 Min Max 15 35 25 MHz 35 25 ns Functional Description The register stages are composed of transparent RS latches arranged in master/slave pairs. The master and slave latches are enabled separately by non-overlapping complementary signals w1 and w2 derived internally from the CP input. Master latches are enabled when CP is LOW and slave latches are enabled when CP is HIGH. Information is transferred from master to slave, and thus to the outputs, by the LOW-to-HIGH transition of CP. Initializing the register requires a LOW signal on S while exercising CP. With S and CP LOW, all master latches are SET (Q side HIGH). A LOW-to-HIGH CP transition, with S remaining LOW, then forces the slave latches to the condition wherein Q7 is LOW and all other register outputs, including CC, are HIGH. This condition will prevail as long as S remains LOW, regardless of subsequent CP rising edge. To start the conversion process, S must return to the HIGH state. On the next CP rising edge, the information stored in the serial data input latch is transferred to QD and Q7, while Q6 is forced to the LOW state. On the rising edge of the next seven clocks, this LOW signal is shifted downstream, one bit at a time, while the serial data enters the register position one bit behind this LOW signal, as shown in the Truth Table. Note that after a serial data bit appears at a particular output, that register position undergoes no further changes. After the shifted LOW signal reaches CC, the register is locked up and no further changes can occur until the register is initialized for the next conversion process. TL/F/10189 – 4 FIGURE a. Figure a shows a simplified hook-up of a LS502, a D/A converter and a comparator arranged to convert an analog input voltage into an 8-bit binary number by the successive approximation technique. Figure b is an idealized graph showing the various values that the D/A converter output voltage can assume in the course of the conversion. The vertical axis is calibrated in fractions of the full-scale output capability of the D/A converter and the horizontal axis represents the successive states of the Truth Table. At time t1, Q7 is LOW and Q6–Q0 are HIGH, causing the D/A output to be one-half of full scale. If the analog input voltage is greater than this voltage the comparator output (hence the D input of the LS502) will be LOW, and at times t2 the D/A output will rise to three-fourths of full scale because Q7 will remain LOW and contribute 50% while Q6 is forced LOW and contributes another 25%. On the other hand, if the analog input voltage is less than one-half of full scale, the comparator output will be HIGH and Q7 will go HIGH at t2. Q6 will still be forced LOW at t2, and the D/A output will decrease to 25% of full scale. Thus with each successive clock, the D/A output will change by smaller increments. When the conversion is completed at t9, the binary number represented by the register outputs will be the numerator of the fraction n/256, representing the analog input voltage as a fraction of the full scale output D/A converter. TL/F/10189 – 5 FIGURE b. 3 Truth Table Inputs Outputs Time tn D S QD Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 CC 0 1 2 X D7 D6 L H H X X D7 X L D7 X H L X H H X H H X H H X H H X H H X H H X H H 3 4 5 6 D6 D4 D3 D2 H H H H D6 D5 D4 D3 D7 D7 D7 D7 D6 D6 D6 D6 L D5 D5 D5 H L D4 D4 H H L D3 H H H L H H H H H H H H H H H H 7 8 9 10 D1 D0 X X H H H H D2 D1 D0 X D7 D7 D7 D7 D6 D6 D6 D6 D5 D5 D5 D5 D4 D4 D4 D4 D3 D3 D3 D3 D2 D2 D2 D2 L D1 D1 D1 H L D0 D0 H H L L H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Logic Diagram TL/F/10189 – 3 Note: Cell logic is repeated for register stages Q5 to Q1. 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS502J NS Package Number J16A 16-Lead Wide Small Outline Molded Package (M) Order Number DM74LS502WM NS Package Number M16B 5 DM54LS502/DM74LS502 8-Bit Successive Approximation Register Physical Dimensions inches (millimeters) (Continued) 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS502N NS Package Number N16E 16-Lead Ceramic Flat Package (W) Order Number DM54LS502W NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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