NTMD3N08LR2 Advance Information Power MOSFET 2.3 Amps, 80 Volts N–Channel Enhancement–Mode SO–8 Dual Package http://onsemi.com Features • Ultra Low On–Resistance Provides Higher Efficiency RDS(on) = 0.215 , VGS = 10 V ♦ RDS(on) = 0.245 , VGS = 5.0 V Low Reverse Recovery Losses Internal RG = 50 Designed for Power Management Solutions in 42 V Automotive System Applications IDSS and RDS(on) Specified at Elevated Temperature Avalanche Energy Specified Miniature SO–8 Surface Mount Package – Saves Board Space Mounting Information for SO–8 Package Provided ♦ • • • • • • • 2.3 AMPERES 80 VOLTS 215 mΩ @ VGS = 5 V (Typ) DUAL SO–8 CASE 751 STYLE 11 Applications • • • • Integrated Starter Alternator Electronic Power Steering Electronic Fuel Injection Catalytic Converter Heaters MARKING DIAGRAM & PIN ASSIGNMENT MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain–to–Source Voltage Drain–to–Source Voltage (RGS = 1.0 m) Symbol Value Unit VDSS VDGR 80 80 V V Gate 1 Source 2 Gate–to–Source Voltage – Continuous Gate–to–Source Voltage – Non–Repetitive (tp ≤ 10 ms) VGS ±15 VGSM ±20 Continuous Drain Current @ TA = 25°C Pulsed Drain Current (Note 1) ID IDM 2.3 25 A Total Power Dissipation @ TA = 25°C (Note 2) PD 3.1 W Operating and Storage Temperature Range TJ, Tstg –55 to +175 °C Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C (VDD = 50 Vdc, VGS = 5.0 Vdc, Peak IL = 7.0 Apk, L = 1.0 mH, RG = 25 ) EAS 25 mJ Thermal Resistance – Junction–to–Ambient (Note 2) RJA 48 TL 260 Maximum Lead Temperature for Soldering Purposes for 10 Seconds Source 1 Gate 2 1 8 2 7 3 3N08 AYWW 6 5 4 Drain 1 Drain 1 Drain 2 Drain 2 (Top View) 3N08 A Y WW = Specific Device Code = Assembly Location = Year = Work Week ORDERING INFORMATION °C/W Device Package NTMD3N08LR2 SO–8 Shipping 2500/Tape & Reel °C 1. Pulse Test: Pulse Width = 10 s, Duty Cycle = 2% 2. Mounted onto a 2″ square FR–4 board (1″ sq. oz. Cu 0.06″ thick single sided), t ≤ 5 seconds This document contains information on a new product. Specifications and information herein are subject to change without notice. Semiconductor Components Industries, LLC, 2002 August, 2002 – Rev. 2 1 Publication Order Number: NTMD3N08LR2/D NTMD3N08LR2 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 80 – – 99.8 – – Vdc mV/°C – – – – 10 250 – – – – 100 –100 1.0 – 1.9 4.6 3.0 – – – – 0.215 0.190 0.446 0.245 0.215 0.505 OFF CHARACTERISTICS V(BR)DSS Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Positive Temperature Coefficient Zero Gate Voltage Drain Current (VDS = 80 Vdc, VGS = 0 Vdc) (VDS = 80 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate–Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) (VGS = –15 Vdc, VDS = 0 Vdc) IGSS µAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Negative Temperature Coefficient VGS(th) Static Drain–to–Source On–State Resistance (VGS = 5.0 Vdc, ID = 1.0 Adc) (VGS = 10 Vdc, ID = 2.5 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc, TJ @ 150°C) RDS(on) Vdc mV/°C Ω DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss – 218 480 Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Coss – 54 150 Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Crss – 15 50 td(on) – – 21 13 34 – tr – – 62 95 104 – td(off) – – 52 47 85 – Fall Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 ) Fall Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 ) tf – – 48 104 81 – Total Gate Charge (VDS = 40 Vdc, VGS = 5.0 Vdc, ID = 1.0 A) Total Gate Charge (VDS = 40 Vdc, VGS = 10 Vdc, ID = 1.0 A) Qtot – – 4.0 7.5 9.0 15 Gate–Source Charge (VDS = 40 Vdc, VGS = 5.0 Vdc, ID = 1.0 A) Q1 – 1.16 – Gate–Drain Charge (VDS = 40 Vdc, VGS = 5.0 Vdc, ID = 1.0 A) Q2 – 2.11 – – – 0.8 1.4 1.0 – trr – 47 93 ta – 25 – tb – 22 – QRR – 0.067 0.134 pF SWITCHING CHARACTERISTICS (Notes 3 and 4) Turn–On Delay Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 ) Turn–On Delay Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 ) Rise Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 ) Rise Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 ) Turn–Off Delay Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 ) Turn–Off Delay Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 ) ns nC BODY–DRAIN DIODE RATINGS (Note 3) Diode Forward On–Voltage (IS = 1.0 Adc, VGS = 0 V) (IS = 1.0 Adc, VGS = 0 V, TJ = 150°C) VSD Reverse Recovery Time (IS = 1 1.0 0A A, dIS/dt = 100 A/ A/s, VGS = 0 V) Reverse Recovery Stored Charge (IS = 1.0 A, dIS/dt = 100 A/s, VGS = 0 V) 3. Indicates Pulse Test: Pulse Width = 300 µs max, Duty Cycle = 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 Vdc ns C NTMD3N08LR2 TYPICAL ELECTRICAL CHARACTERISTICS 5V 9V 4 6 4V 10 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 5 8V 6V VGS = 3.5 V 7V 3 2 TJ = 25°C 1 VDS ≥ 10 V 5 4 3 TJ = 25°C 2 1 TJ = 100°C 0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 0 2 1 2 3 4 5 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 0.5 VGS = 5.0 V 0.4 TJ = 100°C 0.3 TJ = 25°C 0.2 TJ = –55°C 0.1 0 1 0 2 3 6 Figure 2. Transfer Characteristics RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) Figure 1. On–Region Characteristics 4 5 ID, DRAIN CURRENT (AMPS) 0.3 TJ = 25°C 0.25 VGS = 5.0 V 0.2 VGS = 10 V 0.15 0.1 0.05 0 1 0 2 3 4 5 ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Drain Current and Temperature Figure 4. On–Resistance versus Drain Current and Gate Voltage 2.5 100,000 VGS = 5.0 V ID = 1.5 A VGS = 0 V 2 10,000 IDSS, LEAKAGE (nA) RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) TJ = –55°C 1.5 1 TJ = 175°C 1000 100 TJ = 100°C 10 0.5 0 –50 –25 1 0 25 50 75 100 125 150 175 10 20 30 40 50 60 70 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–To–Source Leakage Current versus Voltage http://onsemi.com 3 80 NTMD3N08LR2 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) 600 C, CAPACITANCE (pF) 500 VDS = 0 V VGS = 0 V TJ = 25°C Ciss 400 300 Crss Ciss 200 100 Coss Crss 0 –10 –5 0 VGS 5 10 15 20 25 VDS GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 80 QT 70 8 VDS 60 VGS 50 6 40 Q1 Q2 4 30 20 2 0 ID = 2.3 A TJ = 25°C 10 Q3 0 1 3 2 4 5 0 QG, TOTAL GATE CHARGE (nC) 1000 VDD = 64 V ID = 2.3 A VGS = 5.0 V 100 t, TIME (ns) 10 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) NTMD3N08LR2 tr td(off) tf td(on) 10 1 1 10 100 RG, GATE RESISTANCE (Ω) Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN–TO–SOURCE DIODE CHARACTERISTICS high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by IS, SOURCE CURRENT (AMPS) 2.5 VGS = 0 V TJ = 25°C 2 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current http://onsemi.com 5 NTMD3N08LR2 SAFE OPERATING AREA ID, DRAIN CURRENT (AMPS) 100 10 VGS = 20 V SINGLE PULSE TC = 25°C 10 s 100 µs 1 ms 1 10 ms 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT dc 0.01 0.1 1 10 100 total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. EAS, SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance – General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 µs. In addition the 25 ID = 2.3 A 20 15 10 5 0 25 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE (C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 6 NTMD3N08LR2 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 0.1 0.01 D = 0.5 0.2 0.1 0.05 0.02 Normalized to θja at 10s. Chip 0.01 SINGLE PULSE 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.0154 F 0.0854 F 0.3074 F 1.0E-01 t, TIME (s) 1.0E+00 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 7 0.5776 Ω 1.7891 F 1.0E+01 0.7086 Ω 107.55 F 1.0E+02 Ambient 1.0E+03 NTMD3N08LR2 INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self–align when subjected to a solder reflow process. 0.060 1.52 0.275 7.0 0.155 4.0 0.024 0.6 0.050 1.270 inches mm SO–8 POWER DISSIPATION The power dissipation of the SO–8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO–8 package, PD can be calculated as follows: PD = into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. PD = 150°C – 25°C = 2.0 Watts 62.5°C/W The 62.5°C/W for the SO–8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 8 NTMD3N08LR2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 “SOAK” 160°C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205° TO 219°C “SPIKE” PEAK AT 170°C SOLDER JOINT 150°C 150°C 100°C 140°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 9 NTMD3N08LR2 PACKAGE DIMENSIONS DUAL SO–8 CASE 751–06 ISSUE T D A 8 E 5 0.25 H 1 M B M 4 h B X 45 e A C SEATING PLANE L 0.10 A1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C B 0.25 M C B S A S DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0 7 STYLE 11: PIN 1. 2. 3. 4. 5. 6. 7. 8. http://onsemi.com 10 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 NTMD3N08LR2 Notes http://onsemi.com 11 NTMD3N08LR2 Thermal Clad is a registered trademark of the Bergquist Company. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 2–9–1 Kamimeguro, Meguro–ku, Tokyo, Japan 153–0051 Phone: 81–3–5773–3850 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 12 NTMD3N08LR2/D