PIC16C67 PIC16C67 Rev. A Silicon Errata Sheet The PIC16C67 (Rev. A) parts you have received conform functionally to the Device Data Sheet (DS30234D), except for the anomalies described below. All the problems listed here will be addressed in future revisions of the PIC16C67 silicon. Work around To have the I/O pin high until the compare match low occurs, force a compare match high to get the I/O pin into the high state, then reconfigure the compare match to force the I/O low, when the compare condition occurs. 2. Module: SSP Module (I2C™ mode) 1. Module: CCP (Compare Mode) The Compare mode may not operate as expected when configuring the compare match to drive the I/O pin low (CCPxM<3:0> = 1001). When the CCP module is changed to compare output low (CCPxM<3:0> = 1001) from any other non-compare CCP mode, the I/O pin will immediately be driven low, regardless of the state of the I/O data latch. The pin will remain low when the compare match occurs (see Table 1). However, when the CCP module is changed to compare output high (CCPxM<3:0> = 1000) from any other CCP mode, the I/O pin will immediately be driven low, regardless of the state of the I/O data latch. The pin will be driven high when the compare match occurs. If the bus is active when the I2C mode is enabled, and the next 8-bits of data on the bus match the address of the device, then the SSP module will generate an Acknowledge pulse. Work around Before enabling the I2C mode, ensure that the bus is not active. 3. Module: Timer0 The TMR0 register may increment when the WDT postscaler is switched to the Timer0 prescaler. If TMR0 = FFh, this will cause TMR0 to overflow (setting T0IF). Work around Follow the following sequence: TABLE 1: CCP Mode CCPxM<3:0> = COMPARE OUTPUT LOW SWITCHING I/O pin State Change CCP to CCPxM<3:0> = 1001 1000 H L L L L L H H — L L — H — L L — L H L L L L L H L L L L L a) Read the 8-bit TMR0 register into the W register b) Clear the TMR0 register c) Assign WDT postscaler to Timer0 d) Write W register to TMR0 0xxx 1000 1001 101x 11xx 2001 Microchip Technology Inc. DS80098A-page 1 PIC16C67 Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS30234D), the following clarifications and corrections should be noted. 1. Module: I/O Ports The specification for the High Voltage Open Drain I/O (parameter D150, the RA4 pin) cannot be met without possible long term reliability issues on that I/O pin. If a high voltage drive is required, use an external transistor that can support the required voltage. The new value is shown in Table 2. TABLE 2: DC SPECIFICATION CHANGES FROM DATA SHEET Data Sheet Specification New Specification Param No. Sym. D150 VOD Characteristic RA4 Open Drain High Voltage Units Min Typ Max Min Typ Max — — 10 — — 14 V 2. Module: SSP (SPI Mode Timing Specifications) The SPI interface timings (parameters 71, 71A, 72, 72A, 73, and 73A) have been modified. The new values are shown in Table 3. TABLE 3: Param No. New Specification Sym. 71 TSCH 71A 72 TSCL 72A 73A DC SPECIFICATION CHANGES FROM DATA SHEET TB2B Characteristic SCK input high time Continuous (Slave mode) Single Byte(1) SCK input low time (Slave mode) Continuous Single Byte(1) Last clock edge of the Byte1 to 1st clock edge of the Byte2(1) Data Sheet Specification Units Min Typ Max Min Typ Max 1.25 TCY + 30 ns — — TCY + 20 ns — — 40 — — 1.25 TCY + 30 ns — — 40 — — N.A. 1.5 TCY + 40 ns — — N.A. N.A. TCY + 20 ns — ns ns — ns ns ns * This parameter is characterized but not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. DS80098A-page 2 2001 Microchip Technology Inc. PIC16C67 3. Module: Timer1 The operation of Timer1 needs some clarification when the timer registers are written and the TMR1ON bit is set. When the TMR1H and/or TMR1L registers are written while this clock is low, TMR1 will not increment on the next rising edge of this clock, but must first have a falling clock and the rising clock for TMR1 to increment. The internal clock signal, that is the input to the TMR1 prescaler, affects the incrementing of Timer1 (TMR1H:TMR1L registers and the Timer1 prescaler). When the Timer1 registers are NOT written, the Timer1 will increment on the rising edge of the TMR1 increment clock. Figure 1 shows the two cases of writes to the TMR1H and/or TMR1L registers. Due to the VIH and VIL thresholds on the oscillator/clock pins, external Timer1 oscillator components, and external clock frequency, the Timer1 increment clock may not be of a 50% duty cycle. When the TMR1H and/or TMR1L registers are written while this clock is high, TMR1 will increment on the next rising edge of this clock. The TMR1 increment clock is out of phase of the T1OSO/T1CKI pin by a small propagation delay. FIGURE 1: WRITES TO TIMER1 (EXTERNAL CLOCK/OSCILLATOR MODE) TMR1 Increment Clock (Input to Prescaler) Write to TMR1H and/or TMR1L Register(s) TMR1H:TMR1L Increments 2001 Microchip Technology Inc. Write to TMR1H and/or TMR1L Register(s) TMR1H:TMR1L Increments DS80098A-page 3 PIC16C67 4. Module: RC Oscillator The table for RC Oscillator Frequencies in the Device Characterization section of the Data Sheet is incorrect. The correct characterization information is shown in Table 4. TABLE 4: RC OSCILLATOR FREQUENCIES CHARACTERIZATION CHANGES FROM DATA SHEET Correct Characterization Data Current Data Sheet Values REXT CEXT 22 pF 100 pF 330 pF Average % Variation Average % Variation 5.1 K 3.55 MHz ± 9.63% 4.12 MHz ± 1.4% 10 K 1.99 MHz ± 10.53% 2.35 MHz ± 1.4% 100 K 221.9 kHz ± 12.10% 268 kHz ± 1.1% 3.3 K 1.77 MHz ± 10.67% 1.80 MHz ± 1.0% 5.1 K 1.22 MHz ± 10.41% 1.27 MHz ± 1.0% 10 K 669.4 kHz ± 10.92% 688 kHz ± 1.2% 100 K 71.5 kHz ± 11.21% 77.2 kHz ± 1.0% 3.3 K 625.1 kHz ± 10.68% 707 kHz ± 1.4% 5.1 K 428.5 kHz ± 10.96% 501 kHz ± 1.2% 10 K 231.9 kHz ± 11.32% 269 kHz ± 1.6% 100 K 24.4 kHz ± 12.93% 28.3 kHz ± 1.1% The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is ±3 standard deviation from the average value for VDD = 5V. 5. Module: Brown-Out Reset (BOR) The levels specified for the BOR module thresholds (parameter D005) have changed. The new values are shown in Table 5. TABLE 5: Param No. D005 . MINIMUM AND MAXIMUM BOR RESET VOLTAGES Data Sheet Specification New Specification Sym. VBOR DS80098A-page 4 Characteristic Brown-out Reset Voltage Min Typ Max Min Typ Max 3.65 — 4.35 3.70 — 4.30 Units V 2001 Microchip Technology Inc. “All rights reserved. Copyright © 2001, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.” Trademarks The Microchip name, logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, MPLAB and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICDEM, ICEPIC, Migratable Memory, FanSense, ECONOMONITOR, SelectMode and microPort are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Term Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2001, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2001 Microchip Technology Inc. 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Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS80098A-page 6 2001 Microchip Technology Inc.