MM54HC646/MM74HC646 Non-Inverting Octal Bus Transceiver/Registers MM54HC648/MM74HC648 Inverting Octal Bus Transceiver/Registers General Description These transceivers utilize advanced silicon-gate CMOS technology, and contain two sets of TRI-STATEÉ outputs, two sets of D-type flip-flops, and control circuitry designed for high speed multiplexed transmission of data. Six control inputs enable this device to be used as a latched transceiver, unlatched transceiver, or a combination of both. As a latched transceiver, data from one bus is stored for later retrieval by the other bus. Alternately real time bus data (unlatched) may be directly transferred from one bus to another. Circuit operation is determined by the G, DIR, CAB, CBA, SAB, SBA control inputs. The enable input, G, controls whether any bus outputs are enabled. The direction control, DIR, determines which bus is enabled, and hence the direction data flows: The SAB, SBA inputs control whether the latched data (stored in D type flip flops), or the bus data (from other bus input pins) is transferred. Each set of flip- flops has its own clock CAB, and CBA, for storing data. Data is latched on the rising edge of the clock. Each output can drive up to 15 low power Schottky TTL loads. These devices are functionally and pin compatible to their LS-TTL counterparts. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features Y Y Y Y Y Y Typical propagation delay: 14 ns TRI-STATE outputs Bidirectional communication Wide power supply range: 2 – 6V Low quiescent supply current: 160 mA maximum (74HC) High output current: 6 mA (74HC) Connection Diagram Dual-In-Line Package Order Number MM54HC646/648 or MM74HC646/648 TL/F/5345 – 2 TL/F/5345 – 1 Real-Time Transfer Bus B to Bus A Real-Time Transfer Bus A to Bus B Storage from A, B, or A and B Transfer Stored Data to A or B TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/F/5345 RRD-B30M105/Printed in U. S. A. MM54HC646/MM74HC646 Non-Inverting Octal Bus Transceiver/Registers MM54HC648/MM74HC648 Inverting Octal Bus Transceiver/Registers January 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 0.5 to a 7.0V Supply Voltage (VCC) b 1.5 to VCC a 1.5V DC Input Voltage (VIN) b 0.5 to VCC a 0.5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK, IOK) g 35 mA DC Output Current, per pin (IOUT) g 70 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§ C Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temp. Range (TA) MM74HC MM54HC Input Rise or Fall Times (tr, tf) VCC e 2.0V VCC e 4.5V VCC e 6.0V Min 2 0 Max 6 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns DC Electrical Characteristics (Note 4) Symbol Parameter Conditions TA e 25§ C VCC Typ 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.96 5.46 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL 6.0 mA lIOUTl s lIOUTl s7.8 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V VIN e VIH or VIL 6.0 mA lIOUTl s lIOUTl s7.8 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA IOZ Maximum TRI-STATE Output Leakage VOUT e VCC or GND G e VIH 6.0V g 0.5 g 5.0 g 10 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 8.0 80 160 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. ** VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. Truth Table Inputs G DIR CAB X X X X u H H X X X u H or L Data I/O Operation or Function CBA SAB SBA A1 Thru A8 B1 Thru B8 ’ALS646, ’ALS647 ’AS646 X X X X X Input Not Specified Not Specified Input Store A, B Unspecified Store B, A Unspecified Store A, B Unspecified Store B, A Unspecified X X X X Input Input Store A and B Data Isolation, hold storage Store A and B Data Isolation, hold storage u u H or L 2 ’ALS648, ’ALS649 ’AS648 Truth Table (Continued) Inputs Data I/O Operation or Function G DIR CAB CBA SAB SBA A1 Thru A8 B1 Thru B8 ’ALS646, ’ALS647 ’AS646 ’ALS648, ’ALS649 ’AS648 L L L L X X X X X X L H Output Input Real-Time B Data to A Bus Stored B Data to A Bus Real-Time B Data to A Bus Stored B Data to A Bus L L H H X X X X L H X X Input Output Real-Time A Data to B Bus Stored A Data to B Bus Real-Time A Data to B Bus Stored A Data to B Bus u e low-to-high level transition H e High Level L e Low Level X e Irrelevant The data output functions i.e., data at the bus pins may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled. The data output functions i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. AC Electrical Characteristics MM54HC646/MM74HC646, MM54HC648/MM74HC648 VCC e 5V, TA e 25§ C, tr e tf e 6 ns Symbol Parameter Conditions Typ Guaranteed Limit Units 45 30 MHz fMAX Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay, A or B Input to B or A Output CL e 45 pF 14 25 ns tPHL, tPLH Maximum Propagation Delay, CBA or CAB Input to A or B Output CL e 45 pF 31 40 ns tPHL, tPLH Maximum Propagation Delay, SBA or SAB Input to A or B Output, with A or B high CL e 45 pF 35 50 ns tPHL, tPLH Maximum Propagation Delay, SBA or SAB Input to A or B Output, with A or B low CL e 45 pF 35 50 ns tPZH, tPZL Maximum Enable Time G or DIR Input to A or B Output RL e 1 kX CL e 45 pF 18 33 ns tPHZ, tPLZ Maximum Disable Time, G or DIR Input to A or B Output RL e 1 kX CL e 5 pF 17 30 ns AC Electrical Characteristics MM54HC646/MM74HC646, MM54HC648/MM74HC648 VCC e 2.0–6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC TA e 25§ C Typ fMAX Maximum Operating Frequency CL e 50 pF 2.0V 4.5V 6.0V tPHL, tPLH Maximum Propagation Delay, A or B Input to B or A Output CL e 50 pF CL e 150 pF 2.0V 2.0V CL e 50 pF CL e 150 pF tPHL, tPLH Maximum Propagation Delay, CBA or CAB Input to A or B Output 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits 5 27 31 4 21 24 3 18 20 MHz MHz MHz 60 80 180 200 189 250 225 300 ns ns 4.5V 4.5V 21 30 30 40 37 50 45 60 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 18 22 26 35 31 44 39 53 ns ns CL e 50 pF CL e 150 pF 2.0V 2.0V 110 150 220 270 275 338 330 405 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 31 40 44 54 55 68 66 81 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 28 34 38 47 47 59 57 71 ns ns 3 AC Electrical Characteristics MM54HC646/MM74HC646, MM54HC648/MM74HC648 (Continued) VCC e 2.0b6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC TA e 25§ C Typ tPHL, tPLH Maximum Propagation Delay, SBA or SAB Input to A or B Output tPZL, tPZL 74HC 54HC TA eb40 to 85§ C TA eb55 to 125§ C Units Guaranteed Limits CL e 50 pF 2.0V 85 CL e 150 pF 2.0V 110 170 220 214 277 253 328 ns ns CL e 50 pF 4.5V CL e 150 pF 4.5V 17 22 34 44 43 55 51 66 ns ns CL e 50 pF 6.0V CL e 150 pF 6.0V 14 19 29 37 36 47 43 56 ns ns Maximum Output Enable RL e 1 kX Time, G Input or DIR to A or B CL e 50 pF 2.0V 80 Output CL e 150 pF 2.0V 120 175 225 219 281 263 338 ns ns tPHZ, tPLZ Maximum Output Disable Time, G Input to A or B Output tTHL, tTLH Maximum Output Rise and Fall Time CL e 50 pF 4.5V CL e 150 pF 4.5V 23 31 35 45 44 56 53 68 ns ns CL e 50 pF 6.0V CL e 150 pF 6.0V 21 27 30 38 37 48 45 57 ns ns RL e 1 kX CL e 50 pF 85 23 21 175 35 30 219 44 37 263 53 45 ns ns ns 2.0V 4.5V 6.0V 60 12 10 75 15 13 90 18 15 ns ns ns CL e 50 pF 2.0V 4.5V 6.0V tS Minimum Set Up Time 2.0V 4.5V 6.0V 100 20 17 125 25 21 150 30 25 ns ns ns tH Minimum Hold Time 2.0V 4.5V 6.0V 0 0 0 0 0 0 0 0 0 ns ns ns tW Minimum Pulse Width of Clock 2.0V 4.5V 6.0V 80 16 14 100 20 18 120 24 21 ns ns ns tr, tf Maximum Input Rise and Fall Time 2.0V 4.5V 6.0V 1000 500 400 1000 500 400 1000 500 400 ns ns ns CPD Power Dissipation Capacitance (Note 5) 90 pF CIN Maximum Input Capacitance 5 10 10 10 pF COUT Maximum Output Capacitance 15 20 20 20 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD, VCC2 f a ICC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. Note 6: Refer to back of this section for Typical MM54/74HC AC Switching Waveforms and Test Circuits. 4 TL/F/5345 – 3 Logic Diagram 5 MM54HC646/MM74HC646 Non-Inverting Octal Bus Transceiver/Registers MM54HC648/MM74HC648 Inverting Octal Bus Transceiver/Registers Physical Dimensions inches, (millimeters) Order Number MM54HC646J, MM54HC648J, MM74HC646J, or MM74HC648J NS Package J24F LIFE SUPPORT POLICY Order Number MM74HC646N, MM74HC648N NS Package N24C NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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