54ACT/74ACT823 9-Bit D Flip-Flop General Description Features The ’ACT823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. The ’ACT823 offers noninverting outputs and is fully compatible with AMD’s Am29823. Y Y Y Y Outputs source/sink 24 mA TRI-STATEÉ outputs for bus interfacing Inputs and outputs are on opposite sides ’ACT823 has TTL-compatible inputs Logic Symbols Connection Diagrams IEEE/IEC Pin Assignment for DIP, Flatpak and SOIC TL/F/9894–1 TL/F/9894 – 2 TL/F/9894 – 3 Pin Assignment for LCC Pin Names Description D0 – D8 O0 – O8 OE CLR CP EN Data Inputs Data Outputs Output Enable Clear Clock Input Clock Enable TL/F/9894 – 4 FACTTM is a trademark of National Semiconductor Corporation. TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9894 RRD-B30M75/Printed in U. S. A. 54ACT/74ACT823 9-Bit D Flip-Flop March 1993 Functional Description the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear (CLR) and Clock Enable (EN) pins. These devices are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. The ’ACT823 consists of nine D-type edge-triggered flipflops. These have TRI-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect Function Table Inputs Internal Output OE CLR EN CP D Q O H H H L H L H H L L X X L L H H H H H H L L X X H H L L L L L L X X X X L L L L L H X X X X L H L H L H L L NC NC L H L H Z Z Z L Z NC Z Z L H Function High Z High Z Clear Clear Hold Hold Load Load Load Load H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance L e LOW-to-HIGH Transition NC e No Change Logic Diagram TL/F/9894 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) ’ACT Input Voltage (VI) b 0.5V to 7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) b 20 mA VI e b0.5V a 20 mA VI e VCC a 0.5V b 0.5V to VCC a 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) b 20 mA VO e b0.5V a 20 mA VO e VCC a 0.5V b 0.5V to VCC a 0.5V DC Output Voltage (VO) g 50 mA DC Output Source or Sink Current (IO) DC VCC or Ground Current g 50 mA per Output Pin (ICC or IGND) b 65§ C to a 150§ C Storage Temperature (TSTG) Junction Temperature (TJ) CDIP 175§ C PDIP 140§ C 4.5V to 5.5V 0V to VCC 0V to VCC Output Voltage (VO) Operating Temperature (TA) 74ACT 54ACT b 40§ C to a 85§ C b 55§ C to a 125§ C Minimum Input Edge Rate (DV/Dt) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT TM circuits outside databook specifications. DC Electrical Characteristics 74ACT 54ACT 74ACT TA e TA e b 55§ C to a 125§ C b 40§ C to a 85§ C Units Parameter VCC (V) VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 V VOUT e 0.1V or VCC b0.1V VIL Maximum Low Level Input Voltage 4.5 4.5 1.5 1.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOUT e 0.1V or VCC b0.1V VOH Minimum High Level 4.5 4.49 5.49 4.4 5.4 4.4 5.4 4.4 5.4 V IOUT e b50 mA 3.86 4.86 3.70 4.70 3.76 4.76 V 0.1 0.1 0.1 0.1 0.1 0.1 V 4.5 5.5 0.36 0.36 0.50 0.50 0.44 0.44 V 5.5 g 0.1 g 1.0 g 1.0 mA VI e VCC, GND 5.5 g 0.5 g 10.0 g 5.0 mA VI e VIL, VIH VO e VCC, GND Symbol TA e 25§ C Typ 4.5 VOL Maximum Low Level Output Voltage 4.5 5.5 0.001 0.001 Conditions Guaranteed Limits *VIN e VIL or VIH b 24 mA IOH b 24 mA IOUT e 50 mA *VIN e VIL or VIH IOL 24 mA 24 mA IIN Maximum Input Leakage Current IOZ Maximum TRI-STATE Current ICCT Maximum ICC/Input 5.5 1.6 1.5 mA IOLD ² Minimum Dynamic 5.5 50 75 mA VI e VCC b2.1V VOLD e 1.65V Max IOHD Output Current 5.5 b 50 b 75 mA VOHD e 3.85V Min ICC Maximum Quiescent Supply Current 5.5 160 80 mA VIN e VCC or GND 0.6 8.0 *All outputs loaded; thresholds on input associated with output under test. ² Maximum test duration 2.0 ms, one output loaded at a time. Note: ICC limit for 54ACT @ 25§ C is identical to 74ACT @ 25§ C. 3 AC Electrical Characteristics Symbol VCC* (V) Parameter 74ACT 54ACT 74ACT TA e a 25§ C CL e 50pF TA e b55§ C to a 125§ C CL e 50 pF TA e b40§ C to a 85§ C CL e 50 pF Min Typ 5.0 120 158 Propagation Delay CP to On 5.0 1.5 5.5 9.5 1.5 12.0 1.5 10.5 ns tPHL Propagation Delay CP to On 5.0 2.0 5.5 9.5 1.5 12.0 1.5 10.5 ns tPHL Propagation Delay CLR to On 5.0 2.5 8.0 13.5 1.5 18.0 2.0 15.5 ns tPZH Output Enable Time OE to On 1.5 6.0 10.5 1.5 11.5 1.5 11.5 ns tPZL Output Enable Time OE to On 5.0 2.0 6.5 11.0 1.5 12.0 1.5 12.0 ns tPHZ Output Disable Time OE to On 5.0 1.5 6.5 11.0 1.5 13.5 1.5 12.0 ns tPLZ Output Disable Time OE to On 5.0 1.5 6.0 10.5 1.5 12.0 1.5 11.5 ns fmax Maximum Clock Frequency tPLH 5.0 Max Min Max 95 Min Units Max 109 MHz *Voltage Range 5.0 is 5.0V g 0.5V AC Operating Requirements 74ACT 54ACT 74ACT TA e a 25§ C CL e 50 pF TA e b55§ C to a 125§ C CL e 50 pF TA e b40§ C to a 85§ C CL e 50 pF Parameter VCC* (V) ts Setup Time, HIGH or LOW D to CP 5.0 0.5 2.5 4.0 2.5 ns th Hold Time, HIGH or LOW Dn to CP 5.0 0 2.5 3.0 2.5 ns ts Setup Time, HIGH or LOW EN to CP 5.0 0 2.0 4.0 2.5 ns th Hold Time, HIGH or LOW EN to CP 5.0 0 1.0 3.0 1.0 ns tw CP Pulse Width HIGH or LOW 5.0 2.5 4.5 6.0 5.5 ns tw CLR Pulse Width, LOW 5.0 3.0 5.5 7.0 5.5 ns trec CLR to CP Recovery Time 5.0 1.5 3.5 4.5 4.0 ns Symbol Typ Guaranteed Minimum *Voltage Range 5.0 is 5.0V g 0.5V Capacitance Symbol Units Parameter Typ Units Conditions CIN Input Capacitance 4.5 pF VCC e OPEN CPD Power Dissipation Capacitance 44 pF VCC e 5.0V 4 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74ACT 823 P Temperature Range Family 74ACT e Commercial TTL-Compatible 54ACT e Military TTL-Compatible C QR Special Variations X e Devices shipped in 13× reels QR e Commercial grade device with burn-in QB e Military grade device with environmental and burn-in processing shipped in tubes Device Type Package Code SP e Slim Plastic DIP SD e Slim Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline (SOIC) Temperature Range C e Commercial (b40§ C to a 85§ C) M e Military (b55§ C to a 125§ C) Physical Dimensions inches (millimeters) 28 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 5 Physical Dimensions inches (millimeters) (Continued) 24 Lead Slim (0.300× Wide) Ceramic Dual-In-Line (SD) NS Package Number J24F 24 Lead Small Outline Integrated Circuit (S) NS Package Number M24B 6 Physical Dimensions inches (millimeters) (Continued) 24 Lead Slim (0.300× Wide) Plastic Dual-In-Line (SP) NS Package Number N24C 7 54ACT/74ACT823 9-Bit D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Lit. Ý 114635 24 Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. 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