UTRON UT61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 REVISION HISTORY REVISION Preliminary Rev. 0.1 Preliminary Rev.1.0 Preliminary Rev.1.1 Rev.1.2 DESCRIPTION Original. 1.Add test condition for ISB. 2.Add note to Vcc for access time=10ns. 1.Revised access time : 10/12/15 ns 8ns (max.) for Vcc=3.15V~3.6V 10ns (max.) for Vcc=3.0V~3.6V 2.Add CMOS low power operating : Operating current : 260/220mA (Icc max.) Standby current : 10/2mA(max.) 3.Add Data retention characteristics 4.Revised Terminal Voltage with Respect to Vss(VTERM) : -0.5 to VCC+0.5 -0.5 to 4.6 5.Revised Input high voltage (VIH): 2.2(min)/Vcc+0.5(max) 2.0(min)/Vcc+0.3(max) 1. Revised Standby current : 10/2mA(max) 0.5mA(typ.) 2. Delete ICC1, ICC2 3. Revised ISB : 30mA 3mA, ISB1:10mA 2mA, 4. Add ISB & ISB1 (typ.) : 1mA & 2mA 5. Add Overshoot : VIH ≤ +6.0V for t ≤ tRC /2. Undershoot : VIL ≤ -2.0V for t ≤ tRC /2. 6. Revised Data retention IDR (max) : 3mA 1mA 7. Add order information for lead free product UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 Draft Date Jun 5, 2001 Jun 23,2001 Sep 06,2002 May 20,2003 P80061 UTRON UT61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 FEATURES GENERAL DESCRIPTION The UT61L5128 is a 4,194,304-bit high-speed CMOS static random access memory organized as 524,288 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. Fast access time : 8ns (max.) for Vcc=3.15V~3.6V 10/12ns (max.) for Vcc=3.0V~3.6V CMOS Low operating power Operating current : 260/240/220 mA (Icc max.) Standby current : 0.5 mA (typ.) Single 3.0V~3.6V power supply Operating temperature : Commercial : 0℃~70℃ All TTL compatible inputs and outputs Fully static operation Three state outputs Data retention voltage : 2V (min.) Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16) Package : 44-pin 400mil TSOP-II The UT61L5128 is designed for high-speed system applications. It is particularly suited for use in high-density high-speed system applications. The UT61L5128 operates from a single 3.0V~3.6V power supply and all inputs and outputs are fully TTL compatible. PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K X 8 MEMORY ARRAY Vcc Vss I/O DATA CIRCUIT I/O1-I/O8 COLUMN I/O CE OE CONTROL CIRCUIT WE PIN DESCRIPTION SYMBOL A0 - A18 I/O1 - I/O8 CE DESCRIPTION Address Inputs Data Inputs/Outputs Chip enable Inputs WE Write Enable Input OE VCC VSS NC Output Enable Input Power Supply Ground No Connection NC 1 44 NC NC A0 2 3 43 42 NC NC A1 4 41 A18 A2 40 A3 5 6 A17 A16 39 A4 7 8 38 37 A15 CE I/O1 9 36 I/O8 I/O2 10 11 35 I/O7 Vcc 34 Vss 12 Vss Vcc I/O3 I/O4 WE A5 UT61L5128 13 33 32 I/O6 14 31 I/O5 15 30 A14 29 A13 A6 16 17 A7 18 28 27 A12 A11 A8 19 20 26 A10 A9 25 NC NC 21 NC 22 24 23 NC NC TSOP-II UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 OE P80061 UTRON UT61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to Vss Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 0 to 70 -65 to 150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write OE X H L X CE H L L L I/O OPERATION High - Z High - Z DOUT DIN WE X H H L SUPPLY CURRENT ISB,ISB1 ICC ICC ICC Note: H = VIH, L=VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS (TA = 0℃ to 70℃) PARAMETER SYMBOL TEST CONDITION Power Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Vcc *1 VIH *2 VIL ILI ILO VOH VOL Operating Power Supply Current ICC Standby Current (TTL) ISB Standby Current (CMOS) ISB1 VSS ≦VIN ≦VCC VSS ≦VI/O ≦VCC; Output Disabled IOH= -4mA IOL= 8mA -8 Cycle time=min, 100%duty, -10 I/O=0mA, CE =VIL -12 CE =VIH, other pins =VIL or VIH CE =VCC-0.2V, other pins at 0.2V or Vcc-0.2V MIN. 3.0 2.0 -0.3 -1 -1 2.4 - TYP. MAX. UNIT - 3.3 3.6 VCC+0.3 0.8 1 1 0.4 260 240 220 1 3 V V V µA µA V V mA mA mA mA - 0.5 mA 2 Notes: 1. Overshoot : Vcc+3.0v for pulse width less than 6ns. 2. Undershoot : Vss-3.0v for pulse width less than 6ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80061 UTRON UT61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX. 8 10 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 3ns 1.5V CL=30pF, IOH/IOL=-4mA/8mA AC ELECTRICAL CHARACTERISTICS (TA = 0℃ to 70℃) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYMBOL tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH UT61L5128-8 3.15V~3.6V UT61L5128-10 3.0V~3.6V UT61L5128-12 3.0V~3.6V MIN. MAX. MIN. MAX. MIN. MAX. 8 3 0 3 8 8 4 4 4 - 10 3 0 3 10 8 5 5 5 - 12 3 0 3 12 8 6 6 6 - UNIT ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER SYMBOL UT61L5128-8 3.15V~3.6V MIN. Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* 8 7 7 0 7 0 5.5 0 3 - MAX. 4 UT61L5128-10 3.0V~3.6V MIN. 10 8 8 0 8 0 6 0 3 - MAX. 5 UT61L5128-12 3.0V~3.6V MIN. 12 9 9 0 9 0 7 0 0 - 6 *These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 UNIT MAX. P80061 ns ns ns ns ns ns ns ns ns ns UTRON UT61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2,4) tRC Address tAA t OH tOH Dout Data Valid READ CYCLE 2 ( CE , and OE Controlled) (1,3,5,6) t RC Address t AA t ACE CE t CHZ t CLZ t OHZ OE t OE t OH t OLZ Dout HIGH-Z Data Valid HIGH-Z Notes : 1. WE is HIGH for a read cycle. 2. Device is continuously selected CE =VIL . 3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter. 4. OE is low. 5. tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured ±500mV from steady state. 6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80061 UTRON UT61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) tWC Address tAW CE tCW tAS tWP tWR WE tWHZ Dout tOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 ( CE Controlled) (1,2,5) t WC Address t AW t AS CE t CW t WR t WP WE t WHZ High-Z Dout t DW Din t DH Data Valid Notes : 1. WE or CE must be HIGH during all address transitions. 2. A write occurs during the overlap of a low CE , and a low WE . 3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the I/O drivers to turn off and data to be placed on the bus. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high Impedance state. 6. tOW and tWHZ are specified with CL=5pF. Transition is measured ±500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80061 UTRON UT61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 DATA RETENTION CHARACTERISTICS (TA = 0℃ to +70℃) PARAMETER SYMBOL TEST CONDITION Vcc for Data Retention VDR CE ≧VCC-0.2V , Vcc=2V Data Retention Current IDR CE ≧VCC-0.2V , Chip Disable to Data See Data Retention Waveforms (below) tCDR Retention Time Recovery Time tR MIN. MAX. UNIT 2.0 3.6 V - 1 mA 0 - ms 5 - ms DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) ( CE controlled) VDR ≧ 2V VCC Vcc(min.) Vcc(min.) tCDR CE VIH tR CE ≧ VCC-0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 VIH P80061 UTRON UT61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 PACKAGE OUTLINE DIMENSION θ 44-pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L 2D y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.00 1.20 0.05 0.15 0.95 1.00 1.05 0.30 0.35 0.45 0.12 0.21 18.313 18.415 18.517 11.854 11.836 11.838 10.058 10.180 10.282 0.800 0.40 0.50 0.60 0.805 0.00 0.076 o o 0 5 DIMENSIONS IN INCHS MIN. NOM. MAX. 0.039 0.047 0.002 0.006 0.037 0.039 0.041 0.012 0.014 0.018 0.0047 0.083 0.721 0.725 0.728 0.460 0.466 0.470 0.398 0.400 0.404 0.0315 0.0157 0.020 0.0236 0.0317 0.000 0.003 o o 0 5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80061 UTRON Rev. 1.2 UT61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM ORDERING INFORMATION PART NO. UT61L5128MC-8 UT61L5128MC-10 UT61L5128MC-12 ACCESS TIME (ns) 8 10 12 PACKAGE 44 PIN TSOP-II 44 PIN TSOP-II 44 PIN TSOP-II ORDERING INFORMATION (for lead free product) PART NO. UT61L5128MCL-8 UT61L5128MCL-10 UT61L5128MCL-12 ACCESS TIME (ns) 8 10 12 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 PACKAGE 44 PIN TSOP-II 44 PIN TSOP-II 44 PIN TSOP-II P80061 UTRON Rev. 1.2 UT61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM This page is left blank intentionally. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80061