ETC VMC100LVE111FN

MC100LVE111
3.3VECL 1:9 Differential
Clock Driver
The MC100LVE111 is a low skew 1-to-9 differential driver, designed
with clock distribution in mind. The MC100LVE111’s function and
performance are similar to the popular MC100E111, with the added
feature of low voltage operation. It accepts one signal input, which can be
either differential or single-ended if the VBB output is used. The signal is
fanned out to 9 identical differential outputs.
The LVE111 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize gate
to gate skew within a device, and empirical modeling is used to determine
process control limits that ensure consistent tpd distributions from lot to
lot. The net result is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50 Ω, even if only
one side is being used. In most applications, all nine differential pairs will
be used and therefore terminated. In the case where fewer than nine pairs
are used, it is necessary to terminate at least the output pairs on the same
package side as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of
propagation delay (on the order of 10–20 ps) of the output(s) being used
which, while not being catastrophic to most designs, will mean a loss of
skew margin.
The MC100LVE111, as with most other ECL devices, can be operated
from a positive VCC supply in PECL mode. This allows the LVE111 to
be used for high performance clock distribution in +3.3 V systems.
Designers can take advantage of the LVE111’s performance to distribute
low skew clocks across the backplane or the board. In a PECL
environment, series or Thevenin line terminations are typically used as
they require no additional power supplies. For systems incorporating
GTL, parallel termination offers the lowest power by taking advantage of
the 1.2 V supply as a terminating voltage. For more information on using
PECL, designers should refer to Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to VBB as a switching reference voltage. VBB may
also rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, VBB should be left open.
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MARKING
DIAGRAM*
MC100LVE111
AWLYYWW
PLCC–28
FN SUFFIX
CASE 776
A
WL
YY
WW
28 1
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100LVE111FN
PLCC–28
37 Units/Rail
MC100LVE111FNR2
PLCC–28
500 Units/Reel
200 ps Part-to-Part Skew
50 ps Output-to-Output Skew
ESD Protection: >2 KV HBM, >200 V MM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC= 0 V with VEE = –3.0 V to –3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 250 devices
 Semiconductor Components Industries, LLC, 2001
January, 2001 – Rev. 3
1
Publication Order Number:
MC100LVE111/D
MC100LVE111
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Q0
Q0
Q1 VCCO Q1
Q2
Q2
25
24
23
20
19
LOGIC SYMBOL
22
21
Q0
VEE
26
18
Q3
NC
27
17
Q3
IN
28
16
Q4
15
VCCO
VCC
28-Lead PLCC
(Top View)
1
IN
2
14
Q4
VBB
3
13
Q5
NC
4
12
Q5
5
6
7
8
9
Q8
Q8
Q7 VCCO Q7
10
11
Q6
Q6
Q0
Q1
Q1
Q2
Q2
Q3
Q3
IN
Q4
IN
Q4
Q5
Q5
Q6
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Q6
Q7
PIN DESCRIPTION
PIN
FUNCTION
IN, IN
Q0, Q0–Q8, Q8
VBB
VCC, VCCO
VEE
NC
ECL Differential Input Pair
ECL Differential Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Q7
Q8
Q8
VBB
MAXIMUM RATINGS (Note 1.)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
–8 to 0
V
VI
PECL Mode Input Voltage
VEE = 0 V
VI VCC
6 to 0
V
NECL Mode Input Voltage
VCC = 0 V
VI VEE
–6 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
–40 to +85
°C
Tstg
Storage Temperature Range
–65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
28 PLCC
22 to 26 ± 5%
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
1. Maximum Ratings are those values beyond which device damage may occur.
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2
MC100LVE111
LVPECL DC CHARACTERISTICS VCC= 3.3 V; VEE= 0.0 V (Note 1.)
–40°C
Symbol
Characteristic
Min
25°C
Typ
Max
55
66
Min
85°C
Typ
Max
55
66
Min
Typ
Max
Unit
65
78
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2.)
2215
2345
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 2.)
1490
1595
1680
1490
1595
1680
1490
1595
1680
mV
VIH
Input HIGH Voltage (Single Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single Ended)
1490
1825
1490
1825
1490
1825
mV
VBB
Output Voltage Reference
1.92
2.04
1.92
2.04
1.92
2.04
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3.)
1.8
2.9
1.8
2.9
1.8
2.9
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
0.5
150
0.5
µA
0.5
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device
still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than
or equal to VPP(min).
LVNECL DC CHARACTERISTICS VCC= 0.0 V; VEE= –3.3 V (Note 1.)
–40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
55
66
55
66
65
78
mA
VOH
Output HIGH Voltage (Note 2.)
–1085
–955
–880
–1025
–955
–880
–1025
–955
–880
mV
VOL
Output LOW Voltage (Note 2.)
–1810
–1705
–1620
–1810
–1705
–1620
–1810
–1705
–1620
mV
VIH
Input HIGH Voltage (Single Ended)
–1165
–880
–1165
–880
–1165
–880
mV
VIL
Input LOW Voltage (Single Ended)
–1810
–1475
–1810
–1475
–1810
–1475
mV
VBB
Output Voltage Reference
–1.38
–1.26
–1.38
–1.26
–1.38
–1.26
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3.)
–1.5
–0.4
–1.5
–0.4
–1.5
–0.4
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
0.5
150
0.5
0.5
µA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device
still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than
or equal to VPP(min).
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3
MC100LVE111
AC CHARACTERISTICS VCC= 3.3 V; VEE= 0.0 V or VCC= 0.0 V; VEE= –3.3 V (Note 1.)
–40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
TBD
Typ
85°C
Max
fmax
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay to Output
IN (differential) (Note 2.)
IN (single-ended) (Note 3.)
tskew
Within-Device Skew (Note 4.)
Part-to-Part Skew (Diff)
tJITTER
Cycle–to–Cycle Jitter
VPP
Input Swing (Note 5.)
500
1000
500
1000
tr/tf
Output Rise/Fall Time (20%–80%)
200
600
200
600
Min
TBD
Typ
Max
TBD
Unit
GHz
ps
400
350
650
700
440
390
630
680
50
250
445
395
635
685
50
200
TBD
50
200
ps
500
1000
mV
200
600
ps
TBD
TBD
ps
1. VEE can vary ±0.3 V.
2. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
3. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
5. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the E111 as a differential input as low as 50 mV will still produce full ECL levels at the output.
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC – 2.0 V
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
–
ECLinPS Circuit Performance at Non–Standard VIH Levels
AN1405
–
ECL Clock Distribution Techniques
AN1406
–
Designing with PECL (ECL at +5.0 V)
AN1503
–
ECLinPS I/O SPICE Modeling Kit
AN1504
–
Metastability and the ECLinPS Family
AN1560
–
Low Voltage ECLinPS SPICE Modeling Kit
AN1568
–
Interfacing Between LVDS and ECL
AN1596
–
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
–
Using Wire–OR Ties in ECLinPS Designs
AN1672
–
The ECL Translator Guide
AND8001
–
Odd Number Counters Design
AND8002
–
Marking and Date Codes
AND8020
–
Termination of ECL Logic Devices
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MC100LVE111
PACKAGE DIMENSIONS
PLCC–28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE E
0.007 (0.180)
B
Y BRK
–N–
M
T L-M
0.007 (0.180)
U
M
N
S
T L-M
S
S
N
S
D
Z
–M–
–L–
W
28
D
X
0.010 (0.250)
G1
T L-M
S
N
S
S
V
1
VIEW D–D
A
0.007 (0.180)
R
0.007 (0.180)
Z
C
M
M
T L-M
T L-M
S
S
N
N
S
0.007 (0.180)
H
0.010 (0.250)
S
–T–
T L-M
S
N
S
K
SEATING
PLANE
F
VIEW S
G1
N
S
K1
0.004 (0.100)
J
T L-M
S
E
G
M
S
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2
10
0.410
0.430
0.040
---
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MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2
10
10.42
10.92
1.02
---
0.007 (0.180)
M
T L-M
S
N
S
MC100LVE111
Notes
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MC100LVE111
Notes
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MC100LVE111
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MC100LVE111/D