ETC XCR3256XLSERIES

0
R
XCR3256XL 256 Macrocell CPLD
DS013 (v1.9) January 8, 2002
0
14
Preliminary Product Specification
Features
Description
•
Lowest power 256 macrocell CPLD
•
7.5 ns pin-to-pin logic delays
•
System frequencies up to 140 MHz
•
256 macrocells with 6,000 usable gates
The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at
power sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide
6,000 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 140 MHz.
•
Available in small footprint packages
- 144-pin TQFP (120 user I/O pins)
- 208-pin PQFP (164 user I/O)
- 256-ball FBGA (164 user I/O)
- 280-ball CS BGA (164 user I/O)
TotalCMOS Design Technique for Fast
Zero Power
Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
•
Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 clocks available per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
•
Fast ISP programming times
•
•
Port Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial grade voltage
range
•
Programmable slew rate control per output
•
•
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
140
120
Typical ICC (mA)
•
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the ICC vs. Frequency of our
XCR3256XL TotalCMOS CPLD (data taken with 16
resetable up/down, 16-bit counters at 3.3V, 25°C).
100
80
60
40
20
0
0
20
40
60
80
100
120
140 160
Frequency (MHz)
DS013_01_102401
Figure 1: XCR3256XL Typical ICC vs. Frequency at
VCC = 3.3V, 25°C
Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C
Frequency (MHz)
0
1
10
20
40
60
80
100
120
140
Typical ICC (mA)
0.02
0.91
8.87
17.7
34.8
51.5
68
84.2
100.1
116.6
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
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1-800-255-7778
1
R
XCR3256XL 256 Macrocell CPLD
DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
2.4
-
V
-
0.4
V
VOH(2)
Output High voltage
IOH = –8 mA
VOL
Output Low voltage for 3.3V outputs
IOL = 8 mA
IIL
Input leakage current
VIN = GND or VCC
–10
10
µA
IIH
I/O High-Z leakage current
VIN = GND or VCC
–10
10
µA
ICCSB
Standby current
VCC = 3.6V
-
100
µA
ICC
Dynamic current(3,4)
f = 1 MHz
-
2
mA
f = 50 MHz
-
60
mA
CIN
Input pin capacitance(5)
f = 1 MHz
-
8
pF
CCLK
Clock input capacitance(5)
f = 1 MHz
5
12
pF
CI/O
I/O pin capacitance (5)
f = 1 MHz
-
10
pF
Notes:
1. See XPLA3 family data sheet (DS012) for recommended operating conditions.
2. See Figure 2 for output drive characteristics of the XPLA3 family.
3. See Table 1, Figure 1 for typical values.
4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing.
5. Typical values, not tested.
100
90
IOL (3.3V)
80
70
mA
60
50
IOH (3.3V)
40
30
IOH (2.7V)
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Volts
DS012_10_041901
Figure 2: Typical I/V Curve for the XPLA3 Family
2
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DS013 (v1.9) January 8, 2002
Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions(1,2)
-7
Symbol
Parameter
-10
-12
Min.
Max.
Min.
Max.
Min.
Max.
Unit
TPD1
Propagation delay time (single p-term)
-
7.0
-
9.0
-
10.8
ns
TPD2
Propagation delay time (OR array)(3)
-
7.5
-
10.0
-
12.0
ns
TCO
Clock to output (global synchronous pin clock)
-
4.5
-
5.8
-
6.9
ns
Setup time (fast input register)
2.5
-
3.0
-
3.0
-
ns
Setup time (single p-term)
4.3
-
5.5
-
6.7
-
ns
Setup time (OR array)
4.8
-
6.5
-
7.9
-
ns
0
-
0
-
0
-
ns
TSUF
TSU1
(4)
TSU2
TH(4)
Hold time
TWLH
(4)
Global Clock pulse width (High or Low)
3.0
-
4.0
-
5.0
-
ns
(4)
P-term clock pulse width
4.5
-
6.0
-
7.5
-
ns
Input rise time
-
20
-
20
-
20
ns
Input fall time
-
20
-
20
-
20
ns
TtPLH
TR(4)
TL(4)
fSYSTEM
(4)
-
140
-
105
-
88
MHz
time(5)
-
120
-
120
-
120
µs
TINIT(4)
ISP initialization time
-
120
-
120
-
120
µs
TPOE(4)
P-term OE to output enabled
-
9.0
-
11.0
-
13.0
ns
-
9.0
-
11.0
-
13.0
ns
TCONFIG
(4)
Maximum system frequency
Configuration
TPOD
(4)
P-term OE to output
TPCO
(4)
P-term clock to output
-
8.0
-
10.3
-
12.4
ns
P-term set/reset to output valid
-
9.0
-
11.0
-
13.0
ns
TPAO (4)
disabled(6)
Notes:
1. Specifications measured with one output switching.
2. See XPLA3 family data sheet (DS012) for recommended operating conditions.
3. See Figure 4 for derating.
4. These parameters guaranteed by design and/or characterization, not testing.
5. Typical current draw during configuration is 10 mA at 3.6V.
6. Output CL = 5 pF.
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
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R
XCR3256XL 256 Macrocell CPLD
Internal Timing Parameters(1,2)
-7
Symbol
Parameter
-10
-12
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Buffer Delays
TIN
Input buffer delay
-
2.5
-
3.3
-
4.0
ns
TFIN
Fast input buffer delay
-
2.2
-
2.8
-
3.3
ns
TGCK
Global clock buffer delay
-
1.0
-
1.3
-
1.5
ns
TOUT
Output buffer delay
-
2.5
-
2.8
-
3.3
ns
TEN
Output buffer enable/disable delay
-
4.5
-
5.2
-
6.0
ns
-
1.3
-
1.6
-
2.0
ns
Internal Register and Combinatorial Delays
TLDI
Latch transparent delay
TSUI
Register setup time
0.8
-
1.0
-
1.2
-
ns
THI
Register hold time
0.3
-
0.5
-
0.7
-
ns
TECSU
Register clock enable setup time
2.0
-
2.5
-
3.0
-
ns
TECHO
Register clock enable hold time
3.0
-
4.5
-
5.5
-
ns
TCOI
Register clock to output delay
-
1.0
-
1.3
-
1.6
ns
TAOI
Register async. S/R to output delay
-
2.0
-
2.0
-
2.2
ns
TRAI
Register async. recovery
-
5.0
-
7.0
-
8.0
ns
TLOGI1
Internal logic delay (single p-term)
-
2.0
-
2.5
-
3.0
ns
TLOGI2
Internal logic delay (PLA OR term)
-
2.5
-
3.5
-
4.2
ns
-
2.8
-
3.7
-
4.4
ns
Feedback Delays
TF
ZIA delay
Time Adders
TLOGI3
Fold-back NAND delay
-
6.0
-
8.0
-
9.5
ns
TUDA
Universal delay
-
2.0
-
2.5
-
3.0
ns
TSLEW
Slew rate limited delay
-
4.0
-
5.0
-
6.0
ns
Notes:
1. These parameters guaranteed by design and/or characterization, not testing.
2. See XPLA3 family data sheet (DS012) for the timing model.
4
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1-800-255-7778
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
Switching Characteristics
VCC
S1
Component
R1
R2
C1
R1
Values
390Ω
390Ω
35 pF
VIN
VOUT
R2
Measurement
TPOE (High)
TPOE (Low)
TP
C1
S1
Open
Closed
Closed
S2
Closed
Open
Closed
Note: For TPOD, C1 = 5 pF. Delay measured at
output level of VOL + 300 mV, VOH – 300 mV.
S2
DS013_03_102401
(ns)
Figure 3: AC Load Circuit
7.5
7.4
7.3
7.2
7.1
7.0
6.9
6.8
6.7
6.6
6.5
6.4
6.3
+3.0V
90%
10%
0V
TR
1.5 ns
1
2
4
8
16
Number of Adjacent Outputs Switching
TL
1.5 ns
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
DS017_05_042800
DS013_04_042800
Figure 5: Voltage Waveform
Figure 4: Derating Curve for TPD2
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
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1-800-255-7778
5
R
XCR3256XL 256 Macrocell CPLD
Pin Descriptions
Table 3: XCR3256XL I/O Pins (Continued)
Function MacroBlock
cell
TQ144 PQ208
Table 2: XCR3256XL User I/O Pins
Total User I/O Pins
CS280
TQ144
PQ208
FT256
CS280
3
1
98
17
G15
H17
120
164
164
164
3
2
97
18
G13
H18
3
3
96
19
F16
H19
3
4
94
20
G14
J16
Table 3: XCR3256XL I/O Pins
Function MacroBlock
cell
TQ144 PQ208
6
FT256
FT256
CS280
3
5
93
21
G16
J17
1
1
106
6
C16
E18
3
6
-
-
-
-
1
2
-
7
F12
E19
3
7
-
-
-
-
1
3
104(1)
8
D16
F15
3
8
-
-
-
-
1
4
103
9
E14
F17
3
9
-
-
-
-
1
5
102
10
E15
F18
3
10
-
-
-
-
1
6
-
-
-
-
3
11
-
-
-
-
1
7
-
-
-
-
3
12
92
22
H13
J18
1
8
-
-
-
-
3
13
-
24
H12
K16
1
9
-
-
-
-
3
14
91
25
H15
K17
1
10
-
-
-
-
3
15
90
26
H14
K18
1
11
-
-
-
-
3
16
-
27
H16
L16
1
12
101
11
F13
F19
4
1
114
197
D11
E14
1
13
100
12
E16
G16
4
2
116
196
A11
D14
1
14
99
13
F14
G17
4
3
117
195
E10
A14
1
15
-
15
F15
G19
4
4
-
194
B12
C13
1
16
-
16
G12
H16
4
5
118
193
C11
B13
2
1
107
4
E13
B19
4
6
-
-
-
-
2
2
108
3
D15
B18
4
7
-
-
-
-
2
3
-
206
C13
B17
4
8
-
-
-
-
2
4
-
205
A14
A18
4
9
-
-
-
-
2
5
109
204
E11
A17
4
10
-
-
-
-
2
6
-
-
-
-
4
11
-
-
-
-
2
7
-
-
-
-
4
12
119
192
B11
A13
2
8
-
-
-
-
4
13
120
190
A10
A12
2
9
-
-
-
-
4
14
121
189(1)
C10(1)
C12(1)
2
10
-
-
-
-
4
15
-
188
A9
B12
2
11
-
-
-
-
4
16
122
187
D9
D12
2
12
110
203
A13
C16
5
1
89(1)
28
J14
L17
2
13
111
202
D12
A16
5
2
-
29
J15
L18
J13(1)
L19(1)
2
14
-
201
B13
E15
5
3
88
30(1)
2
15
112
199
C12
D15
5
4
87
31
J16
M16
2
16
113
198
A12
A15
5
5
86
33
L14
M18
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1-800-255-7778
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
Table 3: XCR3256XL I/O Pins (Continued)
Function MacroBlock
cell
TQ144 PQ208
Table 3: XCR3256XL I/O Pins (Continued)
FT256
CS280
Function MacroBlock
cell
TQ144 PQ208
FT256
CS280
5
6
-
-
-
-
7
11
-
-
-
-
5
7
-
-
-
-
7
12
77
45
M16
R17
5
8
-
-
-
-
7
13
-
46
M14
R15
5
9
-
-
-
-
7
14
75
47
N16
T17
5
10
-
-
-
-
7
15
74
48
L12
T16
5
11
-
-
-
-
7
16
-
49
P15
U19
5
12
84
34
K15
M17
8
1
66
65
T12
T13
5
13
-
35
K14
N16
8
2
67
64
R12
W14
5
14
83
36
K16
N19
8
3
68
62
N11
T14
5
15
82
37
K13
N18
8
4
69
61
T13
R14
5
16
-
38
L15
N17
8
5
-
60
P12
W15
6
1
-
78
R9
U10
8
6
-
-
-
-
6
2
55
77
N9
T10
8
7
-
-
-
-
6
3
56
76
T10
W11
8
8
-
-
-
-
6
4
-
73
P10
U11
8
9
-
-
-
-
6
5
60
71
R10
T11
8
10
-
-
-
-
6
6
-
-
-
-
8
11
-
-
-
-
6
7
-
-
-
-
8
12
70
59
R13
U15
6
8
-
-
-
-
8
13
-
58
M11
V15
6
9
-
-
-
-
8
14
71
57
T14
T15
6
10
-
-
-
-
8
15
-
56
N12
V16
6
11
-
-
-
-
8
16
72
55
R14
W17
6
12
61
70
T11
W12
9
1
2
153
D3
B1
6
13
62
69
N10
U12
9
2
1
154
C1
C3
6
14
63
68
P11
T12
9
3
-
159
B4
A4
6
15
-
67
M10
V13
9
4
-
160
E6
B5
6
16
65
66
R11
U13
9
5
143
161
A4
C5
7
1
81
39
K12
P16
9
6
-
-
-
-
7
2
-
40
L16
P18
9
7
-
-
-
-
7
3
80
42
M15
R19
9
8
-
-
-
-
7
4
79
43
N15
R16
9
9
-
-
-
-
7
5
78
44
L13
R18
9
10
-
-
-
-
7
6
-
-
-
-
9
11
-
-
-
-
7
7
-
-
-
-
9
12
-
162
C5
A5
7
8
-
-
-
-
9
13
142
163
B5
E6
7
9
-
-
-
-
9
14
141
164
D6
D6
7
10
-
-
-
-
9
15
140
166
A5
B6
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
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1-800-255-7778
7
R
XCR3256XL 256 Macrocell CPLD
Table 3: XCR3256XL I/O Pins (Continued)
Function MacroBlock
cell
TQ144 PQ208
8
Table 3: XCR3256XL I/O Pins (Continued)
FT256
CS280
Function MacroBlock
cell
TQ144 PQ208
FT256
CS280
9
16
139
167
C6
A6
12
5
15
136
H4
H3
10
1
4(1)
151
D1
D2
12
6
-
-
-
-
10
2
-
150
E4
D1
12
7
-
-
-
-
10
3
5
149
D2
E3
12
8
-
-
-
-
10
4
6
148
E3
E2
12
9
-
-
-
-
10
5
7
147
E1
E4
12
10
-
-
-
-
10
6
-
-
-
-
12
11
-
-
-
-
10
7
-
-
-
-
12
12
16
135
G2
H2
10
8
-
-
-
-
12
13
-
133
J1
J2
10
9
-
-
-
-
12
14
18
132
J3
J3
10
10
-
-
-
-
12
15
19
131
H2
K2
10
11
-
-
-
-
12
16
-
130
J5
K3
10
12
8
146
F4
E1
13
1
-
79
P9
W10
10
13
-
145
F1
F5
13
2
54
80
T9
T9
10
14
9
144
G5
F3
13
3
53
81
P8
U9
10
15
10
142
E2
F4
13
4
-
84
R8
T8
10
16
11
141
F3
G3
13
5
49
86
N8
T7
11
1
-
168
B6
D7
13
6
-
-
-
-
11
2
-
169
E7
C7
13
7
-
-
-
-
11
3
138
170
A6
B7
13
8
-
-
-
-
11
4
-
171
D7
A7
13
9
-
-
-
-
11
5
137
172
B7
C8
13
10
-
-
-
-
11
6
-
-
-
-
13
11
-
-
-
-
11
7
-
-
-
-
13
12
48
87
T8
W7
11
8
-
-
-
-
13
13
47
88
P7
V7
11
9
-
-
-
-
13
14
46
89
R7
U7
11
10
-
-
-
-
13
15
-
90
P6
W6
11
11
-
-
-
-
13
16
45
91
T7
T6
11
12
136
173
C7
B8
14
1
20(1)
129
J2
K4
11
13
134
175
C8
C9
14
2
-
128
J4
L1
A7(1)
B9(1)
14
3
21
127(1)
K1(1)
L2(1)
11
14
133
176(1)
11
15
132
177
D8
D10
14
4
22
126
K3
L3
11
16
131
178
B8
C10
14
5
23
124
K2
M1
12
1
-
140
F2
G2
14
6
-
-
-
-
12
2
-
139
G4
G1
14
7
-
-
-
-
12
3
12
138
G1
G4
14
8
-
-
-
-
12
4
14
137
H1
H1
14
9
-
-
-
-
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Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
Table 3: XCR3256XL I/O Pins (Continued)
Function MacroBlock
cell
TQ144 PQ208
Table 3: XCR3256XL I/O Pins (Continued)
FT256
CS280
Function MacroBlock
cell
TQ144 PQ208
FT256
CS280
14
10
-
-
-
-
16
15
35
109
N3
V1
14
11
-
-
-
-
16
16
36
108
T1
U2
14
12
25
123
L1
M3
14
13
-
122
K4
M4
14
14
26
121
L3
N1
14
15
27
120
K5
N2
14
16
28
119
M1
N3
15
1
44
92
N7
V6
15
2
43
93
R6
U6
15
3
42
95
M7
R6
15
4
41
96
T5
W5
15
5
40
97
T6
T5
15
6
-
-
-
-
15
7
-
-
-
-
15
8
-
-
-
-
15
9
-
-
-
-
15
10
-
-
-
-
15
11
-
-
-
-
15
12
-
98
R5
V5
15
13
39
99
N6
U5
15
14
38
100
T4
W4
15
15
-
101
P5
U4
15
16
37
102
R4
W3
16
1
-
118
L2
P1
16
2
-
117
M2
P2
16
3
29
115
M3
P4
16
4
30
114
N2
R3
16
5
31
113
L5
R2
16
6
-
-
-
-
16
7
-
-
-
-
16
8
-
-
-
-
16
9
-
-
-
-
16
10
-
-
-
-
16
11
-
-
-
-
16
12
32
112
P1
R4
16
13
-
111
M4
T3
16
14
34
110
R1
U1
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
Notes:
1. JTAG pins.
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R
XCR3256XL 256 Macrocell CPLD
Table 4: XCR3256XL Global, JTAG, Port Enable, Power, and No Connect Pins
Pin Type
TQ144
PQ208
FT256
CS280
IN0 / CLK0
128
181
B9
A10
IN1 / CLK1
127
182
A8
D11
IN2 / CLK2
126
183
C9
C11
IN3 / CLK3
125
184
B10
B11
TCK
89
30
J13
L19
TDI
4
176
A7
B9
TDO
104
189
C10
C12
TMS
20
127
K1
L2
PORT_EN
13(1)
116(1)
N1(1)
P3(1)
Vcc
24, 50, 51, 58, 73, 76,
95, 115, 123, 130, 144
5, 23, 41, 63, 74, 83, 85, E8, E9, F7, F8, F9, F10,
A11, B10, C6, C14,
107, 125, 143, 165,
G6, G11, H5, H6, H11, D13, D17, F2, J19, L4,
179, 186, 191
J6, J11, J12, K6, K11, P15, T18, U8, U14, V2,
L7, L8, L9, L10, M8, M9
V9, V11
GND
3, 17, 33, 52, 57, 59, 64,
85, 105, 124, 129, 135
14, 32, 50, 72, 75, 82,
94, 134, 152, 174, 180,
185, 200
E5, F6, F11, G7, G8,
G9, G10, H7, H8, H9,
H10, J7, J8, J9, J10, K7,
K8, K9, K10, L6, L11
E5, E7, E8, E9, E10,
E11, E12, E13, G5,
G15, H5, H15, J5, J15,
K5, K15, L5, L15, M5,
M15, N5, N15, R7, R8,
R9, R10, R11, R12,
R13
No Connects
-
1, 2, 51, 52, 53, 54, 103,
104, 105, 106, 155,
156, 157, 158, 207, 208
A1, A2, A3, A15, A16,
B1, B2, B3, B14, B15,
B16, C2, C3, C4, C14,
C15, D4, D5, D10, D13,
D14, E12, F5, G3, H3,
L4, M5, M6, M12, M13,
N4, N5, N13, N14, P2,
P3, P4, P13, P14, P16,
R2, R3, R15, R16, T2,
T3, T15, T16
A1, A2, A3, A8, A9,
A19, B2, B3, B4, B14,
B15, B16, C1, C2, C4,
C15, C17, C18, C19,
D3, D4, D5, D8, D9,
D16, D18, D19, E16,
E17, F1, F16, G18, H4,
J1, J4, K1, K19, M2,
M19, N4, P5, P17, P19,
R1, R5, T1, T2, T4, T19,
U3, U16, U17, U18, V3,
V4, V8, V10, V12, V14,
V17, V18, V19, W1,
W2, W8, W9, W13,
W16, W18, W19
Notes:
1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for full
explanation.
10
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DS013 (v1.9) January 8, 2002
Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
Ordering Information
Example:
XCR3256XL -7 PQ 208 C
Device Type
Temperature Range
Number of Pins
Speed Grade
Package Type
Device Ordering Options
Speed
Package
Temperature
-12
12 ns pin-to-pin delay
TQ144
144-pin Thin Quad Flat Pack
C = Commercial
TA = 0°C to + 70°C
VCC = 3.0V to 3.6V
-10
10 ns pin-to-pin delay
PQ208
208-pin Plastic Quad Flat Package
I = Industrial
TA = –40°C to +85°C
VCC = 2.7V to 3.6V
-7
7.5 ns pin-to-pin delay
FT256
256-ball Fine-Pitch Ball Grid Array
CS280
280-ball Chip Scale Package
Component Compatibility
Pins
144
208
256
280
Type
Plastic TQFP
Plastic PQFP
Plastic FBGA
Plastic BGA
Code
TQ144
PQ208
FT256
CS280
-7
C
C
C
C
-10
C, I
C, I
C, I
C, I
-12
C, I
C, I
C, I
C, I
XCR3256XL
Revision History
The following table shows the revision history for this document
Date
Version
Revision
01/21/00
1.0
Initial Xilinx release.
02/10/00
1.1
Updated Pinout table.
05/03/00
1.2
Minor updates and added Boundary Scan to pinout table.
11/20/00
1.3
Updated pinout tables; corrected note in Table 4 to read: "port enable pin is brought High".
12/11/00
1.4
Updated specifications and pinout tables.
01/17/01
1.5
Removed Timing Model.
03/05/01
1.6
Added 256-ball Fine-Pitch Ball Grid Array Package.
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
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R
XCR3256XL 256 Macrocell CPLD
12
Date
Version
Revision
04/11/01
1.7
Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed VOH spec.
04/19/01
1.8
Updated Typical I/V curve, Figure 2: added voltage levels.
01/08/02
1.9
Moved ICC vs Freq. Figure 1 and Table 1 to page 1. Added single p-term setup time (TSU1)
to AC Table, renamed TSU to TSU2 for setup time through the OR array. Updated TSUF spec
to match software timing. Added TINIT spec. Updated TCONFIG spec. Updated THI spec to
correct a typo. Updated AC Load Circuit diagram to more closely resemble true test
conditions, added note for TPOD delay measurement.
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DS013 (v1.9) January 8, 2002
Preliminary Product Specification