XG571C APPROVED PRODUCT SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Product Features • • • • • • • • • • • • • • • • • • Frequency Table Supports Pentiumâ and PentiumâPro and Mobil Pentiumâ Processor designs. 4 CPU clocks up to 8 loads. Up to 8 SDRAM clocks for 2 DIMMs. Supports Power Management. 7 PCI synchronous clocks. Optional common or mixed supply mode: (Vdd = Vddq3 = Vddq2 = 3.3V) or (Vdd = Vddq3 = 3.3V, Vddq2 = 2.5V) < 250ps skew CPU and SDRAM clocks. < 250ps skew among PCI clocks. SMBUS 2-Wire serial interface Programmable registers featuring: enable/disable each output pin mode as tri-state, test, or normal 24/48 MHz selections 1 IOAPIC clock for multiprocessor support. 48-pin SSOP and TSSOP package Spread Spectrum Technology for up to 13dB of EMI reduction Block Diagram Buffers Xin Xout REF OSC 3 REF0,1,2 Vddq2 IOAPIC0 Buffer Vddq2 SDATA SDCLK 4 CPUCLK0~3 Buffers Vddq3 SEL PLL1 dly 8 Buffers 6 SDRAM0~7 PCICLK0~5 Buffers PCI_STOP# CPU_STOP# PWR_DWN# MODE PCICLK_F Buffer Buffer 48/24MHZ PLL2 Buffer 48/24MHZ Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com SEL CPU PCI 0 60.0 30.0 1 66.6* *Spread Spectrum mode capable 33.3* Pin Configuration XG571 REF1 1 48 Vdd REF0 2 47 REF2 Vss 3 46 Vddq2 Xin 4 45 IOAPIC0 PW R_DW N# Xout 5 44 MODE 6 43 Vss Vddq3 7 42 CPUCLK0 PCICLK_F 8 41 CPUCLK1 PCICLK0 9 40 Vddq2 Vss 10 39 CPUCLK2 PCICLK1 11 38 CPUCLK3 PCICLK2 12 37 Vss PCICLK3 13 36 SDRAM0 PCICLK4 14 35 SDRAM 1 Vddq3 15 34 Vddq3 PCICLK5 16 33 SDRAM 2 Vss 17 32 SDRAM 3 SEL 18 31 Vss SDRAM 4 SDATA 19 30 SDCLK 20 29 SDRAM 5 Vddq3 21 28 Vddq3 48/24MHZ 22 27 SDRAM6/CPU_STOP# 48/24MHZ 23 26 SDRAM7/PCI_STOP# Vss 24 25 Vdd Document#: 38-07019 Rev. ** 5/17/2001 Page 1 of 17 APPROVED PRODUCT XG571C SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Pin Description Xin, Xout - These pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal (nominally 14.318 MHz). Xin may also serve as input for an externally generated reference signal. PCICLK_F - A PCI clock output that does not stop until in power down mode. It is synchronous with other PCI clocks. SEL - Standard frequency select input. It has internal pull-up. IOAPIC0 - Buffered output of 14.3MHZ multiprocessor support. It is powered by Vddq2. CPUCLK(0:3) - Low skew (<250 pS) clock outputs for host frequencies such as CPU, Chipset, Cache. Vddq2 is the supply voltage for these outputs. PWR_DWN# - Power down pin. When this pin is asserted low, the IC is in shutdown mode where all circuitry is turned off including VCO, crystal buffer and PCICLK_F. It has an internal pull-up. The SMBUS interface is disabled with the PWR_DWN# pin is low. SDRAM(0:5) - Synchronous DRAM DIMs clocks. They are powered by Vddq3. SDRAM6/CPU_STOP# - If MODE=1, this pin is a Synchronous DRAM DIMs clock output powered by Vddq3. If MODE=0, this pin is a CPU_STOP# input signal, where a low level stops the CPU however, the SDRAM clocks will stay active. It has an internal pullup. SDRAM7/PCI_STOP# - If MODE=1, this pin is a Synchronous DRAM DIMs clock output powered by Vddq3. If MODE=0, this pin is a PCI_STOP# input signal, where a low level stops the PCI clocks. It has an internal pull-up. MODE - A low level on this pin causes pins 26, and 27 to be power management inputs PCI_STOP#, and CPU_STOP# respectively. A high level on this pin causes pins 26, and 27 to be clock output signals SDRAM7, and SDRAM6 respectively. It has an internal pull-up resistor. REF(0:2) - Buffered outputs of on-chip reference. 48/24MHz(0:1) - Programmable 48 MHZ or 24 MHZ clock outputs. SDATA - serial data of SMBUS 2-wire control interface. Has internal pull-up resistor. SDCLK - serial clock of SMBUS 2-wire control interface. Has internal pull-up resistor. Vss - Ground pins for the chip. Vdd - 3.3 Volt power supply pins for analog circuit and core logic. Vddq3 - Power supply pins for 3.3V IO pins. Vddq2 - Power supply pins for 2.5V/3.3V IO pins. PCICLK(0:5) - Low skew (<250pS) clock outputs for PCI frequencies. These buffers voltage level is controlled by Vddq3 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com for Document#: 38-07019 Rev. ** 5/17/2001 Page 2 of 17 XG571C APPROVED PRODUCT SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Power Management Functions All clocks can be individually enabled or stopped via the 2-wire control interface. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running when the chip was not powered down. On power up, the VCOs will stabilize to the correct pulse widths within about 0.2 mS. The CPU, SDRAM, and PCI clocks transition between running and stopped by waiting for one positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. When MODE=0, pins 26 and 27 are inputs PCI_STOP# and CPU_STOP# respectively (when MODE=1, these functions are not available). A particular output is enabled only when both the serial interface and these pins indicate that it should be enabled. The IMIXG571 clocks may be disabled according to the following table in order to reduce power consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped. On low to high transitions of PWR_DWN#, external circuitry should allow 0.2 mS for the VCOs to stabilize prior to assuming the clock periods are correct. The CPU and PCI clocks transition between running and stopped by waiting for one positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CPU_STOP# X 0 0 1 1 PCI_STOP# X 0 1 0 1 PWR_DWN# 0 1 1 1 1 CPUCLK LOW LOW LOW 66/60 MHZ 66/60 MHZ PCICLK LOW LOW 33/30 MHZ LOW 33/30 MHZ OTHER CLKs LOW RUNNING RUNNING RUNNING RUNNING XTAL & VCOs OFF RUNNING RUNNING RUNNING RUNNING Power Management Timing PCICLK_F PCI_STOP# PCICLK(0:5) CPU_STOP# CPUCLK(0:3) Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 3 of 17 APPROVED PRODUCT XG571C SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design 2-Wire SMBUS Control Interface The 2-wire control interface implements a write only slave interface. The XG571 cannot be read back. Sub-addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. It also allows 24/48 Mhz frequency selection and test mode enable. During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first. The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions. The SMBUS interface is disabled when the PWR_DWN# pin is low. Previously set control registers are retained. Serial Control Registers NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated. Following the acknowledge of the Address Byte (D2), two additional bytes must be sent: 1) “Command Code “ byte, and 2) “Byte Count” byte. Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged. Byte 0: Function Select Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 1 0 0 Pin# * * * * 23 22 Description Reserved Reserved Reserved Reserved 48/24 Mhz (a”1” sets the output to 48MHz, a “0” sets the output to 24MHz) 48/24 Mhz (a”1” sets the output to 48MHz, a “0” sets the output to 24MHz) Bit1 Bit0 1 1 Tri-State 1 0 Spread Spectrum operating mode 0 1 Test Mode 0 0 Normal operating mode Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 4 of 17 XG571C APPROVED PRODUCT SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Serial Control Registers (Cont.) Function Table Function Description Tri-State Test Mode Normal SEL=1 Normal SEL=0 CPU Hi-Z Tclk/2 66 60 PCI Hi-Z Tclk/4 CPU/2 CPU/2 SDRAM Hi-Z Tclk/2 CPU CPU Outputs Ref Hi-Z Tclk 14.318 14.318 IOAPIC Hi-Z Tclk 14.318 14.318 24MHZ Hi-Z Tclk/4 24 24 48MHZ Hi-Z Tclk/2 48 48 Notes: 1. Tclk is a test clock over driven on the Xin input during test mode. 2. The frequency ratio Fout/Fin for the USB output is 3.35294. Byte 1: CPU, 48/24 MHz Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 x x 1 1 1 1 Pin# 23 22 38 39 41 42 Description 48/24 MHz enable/Stopped 48/24 MHz enable/Stopped Reserved Reserved CPUCLK3 enable/Stopped CPUCLK2 enable/Stopped CPUCLK1 enable/Stopped CPUCLK0 enable/Stopped Byte 2: PCI Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup x 1 1 1 1 1 1 1 Pin# 8 16 14 13 12 11 9 Description Reserved PCICLK_F enable/Stopped PCICLK5 enable/Stopped PCICLK4 enable/Stopped PCICLK3 enable/Stopped PCICLK2 enable/Stopped PCICLK1 enable/Stopped PCICLK0 enable/Stopped Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 5 of 17 APPROVED PRODUCT XG571C SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Serial Control Registers (Cont.) Byte 3: SDRAM Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 26 27 29 30 32 33 35 36 Description SDRAM7 enable/Stopped SDRAM6 enable/Stopped SDRAM5 enable/Stopped SDRAM4 enable/Stopped SDRAM3 enable/Stopped SDRAM2 enable/Stopped SDRAM1 enable/Stopped SDRAM0 enable/Stopped Byte 4: Additional SDRAM Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup x x x x x x x x Pin# - Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Byte 5: Peripheral Control (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup x x 1 1 x 1 1 1 Pin# 45 47 1 2 Description Reserved Reserved Reserved IOAPIC0 enable/Stopped Reserved REF2 enable/Stopped REF1 enable/Stopped REF0 enable/Stopped Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 6 of 17 APPROVED PRODUCT XG571C SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Serial Control Registers (Cont.) Byte 6: Reserved Register Bit 7 6 5 4 3 2 1 0 @Pup x x x x x x x x Pin# - Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Byte 7: Frequency Control Bit 7 6 5 4 3 2 1 0 @Pup x x x x x 1 x x Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 7 of 17 XG571C APPROVED PRODUCT SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). In this product, the modulation is 1.0% down from the resting frequency. Amplitude (dB) Without Spectrum Spread With Spectrum Spread Modulated Center Frequency Frequency(MHz) Rested Center frequency Spectrum Analysis Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 8 of 17 XG571C APPROVED PRODUCT SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Maximum Ratings This device contains circuitry to protect the inputs against damage due to high static voltages or electric Voltage Relative to VSS: -0.3V field; however, precautions should be taken to avoid Voltage Relative to VDD: 0.3V application of any voltage higher than the maximum Storage Temperature: rated voltages to this circuit. For proper operation, Vin -65ºC to + 150ºC Operating Temperature: and Vout should be constrained to the range: 0ºC to +70ºC Maximum Power Supply: VSS<(Vin or Vout)<VDD 7V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Electrical Characteristics Characteristic Symbol Min Typ Max Units Conditions Input Low Voltage VIL - - 0.8 Vdc - Input High Voltage VIH 2.0 - - Vdc - Input Low Current IIL -66 µA Input High Current IIH 5 µA Output Low Voltage IOL = 4mA VOL - - 0.4 Vdc All Outputs (see buffer spec) Output High Voltage IOH = 4mA VOH 2.4 - - Vdc All Outputs Using 3.3V Power (see buffer spec) Tri-State leakage Current Ioz - - 10 µA Dynamic Supply Current Idd - - 100 mA CPU = 66.6 MHz, PCI = 33.3 MHz Static Supply Current Isdd - - 1 mA Powered Down = Active Short Circuit Current ISC 25 - - mA 1 output at a time - 30 seconds VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 9 of 17 XG571C APPROVED PRODUCT SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Switching Characteristics Characteristic Min Typ Max Units Output Duty Cycle Symbol - 45 50 55 % Measured at 1.5V CPU to PCI Offset tOFF 1 - 4 ns 15 pf Load Measured at 1.5V tSKEW - - 250 ps 15 pf Load Measured at 1.5V ∆Period Adjacent Cycles ∆P - - +250 ps - Jitter Spectrum 20 dB Bandwidth from Center BW J 500 KHz Overshoot/Undershoot Beyond Power Rails Vover - 1.5 V 22 ohms @ source of 8 inch PCB run to 15 pf load Ring Back Exclusion VRBE 0.7 2.1 V Note1 Buffer out Skew All CPU and PCI Buffer Outputs - Conditions VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC Note 1: Ring Back must not enter this range. Buffer Characteristics for CPUCLK(0:3), IOAPIC Characteristic Symbol Min Typ Max Units Conditions Pull-Up Current IOH 22 - 31 mA Vout = VDD - .5V Pull-Up Current IOH 37 - 56 mA Vout = 1.25V Pull-Down Current IOL 30 - 41 mA Vout = 0.4V Pull-Down Current IOL 75 - 102 mA Vout = 1.2V Rise/Fall Time Min Between 0.4 V and 2.0 V TRFmin 0.4 - - nS 10 pF Load Rise/Fall Time Max Between 0.4 V and 2.0 V TRFmax - - 2.0 nS 20 pF Load VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V± ±5% , TA = 0ºC to +70ºC Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 10 of 17 XG571C APPROVED PRODUCT SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Buffer Characteristics for REF(1:2) and 48/24 MHz Characteristic Max Units Pull-Up Current Symbol IOH Min 13 Typ - 17 mA Conditions Vout = VDD - .5V Pull-Up Current IOH 30 - 44 mA Vout = 1.5V Pull-Down Current IOL 13 - 19 mA Vout = 0.4V Pull-Down Current IOL 32 - 44 mA Vout = 1.5V Rise/Fall Time Min Between 0.4 V and 2.4 V TRFmin 1.0 - - nS 10 pF Load Rise/Fall Time Max Between 0.4 V and 2.4 V TRFmax - - 2.0 nS 20 pF Load VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC Buffer Characteristics for REF0 and SDRAM(0:7) Characteristic Symbol Min Typ Max Units Conditions Pull-Up Current IOH 30 - 39 mA Vout = VDD - .5V Pull-Up Current IOH 75 - 109 mA Vout = 1.5V Pull-Down Current IOL 30 - 40 mA Vout = 0.4V Pull-Down Current IOL 75 - 103 mA Vout = 1.2V Rise/Fall Time Min Between 0.4 V and 2.4 V TRFmin 0.5 - - nS 20 pF Load Rise/Fall Time Max Between 0.4 V and 2.4 V TRFmax - - 2.0 nS 30 pF Load VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V± ±5% , TA = 0ºC to +70ºC Buffer Characteristics for PCICLK(0:5,F) Characteristic Symbol Min 18 Typ - Max Units 23 mA Conditions Pull-Up Current IOH Vout = VDD - .5V Pull-Up Current IOH 44 - 64 mA Vout = 1.5V Pull-Down Current IOL 18 - 25 mA Vout = 0.4V Pull-Down Current IOL 50 - 70 mA Vout = 1.5V Rise/Fall Time Min Between 0.4 V and 2.4 V TRFmin 0.5 - - nS 15 pF Load Rise/Fall Time Max Between 0.4 V and 2.4 V TRFmax - - 2.0 nS 30 pF Load VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 11 of 17 XG571C APPROVED PRODUCT SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Crystal and Reference Oscillator Parameters Characteristic Symbol Min Typ Max Units Conditions Frequency Fo 12.00 14.31818 16.00 MHz Tolerance TC - - +/-100 PPM Calibration note 1 TS - - +/- 100 PPM Stability (Ta -10 to +60C) note 1 TA - - 5 PPM Aging (first year @ 25C) note 1 Mode OM - - - Pin Capacitance CP DC Bias Voltage VBIAS 0.3Vdd Vdd/2 0.7Vdd V Startup time Ts - - 30 µS Load Capacitance CL - 20 - pF Effective Series resonant resistance R1 - - 40 Ohms Parallel Resonant 6 pF Power Dissipation DL - - 0.10 mW Shunt Capacitance CO - -- 8 pF Capacitance of XIN and Xout pins to ground (each) The crystal’s rated load. Note 1 Note 1 Crystal’s internal package capacitance (total) For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. Budgeting Calculations Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore 2.0 pF Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore 3.0 pF External crystal loading capacitors (connect to ground) 15.0 pF the total parasitic capacitance would therefore be = 20.0.0 pF. Note 1: It is recommended but not mandatory that a crystal meets these specifications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 12 of 17 XG571C APPROVED PRODUCT SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design PCB Layout Suggestion Via to VDD Island Via to GND plane XG571 3.3V VCC FB1 48 1 2 3 C3 4 22µF 5 C4 6 7 47 46 C11 45 44 FB2 43 VCC2.5V 42 41 8 C12 40 C10 9 10 11 12 13 C5 14 15 16 17 18 19 C6 20 21 22 23 24 39 22µF 38 C14 37 36 35 34 C9 33 32 31 30 29 28 C8 27 26 25 C7 This is only a layout recommendation for best performance and lower EMI. The designer may choose a different approach but C4, C5, C6, C7, C8, C9, C10, C11and C12 (all are 0.1µf) should always be used and placed close to their VDD pins. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 13 of 17 XG571C APPROVED PRODUCT SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Package Drawing and Dimensions 48 Pin SSOP Outline Dimensions INCHES SYMBOL A C L H E NOM MAX MIN NOM MAX 0.095 0.102 0.110 2.41 2.59 2.79 A1 0.008 0.012 0.016 0.20 0.31 0.41 A2 0.088 0.090 0.092 2.24 2.29 2.34 B 0.008 0.010 0.0135 0.203 0.254 0.343 C 0.005 - 0.010 0.127 - 0.254 D 0.620 0.625 0.630 15.75 15.88 16.00 E 0.292 0.296 0.299 7.42 7.52 7.59 e D a A2 A A1 B e Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com MILLIMETERS MIN 0.025 BSC 0.635 BSC H 0.400 0.406 0.410 10.16 10.31 a 0.10 0.013 0.016 0.25 0.33 0.41 L 0.024 0.032 0.040 0.61 0.81 1.02 a 0º 5º 8º 0º 5º 8º X 0.085 0.093 0.100 2.16 2.36 2.54 Document#: 38-07019 Rev. ** 10.41 5/17/2001 Page 14 of 17 XG571C APPROVED PRODUCT SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Package Drawing and Dimensions (Cont.) D R0.15 14° TYP 1.0 R0.1 0.05 MAX. 1.0 0.05 MAX. E1 A E BO L20 b .08 C B A -B385 SURFACES ROUGHNESS: 6+ 27n(RZ) 8° 4 A RD [10° TYP R A2 c c1 0.25 -C- 0.07 L C b1 B e A1 DETAIL A R1.30 0.10~0.15 0.00 ~ 0.05 1.0 DETAIL B 48 Pin TSSOP Dimensions INCHES SYMBOL SECTION V-V MIN MILLIMETERS MAX MIN NOM MAX A - - 0.0433 - - 1.10 A1 0.002 0.004 0.006 0.05 0.10 0.15 A2 0.033 0.035 0.037 0.85 0.90 0.95 L 0.019 0.023 0.029 0.50 0.60 0.75 R 0.043 - - 0.10 - - b 0.006 - 0.010 0.170 - 0.27 b1 0.006 0.008 0.009 0.170 0.20 0.225 c 0.004 - 0.007 0.105 - 0.175 c1 0.004 0.005 0.006 0.105 0.125 0.145 θ 0° - 8° e Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com NOM 0.020 BSC 0.50 BSC D 0.488 0.492 0.496 12.40 12.50 12.60 E 0.313 0.319 0.325 7.95 8.1 8.25 E1 0.236 0.240 0.244 6.00 6.1 6.20 Document#: 38-07019 Rev. ** 5/17/2001 Page 15 of 17 APPROVED PRODUCT XG571C SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Ordering Information Part Number Package Type XG571CYB 48 PIN SSOP Commercial, 0ºC to +70ºC XG571CTB 48 PIN TSSOP Commercial, 0ºC to +70ºC Note: Production Flow The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress XG571CYB Date Code, Lot # XG571CYB Flow B = Commercial, 0ºC to + 70ºC Package Y = SSOP T = TSSOP Revision Device Number Notice Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07019 Rev. ** 5/17/2001 Page 16 of 17 APPROVED PRODUCT XG571C SMBus Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology for Pentium® Processor Based Design Document Title: XG571C SMBus Frequency Clock Generator w/EMI Reduction Spread Spectrum Technology Document Number: 38-07019 Rev. ** ECN No. 106947 Issue Date 06/29/01 Orig. of Change IKA Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Description of Change Convert from IMI to Cypress Document#: 38-07019 Rev. ** 5/17/2001 Page 17 of 17