NSC 100364_09

May 15, 2009
100364
Low Power 16-Input Multiplexer
General Description
The 100364 is a 16-input multiplexer. Data paths are controlled by four Select lines (S0–S3). Their decoding is shown
in the truth table. Output data polarity is the same as the seleted input data. All inputs have 50 kΩ pulldown resistors.
■
■
■
■
■
2000V ESD protection
Pin/function compatible with 100164
Voltage compensated operating range = −4.2V to −5.7V
Available to industrial grade temperature range
Standard Microcircuit Drawing
(SMD) 5962-9459201
Features
■ 35% power reduction of the 100164
Logic Symbol
Pin Names
Description
I0–I15
Data Inputs
S0–S3
Select Inputs
Z
Data Output
10030101
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
10030103
10030102
© 2009 National Semiconductor Corporation
100301
100301 Version 2 Revision 2
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Print Date/Time: 2009/05/15 10:45:59
100364 Low Power 16-Input Multiplexer
OBSOLETE
100364
Logic Diagram
10030105
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100301 Version 2 Revision 2
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100364
Truth Table
Select Inputs
Output
S0
S1
S2
S3
Z
L
L
L
L
I0
H
L
L
L
I1
L
H
L
L
I2
H
H
L
L
I3
L
L
H
L
I4
H
L
H
L
I5
L
H
H
L
I6
H
H
H
L
I7
I8
L
L
L
H
H
L
L
H
I9
L
H
L
H
I10
H
H
L
H
I11
L
L
H
H
I12
H
L
H
H
I13
L
H
H
H
I14
H
H
H
H
I15
H = HIGH Voltage Level
L = LOW Voltage Level
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100301 Version 2 Revision 2
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100364
(DC Output HIGH)
ESD (Note 2)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
−50 mA
≥ 2000V
Recommended Operating
Conditions
Above which the useful life may be impaired
Storage Temperature (TSTG)
−65°C to +150°C
Maximum Junction Temperature (TJ)
Ceramic
+175°C
Pin Potential to
Ground Pin (VEE)
−7.0V to +0.5V
Input Voltage (DC)
VEE to +0.5V
Output Current
Case Temperature (TC)
Military
Supply Voltage (VEE)
−55°C to +125°C
−5.7V to −4.2V
Note 1: Absolute maximum ratings are those values beyond which the
device may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55°C to +125°C
Symbol
VOH
VOL
Parameter
Output HIGH Voltage
Output LOW Voltage
Min
Max
Units
TC
−1025
−870
mV
0°C to
VIN = VIH (Max)
Conditions
Loading with
+125°C
or VIL (Min)
50Ω to −2.0V
−1085
−870
mV
−55°C
−1830
−1620
mV
0°C to
−1830
−1555
mV
−55°C
−1035
mV
0°C to
VIN = VIH (Min)
Loading with
+125°C
or VIL (Max)
50Ω to −2.0V
−1085
mV
−55°C
−1610
mV
0°C to
−1555
mV
−55°C
Notes
(Notes 3, 4, 5)
+125°C
VOHC
VOLC
Output HIGH Voltage
Output LOW Voltage
(Notes 3, 4, 5)
+125°C
VIH
Input HIGH Voltage
−1165
−870
mV
−55°C to
Guaranteed HIGH Signal
+125°C
for All Inputs
VIL
Input LOW Voltage
−1830
−1475
mV
−55°C to
Guaranteed LOW Signal
+125°C
for All Inputs
(Notes 3, 4, 5,
6)
−55°C to
VEE = −4.2V
(Notes 3, 4, 5)
+125°C
VIN = VIL (Min)
0°C to
VEE = −5.7V
+125°C
VIN = VIH (Max)
IIL
Input LOW Current
IIH
IEE
Input HIGH Current
Power Supply Current
μA
0.50
−95
300
μA
450
μA
−55°C
−35
mA
−55°C to
Inputs Open
(Notes 3, 4, 5,
6)
(Notes 3, 4, 5)
(Notes 3, 4, 5)
+125°C
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55°C), then testing
immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be
considered a worst case condition at cold temperatures.
Note 4: Screen tested 100% on each device at −55°C, +25°C, and +125°C, Subgroups, 1, 2, 3, 7 and 8.
Note 5: Sampled tested (Method 5005, Table I) on each manufactured lot at −55°C, +25°C, and +125°C, Subgroups A1, 2, 3, 7 and 8.
Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.
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100301 Version 2 Revision 2
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100364
AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
tPLH
Propagation Delay
tPHL
I0–I15 to Output
tPLH
Propagation Delay
tPHL
S0, S1 to Output
tPLH
Propagation Delay
tPHL
S2, S3 to Output
tTLH
Transition Time
tTHL
20% to 80%, 80% to 20%
TC = −55°C
TC = 25°C
TC = +125°C
Units
Min
Max
Min
Max
Min
Max
0.50
2.60
0.60
2.40
0.60
2.80
ns
0.70
3.30
0.90
3.10
1.00
3.50
ns
0.50
2.90
0.70
2.60
0.60
3.00
ns
0.20
1.20
0.20
1.20
0.20
1.20
Conditions
Notes
Figures 1, 2 (Notes 7, 8,
9)
(Note 10)
ns
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55°C), then testing
immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be
considered a worst case condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25°C, temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each Mfg. lot at +25°C, Subgroup A9, and at +125°C, and −55°C temp., Subgroups A10 and A11.
Note 10: Not tested at +25°C, +125°C and −55°C temperature (design characterization data).
Test Circuit
10030106
FIGURE 1. AC Test Circuit
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100301 Version 2 Revision 2
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100364
Switching Waveforms
10030107
Note 11: VCC, VCCA = +2V, VEE = −2.5V
Note 12: L1 and L2 = Equal length 50Ω impedance lines
Note 13: RT = 50Ω terminator internal to scope
Note 14: Decoupling 0.1 μF from GND to VCC and VEE
Note 15: All unused outputs are loaded with 50Ω to GND
Note 16: CL = Fixture and stray capacitance ≤ 3 pF
Note 17: Pin numbers shown are for flatpak; for DIP see logic symbol
FIGURE 2. Propagation Delay and Transition Times
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100301 Version 2 Revision 2
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100364
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Ceramic Dual-In-Line Package (0.400″ Wide) (D)
NS Package Number J24E
24-Lead Quad Cerpak (F)
NS Package Number W24B
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100301 Version 2 Revision 2
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100364 Low Power 16-Input Multiplexer
Notes
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