ETC 22247J

FBGA User’s Guide
Version 4.2
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Publication Number 22247 Revision J
Amendment 0 Issue Date November 1, 2002
November 1, 2002
Version 4.2
© 2002 Advanced Micro Devices, Inc.
Advanced Micro Devices reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
This publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of
merchantability or fitness for a particular application. AMD® assumes no responsibility for the use of any circuitry other
than the circuitry in an AMD product.
The information in this publication is believed to be accurate in all respects at the time of publication, but is subject to
change without notice. AMD assumes no responsibility for any errors or omissions, and disclaims responsibility for any
consequences resulting from the use of the information included herein. Additionally, AMD assumes no responsibility
for the functioning of undescribed features or parameters.
Trademarks
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective
companies.
FBGA User’s Guide
Chapter 1: Introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 7
Table 1.1: Package Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: AMD Fine-Pitch Ball Grid Array (FBGA) - - - - - - - - - - - - - - 9
Package Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2-1. FBGA Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
The Impact of Die Size Changes on FBGA Package Size . . . . . . . . . . . . . . . . . . . . . . . . . 9
The Impact of Die Size Changes on FBGA Package Size . . . . . . . . . . . . . . . . . . . . . . . . 10
FBGA Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2-2. 48-Ball Ball (4 Mb to 32Mb, x8/x16, Low Voltage) . . . . . . . . . . . . 11
Figure 2-3. 48-Ball (16 Mb, x8, Low Voltage) . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2-4. 63-Ball (32 Mb to 64 Mb, x8/x16, Low Voltage) . . . . . . . . . . . . . . 12
Figure 2-5. 63-Ball (32 Mb to 1 Gb, x8, Low Voltage) . . . . . . . . . . . . . . . . . . . 12
Figure 2-6. 84-Ball (32 Mb to 4 Gb, x16/x32 Low Voltage) . . . . . . . . . . . . . . 13
Figure 2-7. 84-Ball (32 Mb to 128 Mb, x16/x3240-Ball (64 Mb, x8, UltraNAND
Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 3: AMD Fortified-BGA - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14
Package Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-1. Fortified-BGA Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Effects of Solder Ball Diameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fortified-BGA Migration and Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fortified-BGA (FBGA) Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-2. 64-Ball Fortified-BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-3. 80-Ball Fortified-BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 4: AMD Multi-Chip Packaging - - - - - - - - - - - - - - - - - - - - - - 17
Package Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-1. 2-Die MCP Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-2. Same-Die Stack (SDS) MCP Construction . . . . . . . . . . . . . . . . . . .
System integration and space savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-3. 2-Die Stack (Flash+SRAM) MCP . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-4. Same-Die-Stack (SDS) MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCP Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-5. Am29DL16XD and 4Mb (x8/x16) SRAM MCP Pinout . . . . . . . . .
Figure 4-6. Am29DL32XD and 4Mb (x8/x16) SRAM MCP Pinout . . . . . . . . .
Figure 4-7. Am29DL32XD and 8Mb (x8/x16) SRAM MCP Pinout . . . . . . . . .
Figure 4-8. Am29DL64XD and 8Mb (x8/x16) SRAM MCP Pinout . . . . . . . . .
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Chapter 5: Daisy Chains - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 21
Figure 5-1. FBGA 16 Mbit Daisy Chain Schematic (Top View) . . . . . . . . . . . 22
Figure 5-2. FBGA 16 Mbit Board Layout (Top View) . . . . . . . . . . . . . . . . . . . 22
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Figure 5-3. FBGA 32 Mbit Daisy Chain Schematic (Top View) . . . . . . . . . . .
Figure 5-4. FBGA 32 Megabit Board Layout (Top View) . . . . . . . . . . . . . . . .
Figure 5-5. FBGA 64 Mbit Daisy Chain Schematic (Top View) . . . . . . . . . . .
Figure 5-6. FBGA 64 Mbit Board Layout (Top View) . . . . . . . . . . . . . . . . . . .
Figure 5-7. FBGA 84-Ball Daisy Chain Schematic (Top View) . . . . . . . . . . . .
Figure 5-8. Fortified BGA 84-Ball Board Layout (Top View) . . . . . . . . . . . . .
Figure 5-9. Fortified BGA 64-Ball Board Layout (Top View) . . . . . . . . . . . . .
Figure 5-10. Fortified BGA 64-Ball Daisy Chain Schematic (Top View) . . . .
Figure 5-11. Fortified BGA 80-Ball Daisy Chain Schematic (Top View) . . . .
Figure 5-12. Fortified BGA 80-Ball Board Layout (Top View) . . . . . . . . . . . .
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Chapter 6: Package Physical Description - - - - - - - - - - - - - - - - - - - - 28
FBGA Package Materials Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.1: FBGA-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBGA-BT Ball Attach Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-1. FBGA Package Ball Attach Detail . . . . . . . . . . . . . . . . . . . . . . . . .
FBGA Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-2. Path of Heat Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.2: Thermal Resistance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 7: Board Design and Layout Considerations - - - - - - - - - - - 53
General Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-1. Solder Wetting Around Pad During Reflow . . . . . . . . . . . . . . . . . .
Recommended Board Design Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-2. Recommended Dimensions for the AMD 0.30 mm Solder Ball . . .
Routing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-3. Example of 48-Ball Single Layer Board Routing . . . . . . . . . . . . . .
Figure 7-4. Example of 63-Ball Single Layer Board
Routing Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-5. Example of Interstitial Via Design for High Ball Count Packages
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Chapter 8: Component Qualification Testing - - - - - - - - - - - - - - - - - 57
Preconditioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.1: Moisture Sensitivity Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HAST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Shock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Retention Bake. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HTOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBGA-BT Component Level Test Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 9: Board Level Characterization Studies - - - - - - - - - - - - - - 61
Experimental Design and Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly of Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stress Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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62
63
63
Chapter 10:Miscellaneous - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 65
Shipping Container Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sockets for FBGA-BT Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBGA Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBGA Package Designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Appendix A: Article Reprints - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 67
Reliability Evaluation of Chip Scale Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
FGBAs—The CSP of Choice for Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Memo on ΨJ–T, Case Level Thermal Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Appendix B: Application Note - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 85
Daisy Chain Samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Revision Summary - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 91
Revision E (Version 2.2): March 13, 1999. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision F (Version 2.3): May 17, 1999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision F+1 (Version 2.3.1): July 30, 1999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision G (Version 3.0): January 15, 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision G+1 (Version 3.1): March 12, 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision H (Version 4.0): January 24, 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision I (Version 4.1): April 12, 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision J (Version 4.2): November 1, 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Version 4.2, November 1, 2002
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Chapter 1:
Introduction
There is a trend in the electron industry to miniaturize. From tower PCs to lap-tops to PocketPCs,
from giant cell phones to pager size handsets, the demand for smaller feature rich electronic devices
will continue for years to come.
The trend for Chip Scale Packages (CSP) have grown tremendously since their introduction.
Applications such as cell phones, home entertainments, automotive engine controllers and networking
equipments all have adopted CSP packages into their systems. To address the needs of different
applications such as small package size, reliability or migration compatibility, AMD offers three
families of CSP: Fine-Pitch Ball Grid Array (FBGA), Fortified-BGA and Stacked-MCM
Table 1.1: Package Highlights
Package Highlights
Benefits
Target Applications
Small Package
Ideal for space constraint PCB
designs
Ideal for application with space constraints.
Portable application such as mobile phones,
camcorders and PDAs would benefit most
1.2mm Max package
height
Ideal for low-provide application
BT-Resin
Superior board level reliability
FBGA Package
Fortified-BGA
Uniform 11x13mm
Package size
Simple and smooth migration
and compatibility across densities up to 256Mb
1.0mm Ball Pitch
Allows for more relax PCB design rules
0.6mm Ball Diameter
Improves board level reliabilities
Removes concerns for Automotive, Networking, Telecom and other applications that demand the highest board level reliabilities
Stacked-MCM
Small Package size
Idea for space constrain PCB designs
1.4mm Max Height
Idea for low-profile applications
Combines Flash and
SRAM
Increase memory capacity with
no increase in board spaces
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Enabling applications with increase memory
for higher performance without increase in
board space. Ideally suited for Camcorders,
mobile phones, PDAs and other wireless applications
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FBGA User’s Guide
Table 1.1: Package Highlights
Available Combinations:
128Mb Flash + Flash
16Mb Flash + 2Mb
SRAM
16Mb Flash + 4Mb
SRAM
32Mb Flash + 4Mb
SRAM
32Mb Flash + 8Mb
SRAM
64Mb Flash + 8Mb
SRAM
64Mb Flash + 16Mb
SRAM
8
Flexible memory combinations
for number design possibilities
and opportunities
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FBGA User’s Guide
Chapter 2:
AMD Fine-Pitch Ball Grid Array (FBGA)
The AMD FBGA package family offers Flash memory designers significant reduction in board real
estate over Thin Small Outline Packages (TSOPs). In addition AMD FBGA packages provide many
advantages over other Flash memory supplies’ chip scale packages, sush as alternatives robust board
level reliability and smooth pinout migrations. The packages are available for several popular 1.8-volt
and 3.0-volt Flash memory densities. The FBGA packages are constructed similar to conventional IC
packages and are an extension of the proven BGA technologies. For PCB assembly, existing
equipment and proven manufacturing processes may be used.
Package Construction
AMD FBGA is constructed on rigid BT-Resin substrates. The die is mounted on the substrate and the
leads are bonded using gold wires. The device is encapsulated in plastic and solder balls are attached
to the bottom of the substrate.
Figure 2-1. FBGA Construction
%75HVLQ
6XEVWUDWH
3ODWHG9LD
PP
6ROGHU%DOO
PP
3LWFK
&RSSHU)RLO
Note: Package Height = 1.2 mm max.
The Impact of Die Size Changes on FBGA Package Size
There are many costs associated with the manufacturing of semiconductor devices: die cost, assembly
cost and testing costs just to name a few. The die cost typically has the most impact on the total
manufacturing cost. In order to drive down the cost of the final product, semiconductor manufacturers
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FBGA User’s Guide
will stride to reduce die sizes. AMD’s FBGA packages allow smaller, lower cost die to be placed in
the same package without affecting package dimensions or requiring PC board redesigns.
The Impact of Die Size Changes on FBGA Package Size
The minimum distance between balls on the FBGA, the ball pitch, great affects an OEM’s PC board
technology and system routing complexity. Device with ball pitches of 0.8mm can be easily be routed
with today’s widely used and cost effect PC board technology (FR4 with 0.005 inch lines and spaces).
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FBGA User’s Guide
FBGA Package Pinouts
All pinouts are shown top view, with balls facing down.
Figure 2-2. 48-Ball Ball (4 Mb to 32Mb, x8/x16, Low Voltage)
Am29LV400B
6 mm
Ball B2 = A17
6
A13
A12
A14
A15
A16
BYTE#
DQ15
/A-1
VSS
Am29LV800B
Am29DL800B
Am29SL800C
5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ7
Ball C3 = A18
4
WE#
RESET#
NC
A19
DQ5
DQ12
VCC
DQ4
3
RY/
BY#
WP#/
ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
Ball D4 = A19
2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
Am29DL16xD
Am29SL160C
1
A3
A4
A2
A1
A0
CE#
OE#
VSS
A
B
C
D
E
F
G
H
6 mm
8 mm
9 mm
8 mm
Am29LV160D
Ball D4 = A19
Ball B3 = WP#/ACC
9 mm
6 mm
Am29LV320D
Am29DS323D
Am29PDS322D
Ball D3 = A20
Ball D3 = WP#/ACC
12 mm
Figure 2-3. 48-Ball (16 Mb, x8, Low Voltage)
6
A14
A13
A15
A16
A17
NC
A20
Vss
5
A9
A8
A11
A12
A19
A10
DQ6
DQ7
4
WE#
RESET#
NC
NC
DQ5
NC
Vcc
DQ4
3
RY/BY#
NC
NC
NC
DQ2
DQ3
Vcc
NC
2
A7
A18
A6
A5
DQ0
NC
NC
DQ1
1
A3
A4
A2
A1
A0
CE#
OE#
Vss
A
B
C
D
E
F
G
H
8 mm
Am29LV017D
9 mm
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FBGA User’s Guide
All pinouts in this chapter are shown top view, balls facing down.
Figure 2-4. 63-Ball (32 Mb to 64 Mb, x8/x16, Low Voltage)
NC
7
NC
NC
A13
A12
A14
A15
A16
BYTE#
DQ15/
A-1
Vss
6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
5
WE#
Reset#
A21
A19
DQ5
DQ12
VCC
DQ4
4
RY/
BY#
WP#/
ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A3
A4
A2
A1
A0
CE#
OE#
Vss
2
NC
1
NC
NC
A
B
NC
NC
NC
14 mm
Am29LV640DU
* Balls are shorted together via the substrate but not connected
to the die
C
NC
11 mm
NC
8 mm
Am29DL32X
8
D
E
F
G
H
J
K
NC
NC
NC
NC
L
M
12 mm
DQ15
ACC
J7
D4
Figure 2-5. 63-Ball (32 Mb to 1 Gb, x8, Low Voltage)
8
NC*
NC*
7
NC*
NC*
NC*
NC*
NC*
NC*
A14
A13
A15
A16
A17
A24
A20
Vss
6
A9
A8
A11
A12
A19
A10
DQ6
DQ7
5
WE#
Reset#
A22
NC
DQ5
NC
Vcc
DQ4
4
RY/
BY#
Acc
A23
A25
DQ2
DQ3
3
A7
A18
A6
A5
DQ0
A26
NC
DQ1
A3
A4
A2
A1
A0
CE#
OE#
Vss
NC*
NC*
* Balls are shorted together via the substrate but not connected
to the die
NC*
NC*
L
M
8 mm
Am29LV033C
14 mm
12
2
NC*
1
NC*
NC*
A
B
C
VCC
J4
Am29LV065D
D
E
F
G
H
J
K
11 mm
A21
12 mm
VIO
A22 =
A23 =
A24 =
A25 =
A26 =
J4
64 Megabit
128 Megabit
256 Megabit
512 Megabit
1 Gigabit
Version 4.2, November 1, 2002
FBGA User’s Guide
All pinouts in this chapter are shown top view, balls facing down.
Figure 2-6. 84-Ball (32 Mb to 4 Gb, x16/x32 Low Voltage)
C9
D9
E9
F9
G9
H9
J9
DQ9
DQ30
VCC
DQ13
DQ12
DQ27
DQ26
VCC
A8
B8
C8
D8
E8
F8
G8
H8
J8
K8
CE#
VSS
DQ15
DQ29
DQ28
DQ11
VSS
DQ24
VCC
A19
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
A20
WORD#
OE#
DQ14
VSS
DQ10
DQ25
A18
A17
A16
A6
B6
C6
D6
E6
F6
G6
H6
J6
K6
WE#
RFU
A21
DQ31/A-1
RFU
RFU
DQ8
A15
A14
A13
A5
B5
C5
D5
E5
F5
G5
H5
J5
K5
RESET#
ACC
WP#
RY/BY#
RFU
RFU
A26
A25
A24
A23
A4
B4
C4
D4
E4
F4
G4
H4
J4
K4
A1
A2
A3
A0
DQ2
RFU
A12
A11
A9
A10
A3
B3
C3
D3
E3
F3
G3
H3
J3
K3
A4
A5
DQ0
DQ16
DQ18
DQ5
DQ21
A8
A6
A7
11 mm
Am29PL3200DU
B9
12 mm
NC
B2
C2
D2
E2
F2
G2
H2
J2
K2
VCC
DQ1
VSS
DQ19
DQ4
DQ6
DQ7
DQ23
VSS
C1
D1
E1
F1
G1
H1
J1
DQ17
VCC
DQ1
DQ20
VSS
VCC
DQ22
A5, D5
A20: 64 Mb
A21:128 Mb
A22: 256 Mb
A23: 512 Mb
A24: 1 Gb
A25: 2 Gb
A26: 4 Gb
Figure 2-7. 84-Ball (32 Mb to 128 Mb, x16/x3240-Ball (64 Mb, x8, UltraNAND Only)
8 mm
Am30LV0064D
Keep-out
Zones
Four
Corners.
May be
required
in higher
density
devices
with larger
packages.
6
NC
Vcc
NC
NC
NC
NC
NC
NC
Vccq
NC
SE#
IO7
IO6
IO5
IO4
NC
NC
CE#
RE#
RY/
BY#
2
NC
CLE
ALE
WE#
WP#
IO0
IO1
IO2
IO3
NC
1
NC
Vss
NC
NC
NC
NC
NC
NC
Vss
NC
A
B
C
D
E
F
G
H
J
K
5
4
3
Version 4.2, November 1, 2002
The keepout zone is
composed
of
additional
balls that
will be oncenter
relative to
the array.
15 mm
13
FBGA User’s Guide
Chapter 3:
AMD Fortified-BGA
New performance driven applications continues to demand high board level reliability packages from
Flash memories. In addition, as PCB designs become increasingly complex, assembly-friendly
package becomes more desirable. AMD’s Fortified-BGA for the Flash memory combines both
superior reliability beyond the standard requirements and ease-of-use in one single package. It is ideal
for telecom, networking, automotive and avionics applications.
Package Construction
AMD’s Fortified-BGA is offer in a single easy to use 13x11mm x 1.4mm Ht. Package size, with
0.6mm solder ball diameter at 1.0mm ball pitch. Designed around AMD's already robust FBGA
(0.8mm ball pitch), the Fortified-BGA uses industry proven BT-Substrate to lower the CTE mismatch
between the substrate and the PCB.
Figure 3-1. Fortified-BGA Construction
%75HVLQ
6XEVWUDWH
3ODWHG9LD
PP
6ROGHU%DOO
PP
3LWFK
&RSSHU)RLO
Note: Package Height = 1.4mm Max.
Effects of Solder Ball Diameter
It is well known in the industry that solder ball diameter has a direct affect on solder joint reliability
during temperature cycling. Lager solder balls typically yield higher standoff heights after board
assembly. The importance of higher standoff is easiest explained through CTE mismatch. As describe
in many papers, higher standoff typically yields higher solder joint reliability during temperature
cycling. AMD's Fortified-BGA currently has the largest solder ball size (0.6mm Diameters) of any
14
Version 4.2, November 1, 2002
FBGA User’s Guide
BGA package for Flash memory. As a result, AMD’s Fortified-BGA offers superior board level
reliability, during Temperature Cycling, compared to other competitor’s BGA packages. When
compared to a competitor’s 10x13mm BGA, the 64-Ball (8x8 matrix) Fortified-BGA is expected to
have a higher relative life by a factor of 4.3X, and the 80-Ball (8x10 matrix) Fortified-BGA is
expected be 4.6X higher relative life.
Fortified-BGA Migration and Transition
AMD’s Fortified-BGA has taken AMD’s tradition of simple pinout migration to higher density one
step further. It virtually allows migration between densities without new board designs.
Fortified-BGA’s 11x13mm package size is designed to host any Flash density up to 256Mb. This
concept greatly lowers cost for customers. By anticipating future density needs, customers can
virtually have one board design. Furthermore, this “one-package-fits-all” concept can also help trim
equipment cost. The same socket, test boards, handlers, traces etc. are now interchangeable between
densities. Thereby increases the useful life of equipments.
AMD's Fortified-BGA takes full advantage of the real estate underneath the package. With 1.0mm ball
pitch, PCB design rules can be more relaxed. At any drill or pad size, 1.0mm pitch provides more
clearance for traces and spaces. For example, either 5mil or 7mil trace and space design rules can by
used. More clearance also allows for larger via capabilities, ideal for multi-layer PCB designs.
Board assembly also benefits from 1.0mm ball pitch. AMD's Fortified-BGA is aligned with many
FPGAs and Micro-Controller in terms of ball pitch. This allows for less expensive PCB technology to
be used.
AMD's Fortified-BGA, in essence, simplifies customers' transition to BGA packages. It is a LowCost, highly reliable CSP solution to TSOP and other traditional leaded packages.
Fortified-BGA (FBGA) Pinouts
All pinouts are shown top view, with balls facing down.
Version 4.2, November 1, 2002
15
FBGA User’s Guide
8
RFU
7
A22
A13
A23
A12
A14
Vccq
A15
Vss
A24
A25
11 mm
Figure 3-2. 64-Ball Fortified-BGA
RFU
A16
R FU
RF U
RF
U
A 13
A1 2
A1 4
A1 5
A 16
A 9
A8
A1 0
A1 1
D Q7
DQ 1
4
R ST #
A2 1
A1 9
A1 8
W E#
V cq
V s
RF U
Vs
DQ 6
D Q5
DQ 1
2
Vc
DQ 4
A2 0
D Q2
DQ 1
0
D Q1 1
DQ 3
A 7
A1 7
A6
A5
D Q0
DQ 8
D Q9
DQ 1
A 3
A4
A2
A1
A 0
CE #
OE #
Vs
R FU
RF U
RF U
R FU
V cq
RF U
RF U
R Y/
A22 = 128Mb
A23 = 256Mb
A24 = 512MB
A25 = 1Gb
RF U
D Q1 3
B Y#
R FU
Vss
RF U
13 mm
6
A9
5
WE#
4
RY/
BY#
A8
A10
RST#
A11
DQ7
DQ14
DQ13
DQ6
AM29LV640X
Ball B4 = ACC
Ball F7 = RFU
Ball G1 = RFU
Ball G7 = DQ15
A21
A19
DQ5
DQ12
Vcc
DQ4
A18
A20
DQ2
DQ10
DQ11
DQ3
AM29LV642X
3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
2
A3
A4
A2
A1
A0
CE#
OE#
Vss
1
RFU
RFU
RFU
RFU
RFU
Vccq
Ball B4 = ACC
Ball F7 = RFU
Ball G1 = CE2#
Ball G7 = DQ15
AM29DL640X
A
B
C
D
E
RFU
F
G
Ball B4 = WP#/ACC
Ball F7 = BYTE#
Ball G1 = RFU
Ball G7 = DQ15/A-1
H
Figure 3-3. 80-Ball Fortified-BGA
8
A2
A1
A0
DQ29
VCCQ
VSS
VCCQ
DQ20
DQ16
WORD\
AM29BDD160G
A2
6
A3
A6
A4
A5
A-1
A7
DQ30
DQ31
DQ26
DQ28
DQ24
DQ25
DQ23
DQ21
DQ18
DQ19
IND\,
WAIT\
OE\
NC
WE\
A3
11 mm
7
A6
VS S
A8
NC
A21
DQ27
RY/BY\
DQ22
DQ17
CE\
A-1
A5
A7
DQ2 9
VCCQ
VSS
VC CQ
DQ2 0
DQ1 6
DQ2 6
DQ2 4
DQ 2 3
DQ1 8
IND\,
WAIT\
NC
DQ3 1
DQ2 8
DQ2 5
DQ 2 1
DQ1 9
OE\
WE\
A2 1
DQ 2 2
DQ1 7
CE\
VCC
DQ30
WORD\
A8
NC
DQ2 7
RY/BY\
A9
A10
A20
DQ1
DQ5
D Q9
WP \
NC
VC C
A1 2
A11
A1 9
DQ2
DQ6
DQ 1 0
DQ1 1
ADV\
CK
A18
DQ0
DQ4
DQ7
D Q8
DQ1 2
DQ1 4
RES ET\
A17
DQ3
VCCQ
VSS
VC CQ
DQ1 3
DQ1 5
VCCQ
A1 5
VSS
A0
A4
AC C
A1 4
5
A1
A1 3
A1 6
VS S
VCC
13 mm
16
4
ACC
A9
A10
A20
DQ1
DQ5
DQ9
WP\
NC
VSS
3
VCC
A12
A11
A19
DQ2
DQ6
DQ10
DQ11
ADV\
CK
2
A14
A13
A18
DQ0
DQ4
DQ7
DQ8
DQ12
DQ14
RES ET\
1
A15
A16
A17
DQ3
VCCQ
VSS
VCCQ
DQ13
DQ15
VCCQ
A
B
C
D
E
F
G
H
J
A19 = 32Mb
A20 = 64Mb
A21 = 128Mb
K
Version 4.2, November 1, 2002
FBGA User’s Guide
Chapter 4:
AMD Multi-Chip Packaging
In portable consumer product segment such as Cell phones, PDAs, digital cameras and audio players
there are demands to increase features and functionalities as well as for smaller, thinner product size.
In order to meet these demands, AMD launched a line of MCP (Multi-Chip Package) products.
Through system integration and PCB optimization, MCP enhances system design in numerous ways
such as reduce PCB size, lower PCB cost, reduce components, lighter weight, smaller system, increase
features and customer flexibility.
Package Construction
Figure 4-1. 2-Die MCP Construction
Mold
Compound
(standard)
Gold
Bond Wire
(standard)
DIE -1
1.4 mm MAX
Die Attach
(standard)
DIE -2
BT Resin Substrate
Solder Mask
Punch or Drill VIA
0.8mm
(FBGA)
0.3, 0.35mm
(FBGA)
Solder Ball Pad
Figure 4-2. Same-Die Stack (SDS) MCP Construction
1.7 mm Max (FBGA)
1.7 mm MAX (Fortified-BGA)
Mold
Compound
(standard)
Gold
Bond Wire
(standard)
DIE-1
Si Spacer
Die Attach
(standard)
DIE-2
BT Resin Substrate
Solder Mask
Punch or Drill VIA
0.8mm
(FBGA)
1.0mm
(Fortified-BGA)
Version 4.2, November 1, 2002
0.45mm
(FBGA)
0.6mm
(Fortified-BGA)
Solder Ball Pad
17
FBGA User’s Guide
System integration and space savings
MCPs are gaining momentum in the industry as a system integration solution. In the cellular
phone market, Flash and SRAM MCP combinations have become very popular. It stacks one
die on top of the other on a rigid BT-substrate. Both chips are wire- bonded to the top of the
substrate and overmolded with encapsulant, solder balls on the bottom of the package. This
technology allows companies to immediately take advantage space savings, with either
smaller or more feature rich products.
Two die stacking is typically use if the top die size is small enough not to cover the bond pad of the
bottom die. However, if both dies are similar in size Same-Die-Stacking (SDS) must be use. SDS uses
a spacer-die, between the top die and the bottom, to allow for addiquiet wire bonding space of the
bottom die. SDS provides powerful flexibility to system integration. With SDS, not only can
components of two different application be integrate in single package, same components can also be
integrated to added feature or higher densities, such as Flash+Flash.
Figure 4-3. 2-Die Stack (Flash+SRAM) MCP
Figure 4-4. Same-Die-Stack (SDS) MCP
18
Version 4.2, November 1, 2002
FBGA User’s Guide
MCP Package Pinouts
All pinouts are shown top view, with balls facing down.
Figure 4-5. Am29DL16XD and 4Mb (x8/x16) SRAM MCP Pinout
A1
A5
A6
A10
NC
NC
NC
NC
Flash only
SRAM only
B1
B3
B4
B5
B6
B7
B8
NC
A7
LB#s
WP#/ACC
WE#
A8
A11
C2
C3
C4
C5
C6
C7
C8
C9
RESET#
CE2s
A19
A12
A15
D6
D7
D8
D9
NC
A9
A13
NC
Shared
A3
A6
UB#s
D2
D3
D4
A2
A5
A18
E1
E2
E3
E4
E7
E8
E9
NC
A1
A4
A17
A10
A14
NC
NC
F1
F2
F3
F4
F7
F8
F9
F10
NC
NC
D5
RY/BY#
VSS
DQ1
DQ6
SA
A16
G3
G4
G5
G6
G7
G8
G9
CE#f
OE#
DQ9
DQ3
DQ4
DQ13
DQ15/A-1
CIOf
H2
H3
H4
H5
H6
H7
H8
H9
CE1#s
DQ0
DQ10
VCCf
VCCs
DQ12
DQ7
VSS
J3
J4
J5
J6
J7
J8
DQ8
DQ2
DQ11
CIOs
DQ5
DQ14
8 mm
11 mm
A0
G2
E10
K1
K5
K6
K10
NC
NC
NC
NC
69-Ball FBGA
Top View
Figure 4-6. Am29DL32XD and 4Mb (x8/x16) SRAM MCP Pinout
A1
A10
NC
NC
B1
B5
B6
B10
NC
NC
NC
NC
C5
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D7
D8
D9
A12
A15
E7
E8
E9
A9
A13
NC
F4
F7
F8
F9
A4
A17
A10
A14
NC
NC
G2
G3
G4
G7
G8
G9
G10
DQ6
SA
A16
NC
H7
H8
H9
D6
D3
D4
A3
A6
UB#
E2
E3
E4
E5
E6
A2
A5
A18
RY/BY#
A20
F1
F2
F3
NC
A1
G1
NC
RESET# CE2s
A0
VSS
DQ1
H2
H3
H4
H5
H6
CE#f
OE#
DQ9
DQ3
DQ4
J3
J4
J5
J6
J7
J8
J9
DQ0
DQ10
VCCf
VCCs
DQ12
DQ7
VSS
K3
K4
K5
K6
K7
K8
DQ8
DQ2
DQ11
CIOs
DQ5
DQ14
L5
L6
NC
NC
8 mm
11.6 mm
J2
L1
F10
DQ13 DQ15/A-1 CIOf
CE1#s
NC
L10
NC
M1
M10
NC
NC
Version 4.2, November 1, 2002
SRAM only
Shared
A19
D5
D2
Flash only
73-Ball FBGA
Top View
19
FBGA User’s Guide
Figure 4-7. Am29DL32XD and 8Mb (x8/x16) SRAM MCP Pinout
A1
A10
NC
NC
B1
B5
B6
B10
NC
NC
NC
NC
C5
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D3
D4
A3
A6
UB#
E2
E3
E4
E5
E6
A2
A5
A18
RY/BY#
A20
F1
F2
F3
F4
NC
A1
A4
A17
G1
G2
G3
G4
G7
NC
D5
D6
RESET# CE2s
Shared
D7
D8
D9
A19
A12
A15
E7
E8
E9
A9
A13
NC
F7
F8
F9
A10
A14
NC
NC
G8
G9
G10
DQ6
SA
A16
NC
H7
H8
H9
A0
VSS
DQ1
H2
H3
H4
H5
H6
CE#f
OE#
DQ9
DQ3
DQ4
J2
J3
J4
J5
J6
J7
J8
J9
CE1#s
DQ0
DQ10
VCCf
VCCs
DQ12
DQ7
VSS
K3
K4
K5
K6
K7
K8
DQ2
DQ11
CIOs
DQ5
DQ14
L1
L5
L6
NC
NC
8 mm
F10
DQ13 DQ15/A-1 CIOf
DQ8
NC
SRAM only
11.6 mm
D2
Flash only
L10
NC
M1
M10
NC
NC
73-Ball FBGA
Top View
Figure 4-8. Am29DL64XD and 8Mb (x8/x16) SRAM MCP Pinout
A1
A10
NC
NC
B1
B5
B6
B10
NC
NC
NC
NC
C5
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D8
D9
A12
A15
D4
A6
UB#
E2
E3
E4
E5
E6
E7
E8
E9
A2
A5
A18
RY/BY#
A20
A9
A13
A21
F1
F2
F3
F4
F7
F8
F9
NC
A1
A4
A17
A10
A14
NC
NC
G1
G2
G3
G4
G7
G8
G9
G10
DQ6
SA
A16
NC
H7
H8
H9
D6
A0
VSS
DQ1
H2
H3
H4
H5
H6
CE#f
OE#
DQ9
DQ3
DQ4
J2
J3
J4
J5
J6
J7
J8
J9
CE1#s
DQ0
DQ10
VCCf
VCCs
DQ12
DQ7
VSS
K3
K4
K5
K6
K7
K8
DQ2
DQ11
CIOs
DQ5
DQ14
L1
L5
L6
NC
NC
F10
DQ13 DQ15/A-1 CIOf
DQ8
NC
8 mm
11.6 mm
NC
20
D7
A19
D3
A3
D5
SRAM only
Shared
D2
RESET# CE2s
Flash only
L10
NC
M1
M10
NC
NC
73-Ball FBGA
Top View
Version 4.2, November 1, 2002
FBGA User’s Guide
Chapter 5:
Daisy Chains
Daisy Chains are primarily requested by OEMs to perform assembly evaluations. Prior to production,
an OEM will generally solder daisy chain samples on to a daisy chain PCB and perform Open/Short
testing to check for misalignments. This test will help OEMs characterize its assembly process and
equipment prior to full production. Daisy Chains are also used in Second Level Solder-Joint Board
Reliability studies. The daisy chain samples are assembled onto the matching PCB and subjected to
temperature cycling in an oven. Board Level Reliability tests are tools to help predict and measure the
expected life of a packages. For more in depth information on Second Level Solder-Joint Board
Reliability, please refer to “Reliability Evaluation Of Chip Scale Packages” by Ranjit Gannamani,
Viswanath Valluri, Sidharth, and MeiLu Zhang (see “Article Reprints”). For more in-depth
information on Daisy Chains please refer to the “Daisy Chain Samples Application Note”. Both are
listed in the Appendices.
Version 4.2, November 1, 2002
21
FBGA User’s Guide
Figure 5-1. FBGA 16 Mbit Daisy Chain Schematic (Top View)
6
5
4
3
2
1
A
B
C
D
E
F
G
H
Figure 5-2. FBGA 16 Mbit Board Layout (Top View)
6
5
4
3
b
2
1
a
A
B
C
D
E
F
G
H
a and b are the input and output of the network for this device.
22
Version 4.2, November 1, 2002
FBGA User’s Guide
Figure 5-3. FBGA 32 Mbit Daisy Chain Schematic (Top View)
6
5
4
3
2
1
A
B
C
D
E
F
G
H
Figure 5-4. FBGA 32 Megabit Board Layout (Top View)
6
5
4
3
2
b
1
a
A
B
C
D
E
F
G
H
Notes:
1. a, b are the input and output of the network for the device.
2. c, d are the input and output of a separate network for the support balls.
Version 4.2, November 1, 2002
23
FBGA User’s Guide
Figure 5-5. FBGA 64 Mbit Daisy Chain Schematic (Top View)
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
Figure 5-6. FBGA 64 Mbit Board Layout (Top View)
8
7
6
5
4
b
3
2
1
d
a
c
A
24
B
C
D
E
F
G
H
J
K
L
M
Version 4.2, November 1, 2002
FBGA User’s Guide
Figure 5-7. FBGA 84-Ball Daisy Chain Schematic (Top View)
9
8
7
6
5
4
3
2
1
A
B
C
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Figure 5-8. Fortified BGA 84-Ball Board Layout (Top View)
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Figure 5-9. Fortified BGA 64-Ball Board Layout (Top View)
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Figure 5-10. Fortified BGA 64-Ball Daisy Chain Schematic (Top View)
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Figure 5-11. Fortified BGA 80-Ball Daisy Chain Schematic (Top View)
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Figure 5-12. Fortified BGA 80-Ball Board Layout (Top View)
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Chapter 6:
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FBGA Package Materials Descriptions
Table 6.1: FBGA-BT
Material Type
Thickness
(µm)
Material
Name
Young’s
Modulus (Pa)
CTE ppm/c
Poisson’s
Ratio
Mold Compound
530
SMT-B-1N
1.50E+10
1.60
0.25
Die Attach
25.4
QMI 536
1.24E+09
8.00
0.4
Silicon Die
254
Silicon
1.31E+11
2.60
0.28
Eutectic Solder
Ball
300
Sn/Pb 63/37
3.10E+10
2.40
0.4
Copper Metallization
27
Cu
1.21E+11
1.70
0.34
25.4
Gold
Pad Plating
13
NI
2.00E+11
1.34
0.31
Solder Resist
50
Epoxy Resin
2.75E+09
6.90
0.3
Substrate Core
200
BT resin
2.60E+10 (Ex = Ey);
1.10E+10 (Ez)
1.50 (CTEx = CTEy);
5.20 (CTEz)
0.11
Wire
FBGA-BT Ball Attach Detail
The ball attach for the FBGA-BT package used a 0.4 mm pad size and a soldermask opening of
0.25 mm, therefore it is soldermask defined. The ball size is 0.3 mm nominal. Note that Figure 6-1
shows ball-to-package attach, not ball-to-printed circuit board attach.
Figure 6-1. FBGA Package Ball Attach Detail
copper pad
(0.4 mm)
soldermask
opening
(0.25 mm)
ball size
(0.3 mm)
FBGA-BT
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FBGA Thermal Management
Thermal energy management is important in today’s rapidly changing microelectronics. To receive the
best possible performance of any electronic product, proper heat dissipation is crucial. The
temperature at which a microelectronic device operates determines among other things the speed and
reliability of the product. Proper thermal management is achieved when heat is transferred or
dissipated from the device to the system air, which is then vented out of the system. A few of the most
important factors affecting device operation temperature are power dissipation, air temperature,
package construction, and cooling mechanisms. The combinations of these factors determine the
device’s operation temperature.
How well FBGA packages dissipate heat can be measured or described by θJA, the junction to air
thermal resistance value.
Figure 6-2. Path of Heat Dissipation
<
TA
<
JT
DIE
θJA – Junction to Air
Referring to Figure 6-2, θJA describes the path of heat dissipation from the active circuit
surface of the die through the mold compound to the ambient air. The equations that govern
this model are:
θJA = ΨJT - ΨTA
ΨJT = (TJss – TTss)/Pd
ΨTA = (TTss - TAss)/Pd
ΨJT = Thermal characterization parameter from device junction to the top center of the package
surface (°C/W).
θJA = Package thermal resistance from the die junction to the ambient air (°C/W). θJA is a
measurement of the package internal thermal resistance as well as the conductive and convective
thermal resistance from the package exterior to the ambient.
ΨTA = Thermal characterization parameter from top surface of the package-to-air (°C/W)
TJss = The junction temperature at steady-state. (oC)
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TTss = The package (top surface) temperature, at steady-state, measured by the thermocouple,
infrared sensor, or fluoroptic sensor.
TASS = Temperature of Ambient Air at Steady State
Pd = Power (watts)
Table 6.2: Thermal Resistance Data
Pkg
Type
FBA048
FBA048
FBB048
FBB048
FBC048
FBC048
FGC048
FGB048
X
Pad Y Pad
Dim. Dim.
(mils) (mils)
281
281
330
330
319
319
354
354
200
200
212
212
315
315
315
236
Ext. Die
Num.
X Die
Dim.
(mils)
Y Die
Dim.
(mils)
Thermal
208
102
Thermal
Thermal
Thermal
Thermal
Thermal
Thermal
Thermal
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208
208
208
208
208
102
102
102
102
102
212
212
212
Pd
(mW)
ΨJ–T
θJMA
θJA
SPD
(°C/W) (°C/W) (°C/W) (LFPM)
770
790
806
815
821
95.8
1417
1437
1445
1453
1456
49.2
697
716
728
735
739
89
1439
1461
1469
1476
1480
46
878
901
917
926
933
78.8
2010
2044
2057
2069
2077
35.7
729
752
767
775
779
89.2
2412
42.5
Test
Code
14.1
0
200
400
600
800
1S0P
6.1
0
200
400
600
800
2S2P
10.5
0
200
400
600
800
1S0P
4.4
0
200
400
600
800
2S2P
5.3
0
200
400
600
800
1S0P
3.9
0
200
400
600
800
2S2P
32.2
30.6
29.4
28.5
0
200
400
600
800
1SOP
74.0
63.1
54.6
53.9
0
2S2P
81.6
71.0
65.8
62.3
45.5
43.6
42.2
41.4
74.0
65.2
59.8
56.9
42.0
40.3
39.0
38.1
65.4
56.9
51.9
48.7
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Table 6.2: Thermal Resistance Data (Continued)
Pkg
Type
X
Pad Y Pad
Dim. Dim.
(mils) (mils)
Ext. Die
Num.
X Die
Dim.
(mils)
Y Die
Dim.
(mils)
Pd
(mW)
ΨJ–T
θJMA
θJA
SPD
(°C/W) (°C/W) (°C/W) (LFPM)
FGB048
354
236
Thermal
102
212
1134
91
FBD063
528
315
Thermal
420
212
1042
1073
1090
1101
1109
64.5
5.2
51.1
44.2
39.8
37.1
Test
Code
0
1S0P
0
200
400
600
800
1S0P
Notes:
1. All measurement date are following SEMI G38-87 (in a wind tunnel), unless marked.
2. TEST CODE describes test PCB. “2 signal layer+2 power layer” or “1 signal layer+0 power layer”
3. For more information on Thermal Management please refer to “Memo on ΨJ-T Case level Thermal
Parameter” in the Appendix.
4. θJMA = Theta of junction to moving air.
5. SPD (LFPM) = Speed of moving air, in terms of “Linear Feet Per Minute”.
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Chapter 7:
Board Design and Layout Considerations
General Design Considerations
One of the first decisions to be made when designing boards for chip scale packages is whether it will
be possible to use conventional PCB technology and design rules, or whether microvia technology will
be necessary. Recently, microvia HDI (High Density Interconnects) boards have been adopted in
several volume applications, particularly in cell-phones and camcorders, and the prices of microvia
boards have been falling quickly. HDI are defined as having vias with a diameter less than 0.006 inch
on pad size of 0.014 inch or smaller. However they are still more expensive. Measured on the basis of
price per unit area per metal layer, microvia boards are at least twice as expensive as high-density
conventional multilayer PCBs, even with blind and buried vias. Furthermore, there is also the question
of availability: it may not be easy to find suppliers with production capacity for microvia boards.
It is for this reason that a pitch of 0.8 mm has been chosen for AMD’s FBGA. As shown in the next
section, single-layer routing for Flash Memory FBGA can be accomplished with line and space widths
of 0.005 inch or more. Because of the relatively low lead count, this can be done in one layer, but if
desired, connections down to inner layers can be accomplished through interstitial vias.
Solder-Mask Defined Versus Non-Solder-Mask Defined
There has been much discussion about the relative merits of solder-mask defined (SMD) and nonsolder-mask defined (NSMD) lands for attaching area array packages such as conventional BGA and
fine pitch BGA. AMD’s FBGA can be used with either, but there are two important benefits of NSMD
pads. One is that smaller copper pads can be used, thus providing more generous clearance for the
routing channels. (Another is that the solder can wet around the sides of the pad during reflow (see
Figure 7-1) thus providing a stronger joint.)
Figure 7-1. Solder Wetting Around Pad During Reflow
Copper attachment pad
Note that if the kind of wetting shown in Figure 7-1 is desired, it is important to provide sufficient
clearance of solder mask around the pad. The PCB supplier may consider the edge of the solder mask
touching the edge of the pad to be acceptable, however, this condition would prevent the solder from
completely wetting the side of the pad.
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PC Board Surface Finish
Another design consideration is the selection of the surface finish for the board. While hot air solder
leveled (HASL) boards have been successfully used for FBGA, it is generally felt that the domed
shape of the pads makes it more difficult to achieve consistent assembly yields. On the other hand,
excellent yields have been achieved with both Ni/Au plated pads and also with bare copper pads
coated with organic solderability preservatives (OSP). In the case of Ni/Au plated pads, it is important
to control the plating quality to prevent embrittlement of the solder joint. This can occur if the gold is
too thick; gold thickness of 5 mils maximum is recommended. There has been some concern in the
industry that certain kinds of nickel plating can cause embrittlement—your PCB supplier should be
able to give advice on this subject.
Recommended Board Design Dimensions
Figure 7-2. Recommended Dimensions for the AMD 0.30 mm Solder Ball
Package Side
Package side is mask defined
Solder wets only the pad
A
C
B
Printed Circuit Board
Recommended Design Value
Dimension
54
Function
0.30 mm
Solder Ball
0.35 mm
Solder Ball
0.60 mm
Solder Ball
A
Solder Mask Opening
on the Package
0.25 ± 0.03 mm
0.30 ± 0.03 mm
0.50 ± 0.03 mm
B
Copper Pad Dimension
0.23 ± 0.01 mm
0.27 ± 0.015 mm
0.40 ± 0.03 mm
C
Copper Pad to
Solder Mask Clearance
0.075 ± 0.025 mm
0.075 ± 0.025 mm
0.075 ± 0.025 mm
—
Trace Width
0.125 ± 0.25 mm
0.125 ± 0.25 mm
0.125 ± 0.25 mm
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Routing Considerations
Figure 7-3. Example of 48-Ball Single Layer Board Routing
Trace to Pad Gap
0.007 in. (0.175 mm)
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Figure 7-4. Example of 63-Ball Single Layer Board
Routing Recommendation
Note: Recommended dimensions are the same as the 48-ball FBGA.
Figure 7-5. Example of Interstitial Via Design for High Ball Count Packages
Pad Pitch
0.800 mm
PAD
PAD
Pad Diameter
0.21 to 0.24 mm
Via Diameter
0.36 to 0.41 mm
VIA
Via Capture Pad Diameter
0.56 to 0.61 mm
Pad to Pad Diagonal Pitch
1.132 mm
PAD
PAD
Pad to Via Capture Pad Gap
0.20 mm
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Chapter 8:
Component Qualification Testing
AMD has one of the highest reliability standards in the industry. Beginning from wafer sort to shipping
of products, AMD has implemented vary stages of testing to ensure high quality and reliability.
Samples are subjected to accelerated stress tests.
The advantages of accelerated stress testing are that these tests use fewer parts and can make failures
occur faster. The stress levels used for these tests are more severe than that seen in the field with welldesigned tests resulting in the same failure mechanisms. Component level testing includes:
1. Preconditioning (Moisture Level Testing)
2. Temperature Cycling
3. Highly Accelerated Stress Test (HAST)
4. Thermal Shock
5. Data Retention Bake
6. High Temperature Operating Life (HTOL)
7. Latch-up
8. Electrostatic Discharge (ESD)
Preconditioning
The Moisture Level Testing is modeled after JEDEC/IPC Standard J-STD-020A. This test is designed
to determine the safe environmental conditions for product exposure, thus reducing the risk of
moisture induced damages. Moisture damages may include, delamination, package cracks during
reflows of board assembly, and “popcorn” effects.
There are six level of moisture sensitivity (See Table 8.1). Products are tested at Level-1 conditions, if
fail, the next higher level is tested until it passes. The only difference between each level is the
parameter of the moisture soak (also know as preconditioning).
There are 3 basic components:
1. 24 hour dry bake at 125°C
2. Preconditioning: Moisture storage parameters depending on JEDEC Moisture Sensitivity Level at
which the package is being qualified (See Table 8.1).
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Table 8.1: Moisture Sensitivity Levels
Soak Requirements
Floor Life
Standard
Accelerated Equivalent
Level
Time
Conditions
Time
(Hours)
Conditions
Time
(Hours)
Conditions
1
Unlimited
≤ 30°C/85% RH
168
85°C/85% RH
2
1 Year
≤ 30°C/60% RH
168
85°C/60% RH
2a
4 Weeks
≤ 30°C/60% RH
696
30°C/60% RH
120
60°C/60% RH
3
168 Hours
≤ 30°C/60% RH
192
30°C/60% RH
40
60°C/60% RH
4
72 Hours
≤ 30°C/60% RH
96
30°C/60% RH
5
24 Hours
≤ 30°C/60% RH
48/72
30°C/60% RH
6
6 Hours
≤ 30°C/60% RH
6
30°C/60% RH
3. Three exposures to conditions to simulate passage through IR Convection Reflow. The first two
passes are intended to simulate the assembly of a double-sided board, and the third pass to
simulate a rework operation—as follows.
Ramp-up rate: +3°C/second max.
Temperature maintained at 125 ±25°C: 120 seconds max.
Time at maximum temperature: 10–20 seconds
Maximum temperature: 235+5/–0°C
Ramp-down rate: –6°C/second max.
Temperature Cycling
Temperature cycling is designed to simulate stress that the device may experience at temperature range
of –40°C to 150°C for 1000 cycles, at a rate of 3 cycles/hour.
HAST
Highly Accelerated Stress Test (HAST) is design to accelerate possible corrosion, delamination,
possible wirebond failure, and intermetallic growths. HAST is performed at constant temperature and
relative humidity for a duration of time. Example: 110°C/85% unbiased for 264 hours.
Thermal Shock
Thermal shock test the integrity of the device under extreme temperate gradients.
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Data Retention Bake
This test ensures that the device loses no data. Test is performed at constant temperature with a specific
duration, example, 150°C for 168 hours.
HTOL
High Temperature Operating Life (HTOL) is sometimes refer to as Infant Mortality. This test is used to
weed out any early life failures and is typically performed for 168 hours at 150°C.
Latch-up
To withstand accidental shorting, all the device pins must meet the specification requirements to
withstand up to 200 mA stress from –1 V to VCC + 1 V.
ESD
Electrostatic Discharge (ESD) test the sensitivity of the device. Two kinds of ESD tests are:
HBM: Human Body Model simulates the ESD event from a human finger to a pin
CDM: Charge Device Model simulates the spark between a single pin of a charged leadframe and a
metallic ground.
Component level testing consists of but is not limited to the above accelerated tests. As it is not
feasible to monitor the reliability of each device types that AMD produces, device representative and
extend of test are selected based on complexity of wafer fabrication process and package type.
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FBGA-BT Component Level Test Results
Package Qualification Data—Contingent Release
Package:
Fine Pitch BGA (FBGA-BT)
Package Body Size:
8 x 9 mm
Product:
Am29LV160, 16 Mb Flash
Test
Preconditioning
16 Mb FBGA-BT 8 x 9 mm package
0/448
JEDEC Level 3
235+5/-0 degrees
Temp cycle (-40 to 150°C)
T = 1000 cycles
0/150
HAST (110°C/85%) unbiased
T = 264 hrs
0/150
Thermal Shock
T = 15 cycles
0/32
Data Retention Bake
T = 168 hrs
0/195
HTOL
T = 500 hours
0/150
Latch-up
Pass
ESD-HBM
±1.1 kV
60
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Chapter 9:
Board Level Characterization Studies
As part of an internal characterization study and ongoing product improvement program, AMD has
conducted board-level testing of the FBGA package for Flash memory.
The testing includes copper lead frame TSOP as a benchmark. As of late January 1999, the results are
as follows.
16 Mb FBGA-BT (ASE)
16 Mb TSOP I 48-Pin
Test: 0/100°C
Test: 0/100°C
Cycles completed: 7847
Cycles completed: 7847
Sample size: 54
Sample size: 40
Failure #
Cycle #
Failure #
Cycle #
1st
5800
1st
5560
2nd
6521
2nd
5708
3rd
6581
3rd
5868
4th
7312
5th
7512
6th
7512
7th
7662
AMD intends to continue the testing until 63% failures occurs or until 9,000 cycles are completed,
whichever occurs sooner.
Experimental Design and Procedure
Board Design
CSP test boards were designed to have six packages (of one package type) on each board, to ensure
adequate spacing between adjacent packages. Space considerations limited the TSOP boards to four
TSOPs per board. On each board, half the packages were oriented at 90° to the other half. These
precautions ensure that the data collected is free of any effects of location / orientation.
All the packages have a daisy chained die in them. The daisy chain circuit is completed on the board
level so that each package consists of a single net. Any failure on any solder ball can be immediately
captured as a break in the daisy chain.
The board is 20 mils thick, which replicates the construction of a standard PCMCIA card.
Board Fabrication
Standard printed circuit board (PCB) processes were used in the fabrication of the boards.
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Materials
Most of the laminates for PCBs in the industry are produced using epoxy resins. The choice of epoxy
resin is made because of its outstanding electrical, mechanical, and thermal properties. FR-4 epoxy
fiberglass laminate is the standard for all high technology and professional electronic assemblies, and
is the material selected for this study.
Design Parameters
Pad defined land pattern for the CSPs was chosen in order to achieve a good interface between the
solder balls and the PCB pads. The circular pad has a diameter of 12 mils, and is dipped with eutectic
63Sn/37Pb solder with thickness of 0.5 to 0.8 mils. The clearance (or spacing) between solder mask
and pads is 3 mils; and the registration is +/- 2 mils. No solder mask is allowed on the pads. Liquid
photo imageable solder mask is coated over base Copper with maximum thickness of 3 mils. 5 mil
nominal trace width is used for all trace routing.
Assembly of Packages
The test boards were not panelized during assembly. Only one piece of board was on each panel.
Fixtures were used at all stages of the process, including printing. The boards were taped onto the
fixtures using Kapton tape. No clean process was used for this study because the stand off height for
CSPs is very low, and cleaning and drying under the CSP package could lead to contamination.
Solder Paste Screen Printing
DEK 265Lt screen printer with 300 mm metal squeegee was the equipment used for the solder paste
printing process. LR737 rosin, a no-clean paste from Alpha Metals was used for the study. It is
designed for stencil application in surface mounting process where post reflow cleaning is not
required. It has mesh size of –325, which is equivalent to a particle size of less than 45 µm diameter.
The key criteria of stencil performance are vertical wall straightness, wall smoothness and dimensional
precision. Laser cut stencils were used, since the laser cutting processes can produce stencils with
smooth and straight vertical walls.
While screen printing solder paste, the stencil thickness and aperture dimensions are combined to
achieve a balance between printing resolution and the avoidance of either starved solder joints or pad
bridging. The stencil was designed to have a thickness of 3 mils and aperture of 12 mils in this study.
During the solder printing process, visual inspection for smear, slump, missing, and bridging is
performed for each board. Paste height at random locations is measured through scanning laser
microscopy (LSM) for one of every five boards. The average paste height is controlled at 3.6 mils with
deviation of 0.3 mils.
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Convection Reflow
The Heller 1800, a forced air convection reflow system was used in the assembly of the boards.
High concentrations of Oxygen (if using air reflow) can degrade the components due to oxidation
when they are at elevated temperatures. In particular, the problem of combustion of the flux in air gives
rise to only a small available process-temperature window for the reflow process. Using Nitrogen can
significantly eliminate the oxidation of the parts and extends the available process-temperature
window for the test boards and fluxes. Therefore, Nitrogen was used for the reflow process.
AMD preferred to control the Oxygen level below 20 ppm during the reflow process. However, there
was no Oxygen analyzer available at the contractor manufacturer site to measure the actual Oxygen
level when processing AMD test boards. We can only state at this time that the maximum Oxygen
level was 100ppm during reflow.
The reflow profile characteristics were as follows:
o
o
o
o
o
Ramp to 110°C with rate of 1.2°C/sec.
Dwell between 110 and 135°C for 90 seconds.
Maintain time above liquidus (183°C) for 45 seconds.
Reach peak temperature at 213 to 215°C.
Cool down with ramp rate of 1.5°C/sec.
Stress Testing
The assembled boards were subjected to temperature cycling. This is the appropriate stress test to
accelerate the wearout failure mechanism being investigated which is solder joint fatigue, primarily
driven by coefficient of thermal expansion (CTE) mismatches.
The 0/100°C temperature cycling range is the most commonly used test condition in the industry for
the board level reliability assessment of CSPs and it accelerates the correct failure mechanism. It is
also probably going to be the future High Density Packaging Users Group (HDPUG) standard, and
there is consensus among North American users and manufacturers for this test condition.
The exact temperature profile used was:
o
o
o
30 min cycles
10 min ramp up/down
5 min soak at hot and cold temperatures
This profile is again consistent with the future HDPUG standard for CSPs.
Test Procedure
The following is a brief description of the various steps involved in carrying out the board level
temperature cycling experiment.
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Initial Resistances / Harnessing
The initial resistance values of each of the nets (each package forms a single net) being monitored are
recorded. These resistance values serve as the baseline. Any packages that are open at Time-Zero are
not considered in the experiment. This can occur due to manufacturing or assembly defects. In this
study however, there were no Time-Zero failures. The individual boards are then harnessed, so that
they can be connected to the event detection equipment. Harnessing is essentially the soldering of
Teflon coated ribbon wire to the end connectors on the test boards.
Temperature Cycling Chamber Profiling
This is done to ensure a uniform temperature across the different boards in the chamber. The Fluke
Hydra Data Bucket is used to collect the thermal mapping data. Measurements are made on three
boards (top, middle, and bottom). On each board, measurements are made at three locations, i.e. the
two sides and the center. These precautions ensure that all the boards are subjected the exact
temperature cycling profile conditions.
Event Detection / Continuous Monitoring
The AnaTech LY515 (Analysis Technology) 256 channel event detector is used to monitor the nets in
real time. Event detectors detect resistance spikes over some preset resistance level. Any instance of
measured resistance value exceeding the threshold resistance value shall be considered as OPEN. An
OPEN followed by 10 additional OPENS within 10% of the time of the first OPEN shall be considered
as a FAILURE and the TIME TO FAILURE shall be the time at which the first OPEN occurred. This is
to avoid any measurement glitch or noise.
Test Strategy
Data collected includes the number of failures, if any, cycles to failure and their location (specific
board, specific net, etc.). It is intended to continue the tests to approximately 63% failure. At the
completion of the testing, the failed units will be analyzed by microsectioning to confirm the validity
of the failures.
64
Version 4.2, November 1, 2002
FBGA User’s Guide
Chapter 10: Miscellaneous
Shipping Container Information
Up to date shipping container information for the FBGA package can be found at the AMD web site:
IC Packages and Packing.
http://www.amd.com/products/packaging/toc.html
Sockets for FBGA-BT Packages
Vendor
SOCKET
FBGA 6x9 mm
Wells
Open Top # 703-1048-07
FBGA 8x9 mm
Wells
Open Top # 703-1048-04 Rev A
Yamaichi
Open Top # NP351-04878 Rev C
FBGA 8x14 mm (63 Balls)
Wells
Open Top # 703-1063-01
Yamaichi
Open Top # NP351-06377-N
* Closed top socket may be available. Contact socket vendor.
Version 4.2, November 1, 2002
65
FBGA User’s Guide
FBGA Package Marking
2 Spaces
LOGO
8 Spaces
@97-AMD
DEVICE DESIGNATION
Year
Week
XX
YY
Assembly Loc.
Lot Info
Q
ZZZ
Fab/Technology
Definition
Architecture
and Voltage
L = LV
D = DL
F=F
S = DS
Density and
Sector Org.
400
800
017
160
162
163
033
322
323
640
Boot or
Uniform
Technology
B = 0.32µ m/CS39S
C = Thin Oxide 0.32 µ m/CS39LS
D = 0.23 µm/CS49S
T = Top
B = Bottom
U = Uniform
Speed
(ns)
Temp.
Range
Voltage Range
55
70
80
90
12 = 120
15 = 150
R = Regulated
V = Full
C
I
E
FBGA Package Designators
Fine-pitch BGA
6 x 8 mm
WA
6 x 9 mm
WB
8 x 9 mm
WC
8 x 14 mm
WD
8 x 15 mm
WG
Fortified BGA
11 x 13 mm
PA, PB, PC
10 x 15 mm
PE
11 x 12 mm
WH
6 x 12 mm
WM
Note: These package codes are not marked on the package — for ordering purposes only.
66
Version 4.2, November 1, 2002
FBGA User’s Guide
Appendix A: Article Reprints
Version 4.2, November 1, 2002
67
FBGA User’s Guide
Reliability Evaluation of Chip Scale Packages
RELIABILITY EVALUATION OF CHIP SCALE PACKAGES
Ranjit Gannamani, Viswanath Valluri, Sidharth, and MeiLu Zhang
Advanced Micro Devices
Sunnyvale, California
ABSTRACT
This paper evaluates various Chip Scale Packages (CSP's)
with respect to board level reliability under accelerated
temperature cycling stress tests. The solder joint reliability
of three different types (based on substrate material) of Fine
Pitch Ball Grid Array (FBGA) packages and the
MicroBGA package is compared. The results are analyzed
using Weibull data analysis and extrapolated to low
cumulative percentage fails. The effect of package and
board design parameters such as solder ball size and board
thickness is also presented.
JEDEC FBGA specification. Consequently, the FBGA-BT
uses 0.3mm solder balls while the FBGA-PI uses 0.4mm
solder balls.
The differences between the physical
dimensions of the FBGA-Cer and FBGA-BT are minimal.
MOLD COMPOUND
DIE
Key words: CSP, BGA, FBGA, solder joints, reliability.
INTRODUCTION
The goal of smaller and portable electronic products is
driving the development of CSPs. CSPs are close to the die
size and are much smaller than conventional packages. In
8Mb density Flash memory for example, a TSOP48 (Thin
Small Outline Package) measures about 18.4mm x 12mm
whereas a comparable CSP (FBGA) would measure only
6mm x 9mm.
Often, different CSPs offer similar reliability at the
component or package level. Once they are mounted on
boards, their ‘second level’ or ‘board level’ reliability could
however be very different, and is based on the unique
material set and construction of each package type. This
study was undertaken to evaluate (i) the board level
reliability of some CSPs of different construction, and (ii)
the effect of package and board design parameters such as
solder ball size and board thickness.
PACKAGES EVALUATED
The following packages were evaluated: (i) FBGA with
Polyimide (PI) tape substrate, or FBGA-PI, (ii) FBGA with
BT (Bismaleimide Triazine) substrate, or FBGA-BT (BT is
the rigid epoxy glass laminate used in the conventional
plastic ball grid arrays), (iii) FBGA with ceramic substrate,
or FBGA-Cer, and (iv) MicroBGA. Each package has a
different material set and structural construction.
0.35 mm
standoff
0.40 mm Ø
Ball
0.80 mm
Pitch
Figure 1. Cross-section of FBGA-PI
Au Bond Wire
Mold Compound
DIE
BT Resin Substrate
0.25 mm
standoff
0.80 mm pitch
0.30 mm Ø
Ball
Figure 2. Cross-section of FBGA-BT
FBGA-PI
Ball size
0.4mm
Solder
eutectic
Substrate thickness
0.08 mm
Substrate material
Polyimide
Die thickness
0.3 mm
Avg Pkg height (measured)0.96 mm
when mounted on boar
FBGA-BT
0.3mm
eutectic
0.36 mm
BT resin
0.26 mm
1.07 mm
FBGA-Cer
0.3 mm
eutectic
0.35 mm
Alumina
0.26 mm
1.18 mm
Table 1. Differences in FBGA construction
Figure 1, Figure 2 and Table 1 illustrate the key differences
between the various FBGAs. The FBGA-PI uses a thin
0.08mm PI tape substrate, while the FBGA-BT uses a
relatively thick 0.36mm BT substrate. Both packages
conform to the same overall package height of ≤ 1.2mm,
which is the maximum package body height specified in the
68
The basic construction of these FBGA packages is to some
extent similar to that of conventional ball grid arrays. The
MicroBGA (Figure 3) however has a unique construction.
It uses a compliant elastomer material between the die and
the polyimide tape. TAB type beam leads are bonded onto
Version 4.2, November 1, 2002
FBGA User’s Guide
the die, and the die is ‘face down’ and exposed on the back
side.
Cu Interconnect
Elastomer
Encapsulant
DIE
1.00 mm MAX
Adhesive
0.23 mm
PolyimideTape (50um)
Solder Ball (63/37PbSn)
Pitch: 0.75 mm.
PI via: 0.33 nom.
Ball Dia: 0.35 nom.
Figure 3. Cross-section of
MicroBGA
TEST BOARDS
Each FR-4 test board measured 3.5" x 2". Both 20mil and
62mil boards were used in this study. Six CSPs were
assembled on each board (Figure 4). On each board, half
the packages were oriented at 90 degrees to the other half,
and precautions were taken in the layout of the board to
ensure that the data collected is free of any effects of
location or orientation. The boards had Non Solder Mask
Defined pads with a HASL finish. Standard best practices
such as no-clean solder paste, laser cut stencils, and
Nitrogen convection reflow were used in the assembly of
the CSPs on the boards. Each CSP contains a daisy chained
die. The daisy chain circuit is completed on the board such
that each package consists of a single net through all the
joints.
Figure 4. A typical CSP test board
TEMPERATURE CYCLING
A 0°C to 100°C, 30 minute single chamber air-to-air
temperature cycling profile with 10 minute ramps and 5
minute dwells was used. This is one of the commonly used
test profiles in the industry. An event detector was used to
monitor the daisy chained test boards in real time. The
event detector was set to record resistance spikes greater
than 300 ohms for 200 nanoseconds. Any spike greater
than 300 ohms was considered as "open". A package was
considered failed when the first open was followed by 10
additional opens within 10% of the time of the first open.
The thermal cycling chamber was profiled before starting
the test, to ensure a uniform temperature across the
Version 4.2, November 1, 2002
different boards in the chamber. Wherever possible, the
tests were continued to 63% fail or greater.
MODELING TECHNIQUE
After temperature cycling was completed, the failure data
was fitted to a Weibull statistical distribution. The Weibull
parameters α (N63.2%) and β (slope) were obtained for the
test, and the data extrapolated to a low cumulative failure
percentage (100 PPM). The test data was then extrapolated
to field use conditions and the projected field life (at 100
PPM) calculated, in order to enable a more intuitive
comparison of the reliability of the different packages. The
Norris-Landzberg modified Coffin-Manson equation [1]
was used to calculate the acceleration factor. The two
example field conditions used in this paper are shown in
Table 2.
Example Field Conditions
Temperature Swing
40 C / 60 C
-15 C / 25C
Cycles / Day
1
1
Table 2. Example field conditions
RESULTS
Extensive temperature cycling data on the different CSPs
was collected.
The test program included various
experimental splits with different combinations of package
and board types. For clarity, the presentation of the results
has been divided into the following five sections.
(A) Comparison of Different Package Types
The Weibull plots for the 8x9mm FBGA-BT, 8x9mm
FBGA-PI, MicroBGA, and 6x9mm FBGA-Cer are shown
in Figure 5. Here, the FBGA-Cer CSP contains the 8Mb
density Flash device, while the other three CSPs contain the
16Mb density Flash device. This data was collected on
20mil (0.5mm) boards under 0/100 degC cycling.
The Weibull slope and cycles to 63.2% failure (N63.2%)
are shown in Table 3. The Weibull plots show that the
FBGA-BT and MicroBGA packages have significantly
larger N63.2% values than the FBGA-PI and FBGA-Cer
packages. It is too be noted that the initial MicroBGA
failures are not solder joint failures and a discussion follows
in a later section. From Figure 5 and Table 3, it can be
seen that the slope of the distribution is different for various
sets of data and hence a direct comparison of N63.2% fails
is not feasible for the whole set of data. It is pertinent to
compare the results at low PPM cumulative percentage
failure mark. Hence, the 100 PPM number, which seems to
be a very conservative number accepted in the industry, was
chosen. Figure 6 shows comparative life projections in the
two example field conditions defined in Table 2.
In termsof board level reliability, it can be seen from Figure
6 that the FBGA-BT and MicroBGA ranked much higher
than the other packages. Both these packages demonstrated
69
FBGA User’s Guide
different bars is a true representation of the comparative
reliability of the different CSPs at the board level.
Weibull plot for various CSPs
99.99%
Ln(Ln(1/(1-F(x))))
2.3
63.2%
0
10%
-2.3
8x9 FBGA-BT
8x9 FBGA-PI
1%
-4.6
6x9 FBGA-Cer
uBGA
0.1%
-6.9
4.6
(100)
6.9
(1000)
9.2
(10000)
11.5
(100000)
Ln(Cycles)
Figure 5. Weibull plots for variousCSPs
Package
N63.2 (cyc)
Beta
# fails / SS
8x9 mm FBGA-BT
8x9 mm FBGA-PI
6x9 mm FBGA-Cer
MicroBGA
11586
2295
1918
9240
5.0
3.9
5.2
4.8
39 / 48
52 / 60
46 / 60
35 / 60
Table 3. Weibull parameters for various
CSPs
Projected Life (yrs)
Comparison of packagesat 100 PPM cume fail
40C / 60C, 1 cyc/day
100
80
60
40
20
0
uBGA
8x9mm
FBGA-BT
8x9mm
FBGA-PI
The higher reliability of the FBGA-BT package can be
attributed to the thick and rigid BT substrate isolating the
silicon die (low CTE) from the solder joint and the board.
In the case of the MicroBGA package, the compliant
elastomer material isolates the silicon die from the solder
joint and the board, and contributes to the high reliability.
The comparatively lower reliability of the FBGA-PI is due
to the fact that the package construction is dominated by
the low CTE Silicon die. As seen in the package cross
section, it is only the die attach layer and the Copper traces
on the PI substrate that separate the solder ball from the
die. The PI tape itself is not in the path; it has openings
that define the pads for ball attachment. The lower
reliability of the FBGA-Cer packages was expected since
there is both global and local CTE mismatch with the FR-4
board. A potential use of this package might be on
Ceramic boards, but that issue is not discussed in this study.
On completion of the tests, failure analysis was carried out
on a sample of the test vehicles. Figure 7 shows microsections of the FBGA-PI and FBGA-BT test boards. Solder
joint cracks at the interface on the component side are seen.
This is consistent with the classic BGA solder joint failure
mechanism that is well documented in the literature.
Figure 8 shows the results of the failure analysis on some of
the initial MicroBGA failures. A lifted beam lead was
detected. The isolation of the low CTE die by the compliant
elastomer results in the beam leads absorbing most of the
cyclic fatigue stress in temperature cycling.
6x9mm
FBGA-Cer
Projected Life (yrs
Comparison of packagesat 100 PPM cume fail
-15C / 25C, 1 cyc/day
100
80
60
40
20
0
Figure 7. Failure analysis of FBGA-PI (left) and FBGA
BT (right). Cracks on component side.
uBGA
8x9mm
FBGA-BT
8x9mm
FBGA-PI
6x9mm
FBGA-Cer
Figure 6. Field life projections
lifetimes considerably higher than the requirements of most
customer applications. The 8x9mm FBGA-PI and 6x9mm
FBGA-Cer data translated to lower field life projections.
The life projections in “years” shown in Figure-6 are for
those two specific field conditions only. The estimation of
lifetimes would vary depending upon the specific field
conditions and the model used to calculate the acceleration
factors between test and field.
However, the key
observation to be made is that the relative size of the
70
Figure 8. Failure analysis of
MicroBGA
Version 4.2, November 1, 2002
FBGA User’s Guide
In these experiments, the FBGA-BT packages (0.3mm
solder balls) were assembled on test boards that were
initially designed for the FBGA-PI package (0.4mm solder
balls). The test boards were designed to have 0.3mm pads
that matched the 0.3mm openings in the PI tape (where the
solder balls are attached) of the FBGA-PI package. The
corresponding opening in the solder mask of the FBGA-BT
package is 0.25mm. It is hence expected that the use of test
boards designed or optimized for the FBGA-BT package
could result in even better FBGA-BT data than that
presented here.
(B) Effect of Package Body Size in FBGA-PI
The FBGA-PI test discussed in the earlier section was on
the 8x9mm body size, which is the package for the 16Mb
density Flash product. The 6x9mm FBGA-PI, the package
size for the 8Mb density device, was also put on the 0/100
degC test. In this case also, 20mil test boards were used.
Figure 9 shows the Weibull plots for both the 8x9mm and
6x9mm FBGA-PI packages.
The relevant Weibull
parameters are in Table 4 and field life projections in
Figure 10. As seen in the Weibull plots and the field life
projections, the larger 8x9mm package demonstrated a
lower lifetime than the 6x9mm package. This difference is
attributed to the larger package body size and the larger die
size of the 16Mb device, i.e. the domination of the low CTE
Silicon die is more pronounced in the larger package for
the higher density Flash product. Based on these findings,
it was anticipated that even larger packages for higher
density products (32/64Mb) would show poorer solder joint
lifetimes in the FBGA-PI package due to the same reasons.
0
99.99%
Effect of Package Body Size
Weibull plot for 6x9 mm and 8x9 mm FBGA-PI
Projected Life (yrs
40
30
20
10
0
6x9mm FBGA-PI
material, die attach compliancy, solder ball size, etc. The
package design variable evaluated here was solder ball size.
The solder ball size on the initial FBGA-PI package was
0.40mm nominal. This ball size was increased to 0.45mm
nominal. Though the ball size was increased, the overall
height of the package was maintained below 1.2mm. The
PI tape opening was increased from 0.3mm to 0.38mm.
The new test boards had 0.35mm pads. Based on industry
practice, this was deliberately maintained a little smaller
than the 0.38mm PI tape openings on the new FBGA-PI
package.
Figure 11 shows the Weibull plots for both the 0.4mm ball
and 0.45mm ball FBGA-PI packages.
The relevant
Weibull parameters are in Table 5. Figure 12 shows the
field life projections for the FBGA-PI packages with
0.40mm and 0.45mm solder balls. As expected, the use of
the larger solder balls results in an improved solder joint
lifetime.
63.2%
8x9 mm FBGA-PI with Larger Solder Balls
10%
-2.3
2.3
-4.6
-6.9
8x9mm FBGA-PI
Figure 10. Field life projections
1%
6x9 FBGA-PI
8x9 FBGA-PI
0.1%
4.6
(100)
6.9
(1000)
9.2
(10000)
11.5
(100000)
Ln(Cycles)
Ln(Ln(1/(1-F(x))))
Ln(Ln(1/(1-F(x))))
2.3
Comparison of packagesat 100 PPM cume fail
-15C / 25C, 1 cyc/day
0
99.99%
63.2%
10%
-2.3
-4.6
8x9 FBGA-PI 0.4 mm dia
ball
1%
8x9 FBGA-PI 0.45 mm
dia ball
-6.9
4.6
Figure 9. Effect of package body size in FBGA-PI
Package
N63.2 (cyc)
Beta
# fails / SS
8x9 mm FBGA-PI
6x9 mm FBGA-PI
2295
2685
3.9
6.0
52 / 60
38 / 60
Table 4. Weibull parameters for different body sizes
(C) Use of Larger Solder Balls on FBGA-PI
Design / package changes to improve the board level
reliability of the FBGA-PI were investigated. Design
parameters that may impact the board level reliability are
substrate material, substrate thickness, mold compound
Version 4.2, November 1, 2002
6.9
9.2
11.5
Ln(Cycles)
Figure 11. Use of larger solder balls on FBGA-PI
Package
N63.2 (cyc)
Beta
# fails / SS
8x9 mm FBGA-PI, 0.40 ball
8x9 mm FBGA-PI, 0.45 ball
2295
2424
3.9
5.5
52 / 60
40 / 60
Table 5. Weibull Parameters for solder ball size
From the Weibull plots it can be seen that it is challenging
to quantify the improvement due to the use of larger solder
71
FBGA User’s Guide
balls. While the N63.2% values are relatively close, the
different slopes tend to amplify the difference between the
two datasets, especially when projected to lower PPM. For
example, if a 1000 PPM criterion is used, the improvement
obtained (of 1.8X) is significantly lower than that shown in
Figure 12 (2.1X). To get an average picture of the whole
data the slopes from the two datasets were pooled to obtain
a common slope of 4.7, and an N63.2% fitted to both
datasets. Now comparing N63.2% values results in an
improvement of 1.13X with the use of larger solder balls.
From this analysis it is seen that even in a best case
scenario for the larger solder balls, the improved lifetime is
still lower than that of the FBGA-BT and MicroBGA
packages.
40
30
For the FBGA-BT package the results are preliminary as
the tests on 62mil boards are still in progress. Initial data
shows minimal difference as the failures obtained so far
have lined up on the existing data on the 20mil boards (see
Figure 14 and preliminary life projections in Figure 15).
It should also be noted that that the 62mil boards were
assembled at a different site. Hence, while these may not
be exact comparisons the information presented is still
useful to demonstrate that there is no significant difference
in the lifetimes projected even when the same packages are
assembled on thicker boards.
20
10
6x9 mm FBGA-PI on 20 mil and 62 mil boards
0
8x9mm FBGA-PI, 0.4 mm
ball
2.3
8x9mm FBGA-PI, 0.45 mm
ball
Figure 12. Field Life Projection
Ln(Ln(1/(1-F(x)))
Projected Life (yrs
Comparison of packagesat 100 PPM cume fail
-15C / 25C, 1 cyc/day
section) exists for these two sets of FBGA-PI data as well.
Using the technique of pooling to a common slope of 7 and
recomputing the N63.2% values, it is found that on an
average, the solder joint life on thinner board exceeds that
on the thicker board by 1.34X for FBGA-PI package. The
slope (beta) for the thicker board was higher than that for
thinner board, and so projections to a low PPM value
showed minimal difference (Figure 15).
0
(D) Evaluation of Test Vehicles built on 62 mil Boards
All the data discussed in earlier sections was collected on
test boards that were 20mil thick. Testing (0/100 degC
cycling) was also carried out on 62mil (1.6mm) boards to
evaluate the effect of these thicker boards on the solder
joint lifetimes. Figure 13 shows the Weibull plots for the
6x9mm FBGA-PI on both 20mil and 62mil boards. Figure
14 shows similar plots for the 8x9mm FBGA-BT package.
The relevant Weibull parameters are listed in Table 6. It
should be noted here that the FBGA-BT / 62mil board data
presented here is preliminary. This will be updated as
more failures are collected.
It can be seen from Figure 13 that the same challenge of
quantifying the difference (as outlined in the previous
72
63.2%
10%
-2.3
-4.6
-6.9
1%
6x9 FBGA-PI/20 mil
board
0.1%
6x9 FBGA-PI/62 mil
board
4.6
(100)
6.9
(1000)
9.2
(10000)
11.5
(100000)
Ln(Cycles)
Figure 13. FBGA-PI on 20 and 62mil boards
8x9 mm FBGA-BT on 20 mil and 62 mil boards
2.3
Ln(Ln(1/(1-F(x))))
It should also be noted that at 0.45mm, the solder ball size
is quite close to the maximum possible for the solder ball
array with a pitch of 0.8mm, in order to retain sufficient
room to route traces to internal solder balls. Additionally,
the eventual move to a 0.5mm pitch solder ball array
(necessitated by shrinking die sizes due to improved fab
processes, and the need for smaller form factor packages)
will make the use of a 0.45mm ball impossible. The
FBGA-BT package that currently uses 0.3mm solder balls
would be able to transition to a 0.5mm solder ball pitch
without requiring a change in ball size.
99.99%
0
99.99%
63.2%
10%
-2.3
-4.6
-6.9
8x9 FBGA-BT/20 mil
board
1%
8x9 FBGA-BT/62 mil
board
0.1%
6.9
(1000)
9.2
(10000)
11.5
(100000)
Ln(Cycles)
Figure 14. FBGA-BT on 20 and 62mil boards
Package
N63.2 (cyc)
Beta
# fails / SS
6x9 mm FBGA-PI, 20mil board
6x9 mm FBGA-PI, 62mil board
8x9 mm FBGA-BT, 20mil board
8x9 mm FBGA-BT, 62mil board
2685
1932
11586
11757
6.0
7.9
5.0
5.2
38 / 60
45 / 48
39 / 48
5 / 30
Table 6. Weibull parameters
Version 4.2, November 1, 2002
FBGA User’s Guide
Projected Life (yrs)
Effect of Board Thickness
Comparison at 100 PPM cume fa
-15C / 25C, 1 cyc/day
100
75
50
25
0
6x9 FBGA-PI,
20mil board
6x9 FBGA-PI, 8x9 FBGA-BT, 8x9 FBGA-BT,
62mil board
20mil board
62mil board
Figure 15. Evaluation on 62mil boards
(E) Temperature Cycling at -40 / 100
degC
A limited amount of data was also collected at the -40/100
degC, 30 minute cycle test condition on 20mil boards.
Table 7 is a summary of that data. The 8x9mm FBGA-BT
and the 8x9mm FBGA-PI packages were evaluated. The
test was terminated at 2507 cycles. At that point, there
were zero fails (0/60) of the FBGA-BT test vehicles and
extensive failures (49/60) in the FBGA-PI test vehicles.
While no field projections are included here, this
information again gives an indication of the relative
robustness of the two packages.
Test Condition: -40 / 100 degC
Cycles completed
Data
8x9 FBGA-BT
8x9 FBGA-PI
2507
No fails
out of 60
2507
49 fail
out of 60
First fail at:
n/a
754
Test status
Stopped
Stopped
still lower than that of FBGA-BT and MicroBGA
packages. Feasibility of using a 0.45mm ball size
would be challenged as migration to 0.5mm ball pitch
is made.
(iv) At 100 PPM no significant difference in the board level
reliability was detected for both the FBGA-BT and
FBGA-PI packages assembled on the thicker 62mil
boards when compared to those mounted on the 20mil
boards.
(v) Limited data at the -40/100 degC test condition
indicates the relative robustness of FBGA-BT over
FBGA-PI with respect to board level reliability, that is
consistent with the rest of the 0/100 degC data
discussed in this paper.
ACKNOWLEDGMENT
The authors would like to acknowledge Melissa Lee, John
Hunter, Bruce Schupp, James Hayward, and Ed Fontecha
for their guidance and support, Dave Morken for the SEM
analysis and Robert Dudero for cross-sectioning of the
samples.
REFERENCES
[1] K. Norris and A. Landzberg, IBM Journal of Research
and Dev, 13, pp 266, 1969.
[2] K. Ano, et al, “Reliability study of the chip scale
package using flex substrate”, SMI Proc, pp44-47, 1997.
[3] R. Darveaux, J. Heckman, A. Mawer, “Effect of test
board design on the 2nd level reliability of a fine pitch BGA
package”, Proc of SMI, pp 105-111, 1998.
[4] C.F. Coombs Jr., “Printed Circuits Handbook”,
McGraw Hill, NY, 1995.
Table 7. Board Level Reliability Data at –40/100
degC
test condition
CONCLUSIONS
(i) In the packages evaluated, the FBGA-BT and
MicroBGA demonstrated lifetimes considerably higher
than the FBGA-PI and FBGA-Ceramic packages.
These differences in board level reliability can be
explained by the differences in package construction
and material sets.
(ii) In the FBGA-PI package, the larger 8x9mm package
for the higher density 16Mb device (larger Silicon die)
demonstrated lower reliability than the 6x9mm
package for the 8Mb device. Based on this trend, it
was anticipated that even larger packages (for
32/64Mb) would show lower solder joint lifetimes in
the FBGA-PI construction.
(iii) The use of the larger solder balls (0.45mm vs. 0.4mm)
on the FBGA-PI package resulted in an improved
solder joint fatigue life. Even in the best case scenario
for the larger solder balls, the improved lifetime was
Version 4.2, November 1, 2002
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FBGA User’s Guide
FGBAs—The CSP of Choice for Flash Memories
THE CSP OF CHOICE
FBGAs
MSG
FOR FLASH MEMORIES
2000
a publication of the manufacturing services group
AMD RECENTLY PLAYED A
pivotal role in the emergence of
the FBGA (fine pitch ball grid
array) as the new chip scale package (CSP) of choice for flash
memory devices. This time two
years ago, the micro ball grid
array (µBGA) was the only CSP
available for downsizing from
the larger, traditional leaded
packages used for flash memories
(such as the thin small outline
plastic (TSOP) package). That
changed last year when AMD began offering an FBGA design that
afforded so many advantages, it
product applications (e.g., cellular phones, pagers, hand-held
computers, etc.). As this story
unfolds, you will see how AMD
persevered in the face of an established preference for Intel’s µBGA
to win overwhelming acceptance
of the FBGA as the preferred CSP
in these applications.
PACKAGE SIZE MATTERS
In applications where miniaturization is a priority, CSPs are a
❝ When it comes to
package technology for
flash memories,
AMD can do anything
that can be done. We have
the licenses, the technology,
and the ability.❞
Bruce Schupp, NVD product marketing
put a fork in the package roadmap
for flash memories in automotive,
telecom, and new consumer
74
crucial stepping stone on the way
to direct chip attach (DCA), in
which the die is bonded directly
Version 4.2, November 1, 2002
FBGA User’s Guide
Figure 1 shows the smaller size of CSPs
next to a comparable density TSOP.
to the end-use printed circuit board
(PCB). While DCA technology offers the ultimate in miniaturization, the infrastructure for it is not
established enough for DCA to be
cost competitive. Moreover, DCA
is not a viable option when the die
has been designed for wirebonded
interconnects (i.e., the bond pads
are located around the periphery of
the die), as is the case with all flash
memories in traditional leaded
packages. DCA is better suited for
die having the bond pads in an
array across the die surface, enabling the connections to be made
with flip-chip technology instead
of conventional wirebonding.
Figure 1 shows the smaller footprint of a CSP next to a comparable
density TSOP. The smaller form/fit
factor saves considerable board
space and provides a lower profile
– all of which is needed when trying to cram more memory capacity
onto ever smaller motherboards,
or in products striving to fit into
the palm of your hand.
acceptance of it was already established. AMD’s LV800 flash
family was initially offered in a
µBGA, and we shipped modest
quantities of it. But these early
µBGA package designs included
polyimide tape embedded with
solid gold traces for routing the
signals from the die to the external terminals, and this was too
costly. So we had the polyimide
tape replaced with a copper core
tape that had gold-plated copper
traces ("beam leads") instead of
solid gold. This flash gold was
bondable and kept oxidation from
growing, and the copper brought
the costs down. We ran into a
roadblock, however, when our
supplier was unable to produce
the copper core tape in sufficient
quantities. It was a roadblock that
soon proved to be a blessing in
disguise.
Faced with no reliable, costeffective CSP to offer flash customers, we turned to Fijitsu,
AMD's FASL business partner.
Fijitsu had an FBGA with a
polyimide tape substrate that
looked promising, so we got permission to adopt their package
technology. Besides being cheaper
than the µBGA, the FBGA construction was appealing because
the package size could remain the
same even if the die size became
smaller. To better understand this,
it helps to look at the configuration of an FBGA versus a µBGA.
µBGA CONSTRUCTION –
ONE DIE SIZE ONLY PLEASE
The µBGA package is not like a
standard IC package in which you
attach a die. It is a construction
that is built on top of the die, so
the package is nearly the same
size as the die itself. The crosssection drawing in Figure 2 shows
the die-down configuration, interconnected by gold-plated beam
leads to traces that route through
the polyimide tape to an array of
external solder balls.
This package construction presented a problem for AMD because of our die size. For many of
the popular densities of the time,
our die size was smaller than any
other flash manufacturer’s. While
this is good for keeping fab costs
down (more die per wafer), our
die size was too small to provide
room for the size of the solder
ball array while keeping the pitch
(the distance between the
centerlines of adjacent solder
balls) at a manageable 0.75 mm
for board assembly. Moreover,
even if our die could have fit initially, every time we implemented
a die shrink we would face the
NOT JUST ANY CSP WILL DO
In addressing the demand for a
flash memory CSP, AMD first
looked at the µBGA, since market
Version 4.2, November 1, 2002
Figure 2 shows a cross-section of the die-down configuration of a µBGA package.
75
FBGA User’s Guide
MSG
Figure 3 shows a cross-section of the die-up configuration of an FBGA package.
same size problem. Thus, with
die shrinks occurring regularly,
µBGAs are not an attractive CSP
solution for flash memories –
either for us or for our customers
– because the form/fit of the package must change with every die
shrink. This was becoming painfully apparent to several top-tier
OEMs who were attempting to
use the µBGA package for flash
memories.
FBGA CONSTRUCTION –
DIE SHRINK FRIENDLY
In the FBGA construction, the
die is wirebonded to a substrate
and then overmolded with epoxy,
a construction very much like that
of a standard BGA (see Figure 3).
The minimum package size winds
up being about 1.2 times the size of
the die, slightly larger than a comparable density µBGA. But this size
advantage wins no points when it
comes to die shrinks. Because of
the FBGA construction, it can do
what the µBGA cannot: accommodate a reduction in die size with
no change to the package dimensions. This renders a die shrink
transparent mechanically to both
AMD’s and our customers’ manufacturing lines – clearly, a winwin situation.
76
BUILDING INFRASTRUCTURE
For any new package technology, it is critical that there be a
supporting industry infrastructure. We already knew that in the
flash market OEMs want:
• the smallest, most powerful
flash memory they can get in a
package that has the largest
pitch;
• multiple supply sources;
• package designs that do not
change with every die shrink.
So we set our sights on qualifying the FBGA and on fortifying
the infrastructure for it, the latter
of which was no small task in a
market where the µBGA was already synonymous with CSP.
With no appreciable tooling or
reliability data available at the
time for the FBGA, we knew we
needed to tackle these four prerequisites to market acceptance:
• board level reliability;
• board level rework ability;
• socket suppliers;
• alternative supply sources.
Board Level Reliability
We began testing the reliability
of the FBGA after it was mounted
onto a PCB similar to those in use
by our major customers. We soon
learned that the substrate of the
FBGA – the polyimide tape – was
too thin to absorb the stress incurred from the different CTE (coefficient of thermal expansion)
rates of the silicon versus the PCB
(using FR4 material). When
heated, the PCB expands at a
much higher rate than the silicon, and the package substrate
has to manage this difference.
Although the polyimide substrate
proved reliable enough for many
applications, it did not meet the
long-lifetime reliability that is
needed in commercial and industrial outdoor applications, such
as in the telecommunications
infrastructure or automotive
environments.
■
Tape vs Rigid Substrate
While we were testing the tape
FBGA, we also evaluated an FBGA
design that had an organic substrate of BT (Bismaleimide Triazine) resin. Because this material
was thicker and had a CTE closer
to that of the PCB, it could better
manage the stress than could the
thinner polyimide tape. So we
switched. The results of the extensive tests on the board level
reliability performance can be
found in the white paper, “Reliability Evaluation of Chip Scale
Packages,” published in 1999 by
the following AMDers: Ranjit
Gannamani, Vis Valluri, Sidharth
Sidharth, and MeiLu Zhang. A copy
of this paper can be obtained from
MSD Engineering (x26415).
As for the µBGA, its board-level
reliability performance is comparable to that of the FBGA due to
the ability of its elastomer layer
to absorb the stress from the
different CTE rates. These reliability
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FBGA User’s Guide
MSG
results are also presented in the
white paper referenced earlier.
■
Board Level Rework Ability
and Socket Suppliers
NVD and MSD engineers
teamed up to familiarize boardlevel rework companies with the
FBGA package. They also worked
with socket suppliers, for those
customers who do programming
prior to system assembly, to arrange support for AMD's FBGA
package.
■
Version 4.2, November 1, 2002
THE FRUITS OF OUR LABORS
This infrastructure work took
about a year to come to fruition
and, because of AMD’s success in
this effort, FBGAs are now the
most preferred CSP package for
flash memories used in commercial and industrial applications. µBGA shipments still
outnumber FBGAs due to the top
two or three cellular telephone
OEMs using them in large quantities; however, the number of
OEMs now choosing FBGAs for
flash far exceeds those preferring
the µBGA. With AMD able to produce flash memory roadmaps
knowing what the package footprint will look like years in the
future, whether it be burst mode,
page mode, or random access types
of flash memory, even the OEMs
committed to µBGA are now wanting FBGAs for future designs.
Thanks go to the following
AMDers for their valuable contributions to this article and for
the instrumental roles they
played in bringing the industry
around to embracing the FBGA:
Bruce Schupp, Melissa Lee,
Ranjit Gannamani, Vis Valluri, and
Sidharth Sidharth.
▼
Alternative Supply Sources
NVD Marketing contacted
some of our competitors and
showed them footprints and
pinouts for our flash memory
parts. After negotiating some
pinout changes, NVD got their
commitment to support both the
µBGA and the FBGA pack-age
styles for the same flash memo-
ries. NVD also worked with the
industry-wide JEDEC JC-42.4
Committee to establish AMD’s
version of the FBGA pinout as an
official industry standard. Because of this, all FBGA packaged
flash memories manufactured in
the world today conform to the
AMD footprint. We are continuing to work with JEDEC for the
adoption of additional FBGA
footprints designed to accommodate future generations of very
high-density, high-performance
flash memories.
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FBGA User’s Guide
Memo on ΨJ–T, Case Level Thermal Parameter
MSD Engineering
Memo on Ψ J-T , Case Level Thermal Parameter
Introduction
A new thermal parameter has been developed by the EIA/JEDEC JC15.1 subcommittee on
thermal phenomenon in electronic packaging. The parameter is called ΨJ-T, (psi j-t) and is a
modification and replacement of the much abused junction-to-case thermal resistance,
θJC,
value for plastic packages. This memo outlines the history and physical description of θJC
measurements, and shows why they are poor performance indicators for plastic packages.
The ΨJ-T parameter is introduced and its use is explained.
History
θJC is a measurement that is used to describe the internal thermal resistance of a packaged
semiconductor device. Originally, the measurement was developed as a method of
calculating junction temperature (T J) from a known reference point on the outside of the
package. The natural place for this reference point is defined as "the shortest thermal path
from the junction to the outside of the package," which is also the best heat sinking surface.
In the days when the specification was generated, the mainstream package was the
ceramic DIP, which for the military, were mounted onto 'cold rails'; flat liquid cooled tubes
that contacted the bottoms of the DIPS in the application. These cold rails were held at a
constant temperature and served as a reference point for calculating T J.
The test method is performed by bringing the desired package surface to thermal
equilibrium, an isothermal case condition at some defined temperature, by using a large
cold plate or heat sink. The idea is to keep the external package temperature constant
while the device is powered up. Heating voltage and current are supplied to the device to
power up the die while keeping the package surface at the initial defined temperature.
When the device comes to steady-state temperature and power conditions, the junction
temperature is measured and junction to case thermal resistance is calculated using
equation (1).
θJC = TJ-TR/PD
(1)
where:
TJ = junction temperature
TR = reference temperature (case)
PD = Power dissipation
Heat Flow In Microelectronic Packaging
Heat flow in a hermetic package is well defined as illustrated in figure 1. In the diagram it is
seen that the die is attached to a ceramic substrate inside of a cavity. When the package is
assembled, the cavity is left intact, that is, only air or some other gas comes in contact with
the die surfaces not bonded to the cavity. Since the thermal conductivity of the ceramic is
1
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quite high when compared to air or other gasses, most of the heat generated (~90%) from
the circuitry on the die surface is conducted through the silicon and into the ceramic
substrate. The heat travels through the ceramic and is dissipated into the air or into a heat
sink. Some spreading occurs in the ceramic (at an approximate 45° angle), so the analysis
can be almost purely one-dimensional. This approach works well in any type of hermetic
package including PGAs, CQFPs, CBGAs, and other ceramic packages.
Die
Lid
Heat Flow
surface
Figure 1. Heat Flow in Hermetic Package
When plastic packages gained popularity, much of the thermal analysis was left intact, such
as the θJA (junction-to-air thermal resistance) parameter, and θJC. It was assumed, incorrectly,
that the junction-to-case value could be used in plastic packages to predict junction
temperature the same way it was used for hermetic packages. The problem with θJC for
plastic packages is fundamental, and it is easily seen how the physical construction of plastic
packages negates the use of this simple parameter.
Figure 2 shows the typical construction and heat flow in a plastic quad flat pack (PQFP).
Heat flow paths are represented by a resistor network analogy in the diagram. As can be
seen from the figure, heat flow in the plastic package is very complex when compared to
the hermetic package. In plastic packages, the die is usually mounted onto a copper alloy
die pad, wire bonded to the lead fingers which radially or orthogonally emanate from the
die area, and is finally encapsulated in plastic moulding compound. Because the die is
contacted on all sides by solid matter, heat can flow easily in a multitude of directions. Due
to the copper alloy's high thermal conductivity, the heat immediately spreads into the die
attach paddle, and subsequently into the lead frame. Some heat also flows into the
moulding compound and is released by convection from the package external surfaces. It
is due to this complex heat flow that θJC is ill defined for plastic packages.
Problematic θ JC for Plastic
First, the shortest thermal path is difficult to determine. If the package is thin, and the die
paddle is close to the exterior of the package, this may be the shortest path. On the other
hand, if the lead fingers are close to the die paddle, the most direct path may be through
the lead frame and into the printed circuit board(PCB). The latter of these two possible paths
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FBGA User’s Guide
is more likely, but in any case, the external environment plays a crucial role in the thermal
performance of plastic surface mount devices. As an example, if the PCB is relatively low in
thermal conductivity, e.g. no internal planes and minimized metal traces on the surface,
then the shortest path may well be through the bottom of the package. But, if the PCB has
internal voltage and heat spreading planes, the leads may dominate the heat flow.
Secondly, how are these surfaces made to be isothermal as to satisfy the original intent of
the ceramic based measurements? It was believed that using a well stirred fluid bath with a
fluorinert liquid would force all surfaces on the plastic package to an isothermal state. Due
to the nature of stirred fluids, the measurement breaks down to a moving fluid measurement
and the package surfaces are not isothermal. Recently methods have been developed to
use jet impingement to create high heat transfer coefficients on package surfaces, very
nearly creating the isothermal specification. Although these methods are useful for creating
specific boundary conditions for conduction models, the measurement is still not useful for
predicting junction temperature from a known package temperature.
Figure 2. Heat Flow in Plastic Packages
Customer Use
Through the years, the real identity of θJC was diluted, and today most system houses predict
temperature by placing a thermocouple on the package surface and using the
manufacturer's published θJC values to compute junction temperature. This is a fallacy and is
wholly inaccurate. Today, it is an all too common practice and is accepted as correct. For
hermetic packages, the correct method is to install a heat sink on the surface identified as
the isothermal reference plane, and then use a thermocouple imbedded in the heat sink
and touching the case to properly calculate junction temperature using θJC. for plastic
packages, there is no equivalent method.
Enter Ψ J-T
During discussions with industry leading suppliers, it became obvious that the practices
described above were in use regularly and without question. Users of semiconductors had
grown accustomed to placing the thermocouple and calculating the junction temperature
without really understanding the implications of their actions. To counter this trend and
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provide a more meaningful method to predict junction temperature in plastic packaged
devices, the parameter ΨJ-T was created. An excerpt from the EIA/JESD51-2 standard
follows describing the method and use of ΨJ-T.
4.0 THERMAL CHARACTERIZATION PARAMETER - ΨJT
JUNCTION-TO-TOP CEN TER OF PACKAGE
The thermal characterization parameter, ΨJT, is proportional to the temperature difference between the top
center of the package and the junction temperature. Hence, it is a useful value for an engineer verifying
device temperatures in an actual environment. By measuring the package temperature of the device, the
junction temperature can be estimated if the thermal characterization parameter has been measured under
similar conditions.
The use of ΨJT should not be confused with θJC which is the thermal resistance from the device junction to the
external surface of the package or case nearest the die attachment as the case is held at a constant
temperature. The use and reporting of the case temperature during the junction to ambient thermal
resistance test is optional.
The measurement may be made using a temperature transducer such as a thermocouple, fluoroptic sensor,
or infrared sensor.
4.1 THERMOCOUPLE PLACEMENT LOCATION
The thermocouple bead shall be attached to the package at the geometric center of the top surface. The
position must be reported, in all cases, along with the measurement data.
4.2 PACKAGE THERMOCOUPLE APPLICATION
CAUTION: Usefulness of this measurement is dependent on the procedure.
Application of the thermocouple is critical to ensure proper thermal contact to the package and to ensure
that the θJA measurement is not disturbed. Determination of the package surface temperature, of a low
conductance package body, requires that the following factors be considered:
4.2.1 The thermocouple wire and bead shall touch the surface of the package.
4.2.2 Best practice for attaching the wire and thermocouple bead is the use of a minimal amount of
thermally conducting epoxy. The distance across the epoxy bead shall not exceed .1” (2.54 mm) in
any direction.
4.2.3 The thermocouple wire shall be routed next to the package body down to the board and along
the board. This reduces cooling of the thermocouple junction by heat flowing along the wire.
4.2.4 Thermocouple wire size shall be small such that heat loss along the wire does not cause
anomalous low readings. Recommended maximum thermocouple sizes is 36 gauge. For type T
thermocouples, 40 gauge is preferred.
4.3 PROCEDURE
The junction temperature and package temperatures are determined at the steady-state condition in the
measurement as specified above. The junction-to-top center of package thermal characterization
parameter, ΨJT, is calculated using the following equation:
θ
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FBGA User’s Guide
ΨJT = (TJss - TTss)/PH
(4)
where ΨJT = thermal characterization parameter from device junction to the top center of the
package surface( °C/W)
TJss = the junction temperature at steady-state.
TTss = the package (top surface) temperature, at steady-state, measured by the thermocouple,
infrared sensor, or fluoroptic sensor.
The relationship between the junction-to-ambient thermal resistance, θJA, and the junction-to-top center of
package thermal characterization parameter, ΨJT, is described by equation 5:
θJA = ΨJT + ΨTA
(5)
where ΨTA = thermal characterization parameter from top surface of the package-to-air ( °C/W)
The package-to-air thermal characterization parameter, ΨTA, is based on the steady-state ambient air
temperature as shown here:
ΨTA = (TTss - TAss)/PH
(6)
The thermal characterization parameters, ΨJT and ΨTA, have the units °C/W but are mathematical constructs
rather than thermal resistances because not all of the heating power flows through the exposed case surface.
It is not necessary to report ΨTA because it can be determined from the relationship between θJA and ΨJT.
Also, ΨTA is very dependent on the application-specific environment.
Conclusion
This memo has attempted to educate and inform package, process, and product engineers
in the correct use of temperature measurements on the external surface of the package to
determine junction temperature. If we educate our customers, system level thermal analysis
will be more accurate, allowing a larger application range for our products, especially in
critical situations. Because the measurement is relatively new, we are in the process of
generating ΨJ-T values for all AMD surface mount plastic packages. If a value is needed for a
particular product, please contact the Package Characterization Group in MSD
Engineering.
References
1. "Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device), EIA/ JESD51
Standard, Electronic Industries Association, 1995
2. "Integrated Circuit Thermal Measurement Method - Electrical Test Method (Single Semiconductor Device),
EIA/JESD 51-1 Standard, Electronic Industries Association, 1995
3. "Integrated Circuit Thermal Test Method Environmenatl Conditions - Natural Convection (Still Air), EIA/JESD 51-2
Standard, Electronic Industries Association, 1995
4. "Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages," EIA/JESD 51-3 Standard,
Electronic Industries Association, 1996
5. "Thermal Test Chip Guideline (Wire Bond Type Chip)," EIA/JESD 51-4 Standard, Electronic Industries Association,
1996
6. E
“ xtension of Thermal Test Board Standards for Packages with Direct Attach Mechanisims”, EIA/JESD 51-5,
Electronic Industries Association, 1999
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7. I“ntegrated Circuit Thermal Test Method Environmental Conditions –Forced Convection (Moving Air), EIA/JESD 51-6,
Electronic Industries Association, 1999
8. “High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages”, EIA/JESD 51-7, Electronic
Industries Association, 1999
9. "Accepted Practices for Making Microelectronic Device Thermal Characteristics Tests - A User's Guide," JEDEC
Engineering Bulletin No. 20, Electronic Industries Association, Washington, DC.
10. "Thermal Characteristics," Method 1012.1, MIL-STD-883C Test Methods and Procedures for Microelectronics,
Department of Defense, Washington, DC.
11. "Unencapsulated Thermal Test Chip," SEMI G32-86 Guideline, 1989 Book of SEMI Standards, Vol. 4, Packaging
Division, SEMI, Inc. Mountain View, CA.
12. "Junction-to-Case Thermal Resistance Measurements of Molded-Plastic Packages," SEMI G43-87 Test Method,
1989 Book of SEMI Standards, Vol. 4, Packaging Division, SEMI, Inc. Mountain View, CA.
13. "Thermal Test Board Standardization for Measuring Junction-to-Ambient Thermal Resistance of Semiconductor
Packages," SEMI G42-88 Specification, 1989 Book of SEMI Standards, Vol. 4, Packaging Division, SEMI, Inc.
Mountain View, CA.
14. J“ unction-to-Case Thermal Resistance Measurements of Ceramic Packages," SEMI G30-88 Test Method, 1989 Book
of SEMI Standards, Vol. 4, Packaging Division, SEMI, Inc. Mountain View, CA.
15. "Thermal Transient Testing for Die Attachment Evaluation of Integrated Circuits," SEMI G46-88 Test Method, 1989
Book of SEMI Standards, Vol. 4, Packaging Division, SEMI, Inc. Mountain View, CA.
16. "Still-and Forced-Air Junction-to-Ambient Thermal Resistance Measurements of Integrated Circuit Packages," SEMI
G38-87 Test Method, 1989 Book of SEMI Standards, Vol. 4, Packaging Division, SEMI, Inc. Mountain View, CA.
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Appendix B: Application Note
The following information is excerpted from a published AMD Application Note, number 22142.
Version 4.2, November 1, 2002
85
Daisy Chain Samples
Application Note
Daisy Chain samples are non-functional parts with a
pattern of inter-connected balls. These samples are
typically assembled onto a printed circuit board (PCB)
with matching patterns. Once assembled on the matching PCB, all balls are connected creating a continuous
network. Refer to Figure 1.
Notes:
1. “_____” Solid traces are Daisy Chain patterns on the FBGA package.
2. “- - - - -” Dash traces are Daisy Chain patterns on the PCB.
3. ‘a’, ‘b’ are the input and output of the network for the device.
4. ‘c’, ‘d’ are the input and output of a separate network for the support balls.
Figure 1.
FBGA 32 Mb and 64 Mb Silicon Daisy Chain with Matching PCB Schematic (Top View)
Daisy Chain samples are primarily requested by OEMs
to perform assembly evaluations. Prior to production,
an OEM will generally solder daisy chain samples on to
a daisy chain PCB and perform Open/Short testing to
check for misalignments. This test will help an OEM
characterize its assembly process and equipment prior
to full production.
Daisy Chains are also used in Second Level SolderJoint Board Reliability studies. The daisy chain samples are assembled onto the matching PCB and subjected to temperature cycling in an oven. Board Level
Reliability tests are tools to help predict and measure
the expected life of packages. For more in depth information on Second Level Solder-Joint Board Reliability,
Publication# 22142 Rev: A Amendment/+2
Issue Date: April 15, 2002
FBGA User’s Guide
please refer to “Reliability Evaluation of Chip Scale
Packages” by Ranjit Gannamani, Viswanath Valluri,
Sidharth, and MeiLu Zhang.
Currently AMD has three types of FBGA daisy chains:
Stitched Daisy Chains, Metal Mask Daisy Chains and
Substrate Daisy Chains. Since the main purpose is to
characterize assembly process and equipment, OEMs
typically have no preference on the type of daisy chain
used.
DESCRIPTIONS
bonding. There are no wire bonds from the dummy silicon slug to the substrate.
Metal Mask Daisy Chains
The functional substrate is used with a special daisy
chained wafer. There is no active circuitry on the wafer,
only the simulated bond-pads. Adjacent bond-pads are
shorted via metal mask. Daisy chain patterns are produced by wire bonding the bond-fingers on the substrate to the bond-pads on the wafer.
Substrate Daisy Chains
Stitched Daisy Chains
The functional substrate is used with a dummy silicon
slug. Daisy chain patterns are produced by shorting
pairs of adjacent bond-fingers on the substrate via wire
A dummy silicon slug is used with a special daisy
chained substrate. Shorting adjacent balls on the substrate produces daisy chain patterns.
9 X 8 MM FINE PITCH-BGA (WC) DAISY CHAIN SCHEMATIC
Board Connection (Top View)
Package Connection (Bottom View)
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A
B
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D
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Note: a and b are input and output of the network.
12 X 6 MM 48-BALL FINE PITCH-BGA DAISY CHAIN SCHEMATIC
Board Connection (Top View)
Package Connection (Bottom View)
6
6
5
5
4
4
3
3
2
2
b
1
a
1
A
A
B
C
D
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D
E
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H
H
Note: a and b are input and output of the network.
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FBGA User’s Guide
12 X 11 MM 63-BALL FINE PITCH-BGA DAISY CHAIN SCHEMATIC ‘
Board Connection (Top View)
Package Connection (Bottom View)
8
8
7
7
6
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5
5
4
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b
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Note: a and b are input and output of the network. c and d are input and output of a separate network for support
balls.
13 X 11 MM 64-BALL FORTIFIED-BGA DAISY CHAIN SCHEMATIC
Board Connection (Top View)
Package Connection (Top View)
a
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
A
B
C
D
E
F
G
H
A
b
B
C
D
E
F
G
H
Note: a and b are input and output of the network.
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13 X 11 MM 80-BALL FORTIFIED-BGA DAISY CHAIN SCHEMATIC
Package Connection (Top View)
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
Note: a and b are input and output of the network.
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ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination)
is formed by a combination of the following:
Am29LV160D
WC
D
2
2
B
SUBSTRATE TYPE
A
= Top or internal/intermediate layers shorted on the substrate
B
= Bottom layer shorted on the substrate
C
=
Wirebond
DAISY CHAIN CONNECTION
1
= Daisy chain connection is on the die (metal mask)
2
= Daisy chain connection is on the substrate
SOLDER MASK OPENING AND GROUND PLANE
1
=
No ground plane
2
= 0.25 mm solder mask opening
3
= 0.27 mm solder mask opening
5
= 0.50 mm solder mask opening
6
= 0.55 mm solder mask opening
DAISY CHAIN
PACKAGE TYPES
PB
= 80-ball Fortified Ball Grid Array (FBGA)
1.00 mm pitch, 13 x 11 mm package
PC
= 64-ball Fortified Ball Grid Array (FBGA)
1.00 mm pitch, 13 x 11 mm package
WC = 48-ball Fine Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 9 x 8 mm package
WH = 63-ball Fine Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 12 x 11 mm package
WM = 48-ball Fine Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 12 x 6 mm package
DEVICE NUMBER/DESCRIPTION
Valid Combinations for BGA Daisy Chain
Density
Package
Order Number
Package Marking
16 Mb
9 x 8 Fine Pitch BGA (WC)
13 x 11 mm Fortified BGA (PB)
AM29LV160DWCD22B
AM29BDD160GPBD62B
LV160DD22B
BDAFGD62B
32 Mb
12 x 6 mm FBGA (WM)
AM29DL323DWMD22B
DL323DD22B
64 Mb
12 x 11 Fine Pitch BGA (WH)
13 x 11 mm Fortified BGA (PC)
AM29DL640DWHD22B
AM29LV640DPCD62B
DL640DD22B
LCEDD62B
To place an order, please contact your local AMD sales representative. For a current list of contacts via the
Internet go to http://www.amd.com/support/sales.html
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Revision Summary
Revision E (Version 2.2): March 13, 1999
Chapter 2
Modified 32 and 64 Mb daisy chain and board layout drawings. 32 and 64 Mb pinout drawings now
show outrigger balls that are shorted.
Revision F (Version 2.3): May 17, 1999
Construction of the FBGA-BT figure
Revised the following callouts: Mold Compound (deleted “Multi-Functional”), Die Attach (deleted
“Non-conductive”), Solder Mask (deleted “50µ Nom”), Copper Foil (deleted “12µ”), Plating (deleted
thickness from Cu and Au).
FBGA Package Materials Descriptions
In the table, renamed the following parameters: Rigid Substrate; Molding Compound; Die Attach
Material. Deleted “Interposer” from Copper Metallization.
FBGA Ball Attach Detail
Clarified type of attach.
Component Level Testing, FBGA-BT
Changed JC-14.1-98-135, Level 2 qualifications is planned for Q2, 1999 to JCB-98-104. In the table,
added rows 4 through 6. In item 3, changed ramp-up rate to 3°C, time at max. temperature to 10–20
seconds.
FBGA-BT Component Level Test Results
Replaced and reformatted data in table.
Test Strategy
Deleted reference to data supplied to AMD weekly.
FBGA Package Marking
Added “D” technology designator. Revised explanatory table.
FBGA Package Dimensions
Renamed WE and WF designators to WG and WH, respectively.
Version 4.2, November 1, 2002
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FBGA User’s Guide
Revision F+1 (Version 2.3.1): July 30, 1999
Chapter 2
16 Mb Daisy Chain and Board Layout figures. Added new 99xx date code daisy chain schematic and
board layout. Added 98xx date code to previous drawings.
Revision G (Version 3.0): January 15, 2001
Chapter 2
Replaced all FGBA pinout figures with new illustrations.
Chapter 3
Updated package outline diagrams with specification 16-038-9 illustrations. Replaced Table 3-1
FBGA-BT with new information. Section on “FBGA Thermal Resistance Data” replaced with section
on “FBGA Thermal Management”.
Chapter 4
Added HDI information in the “General Design Considerations” section. Replaced “Routing
Dimensions” section with “Routing Recommendation” section. Added “gold thickness of 5 mils max
is recommended” to the “PC Board Surface Finish” subsection. Updated “Recommended Design
Values” in the table below Figure 4-2. Replaced “Routing Dimensions” and “Routing for 32-Megabit”
figure with “Example of Routing” figures.
Chapter 5
Replaced entire chapter with new information.
Appendix A
New article reprints.
Appendix B
New application note.
Revision G+1 (Version 3.1): March 12, 2001
Chapter 2—Daisy Chains
Added “Both are listed in the Appendices.” to the end of the second paragraph.
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Chapter 3—FBGA Thermal Management
Added “TASS = Temperature of Ambient Air at Steady State” to the “θJA – Junction to Air” equations
Table 3-2. Thermal Resistance Data: Changed table headings “θJC (°C/W)” to “θJMA (°C/W)” and
“θJMA (°C/W)” to “ΨJ–T (°C/W). Shifted down the values in the θJMA (°C/W) table column. Moved
data of the FGC048 ΨJ–T (°C/W) table cell to the FGC048 θJMA (°C/W) location. Added the following
table notes: “4. θJMA = Theta of junction to moving air.” and “5. SPD (LFPM) = Speed of moving air,
in terms of “Linear Feet Per Minute”.” Corrected the FBD063 θJA (°C/W) data.
Revision H (Version 4.0): January 24, 2002
Chapters 1–4
Chapters were completely rewritten. It is recommended that users of previous editions read through
these chapters to familiarize themselves with the revised content.
Chapter 5
New daisy chain schematics and board layouts have been added. The first two figures from the
previous User’s Guide have been deleted.
Revision I (Version 4.1): April 12, 2002
Chapter 2
Figure 2-3: Added Am29PDS322D to list of devices in 8 x 9 mm package.
Figure 2-7: corrected 4Gb to 128 Mb.
Chapter 5
Corrected figure 5-7 from 80 to 84 ball; figure 5-8 from 64 to 84 ball, figure 5-10 from 80 to 64 ball.
Chapter 6
Table 6.1: Corrected units of measure in thickness column from mm to µm. Deleted E-05 from
specifications in CTE ppm/c column.
Added descriptions for FLA069, FLB073, LAA064, LAA080, LAB 080, and LBA176
Chapter 7
Recommended Board Desin Dimensions: Modified table to show both 0.30 and 0.60 mm balls.
Version 4.2, November 1, 2002
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FBGA User’s Guide
Chapter 10
FBGA Package Designators: Added 6 x 12, 11 x 13 , and 10 x 15 mm sizes.
Appendix B
Updated information from October 25, 2001 revision of application note.
Revision J (Version 4.2): November 1, 2002
Chapter 7
Modified table to include values for 0.35 mm solder balls. Changed tolerances on dimension A for
0.30 and 0.60 solder balls. Changed dimension C for 0.30 solder balls.
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Version 4.2, November 1, 2002
95
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11/01/02
22142J