ETC 22363A

Simple Systems Interface for
UltraNAND™ Flash
Application Note
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Publication Number 22363 Revision A
Amendment 0 Issue Date April 20, 1999
Simple System Interface for
UltraNAND™ Flash
Application Note
AMD has developed the UltraNAND™ product line to
address high-density non-volatile memory needs. Target applications include code and data storage in embedded or removable media systems. This application
note describes a simple hardware system interface for
u p to t hr ee U ltra N A N D b a n ks, u sin g a sin g le
AmPALLV16V8-10SC or AmPALLV22V10-10PC PLD
(Programmable Logic Device). A bank combines two or
more 8-bit UltraNAND devices to accomodate system
system bus width requirements (16-bit or higher).
Note: Please refer to the UltraNAND device data sheet and
“Boot Loader for UltraNAND Flash Simple System Interface”
application note for further information as necessary.
Appropriate Applications
AMD’s UltraNAND Flash provides high-speed read,
program, and erase operations at a lower cost per bit
than NOR Flash, which makes it ideal for high-density
non-volatile storage applications. Appropriate applications are those that use non-volatile memory to store
code or data which is transferred, or shadowed, to a
high-speed memory resource—like synchronous
DRAM—for fast random access or execution. UltraNAND has relatively slow (7 µs) access to random
pages, but fast (50 ns) access to sequential bytes
within a selected page. The slow random access and
the requirement for command and address input
makes UltraNAND inappropriate for code XIP (Execute
in Place) operations. The fast sequential read and
write speed, high-density, and lower cost per bit make
UltraNAND ideal for disk replacement or other high-volume non-volatile storage applications that do not require high-speed random access.
System Related Benefits of UltraNAND
UltraNAND has been designed to be fully hardware
and software compatible with NAND architecture Flash
already available on the market. However, current
competitive products generally require ECC (Error
Check and Correction) to meet their specified program/
erase cycle endurance, and are not typically available
as 100% good devices. Most of these competing devices are sold with the understanding that they may
have a few bad blocks when shipped from the manufacturer. Using a product with bad blocks usually requires that the system provide some form of bad block
management to map defective blocks out of the system
memory space. The requirement for ECC and bad
block mapping adds hardware and software design
complexity, generally increases total system cost, and
impacts system performance. In some cases the performance impact can be as great as a 40% decrease in
overall data throughput.
UltraNAND has been designed as an improved product
solution over the competition, providing 100,000 program/erase cycle endurance without requiring ECC.
UltraNAND is also available with 100% good blocks,
which eliminates the need for bad block mapping. The
program/erase cycle endurance, without ECC, and
availability of 100% good devices greatly simplifies
system design requirements. Applications can use UltraNAND with simple system interface logic, rather
than the sophisticated memory controller that would be
required with competing devices. The package, pinout, command set, and bus interface compatibility of
UltraNAND allow applications designed to support
older NAND architecture devices to be simplified, and/
or cost reduced, with UltraNAND.
UltraNAND Interface Requirements
As shown in Figure 1, UltraNAND utilizes a multiplexed
command/address/data bus. All command, address,
and data information is passed to and from the device
through I/O[0..7] (8-bit I/O port). Control signals are
provided on the device for CE# (Chip Enable), CLE
(Command Latch Enable), ALE (Address Latch Enable), WE# (Write Enable), RE# (Read Enable), SE#
(Spare area Enable), and WP# (Write Protect). There
is also an open drain RY/BY# (Ready/Busy) output pin
used to indicate when the device is busy with an internal operation.
System applications using UltraNAND must generate
the proper control signals for the device which, in many
cases, are not used by any other system resource.
Fortunately, the interface logic required to generate the
appropriate UltraNAND signals is reasonably simple
and can be designed in discrete logic, incorporated in
a PLD, or included in the system ASIC. The simple
system interface designs included in this application
note have been developed for the AmPALLV16V8 and
AmPALLV22V10 PLDs. Source and simulation code
for two PLD versions, single and multiple bank support,
Publication# 22363 Rev: A Amendment/0
Issue Date: April 20, 1999
is included in this application note. The PLDs generated are shown in Figure 4 and Figure 5.
tions that do not have programmable I/O lines available.
System Interface Description
Typical System Implementation
Using Programmable I/O
In many applications using UltraNAND, there may be
programmable I/O lines available, either in a microcontroller or the system interface logic, that can be
used to generate the UltraNAND CE#, CLE, ALE, SE#,
and WP# inputs. With enough programmable I/O lines
available, the Interface PLD described in this application note is not required, and the system can provide all
of the interface support needed through those programmable I/O lines. If WP# does not need to be dyn a mica lly co n tro lle d by th e syste m, on ly fo ur
programmable I/O lines are required. This application
note is intended to describe the basic logic needed to
control up to three UltraNAND banks for those applica-
A typical application of the simple system interface is
shown in Figure 1 with the Interface PLD supporting a
single UltraNAND bank consisting of two UltraNAND
devices. The Interface PLD uses the usual system
control signals to create the full set of control signals
needed by the UltraNAND Flash. The system software
is then able to program the Interface PLD to generate
the signal sequence required for proper operation. Because fewer than three UltraNAND banks are required,
the 16V8 PLD version that supports only one bank was
used.
The INIT signal is unused in this application example.
Refer to the “Boot Loader for UltraNAND Flash Simple
System Interface” application note for information on
generating an INIT signal using a Boot Loader PLD.
System Address, Control, and Data Buses
D6
AmPALLV16V8-10SC
CE#
I/O[0..7]
D[8..15]
4
16
A[0..3]
OUTCE#
CE#
CLE
CLE
WRITE#
ALE
ALE
READ#
WE#
WE#
CE#
RE#
RE#
RESET
SE#
SE#
INIT
WP#
WP#
I/O[0..7]
D[0..7]
VCC
RY/BY#
UltraNAND
RY/BY#
READY
Interface PLD
Figure 1.
2
Typical System Interface Application for a Single UltraNAND Bank
Simple System Interface for UltraNAND™ Flash
System Interface Signal Description
The UltraNAND Interface PLD is responsible for generating the signals required by the UltraNAND device,
which are not found in typical systems. These are CLE,
ALE, WE#, RE#, SE#, and WP#. In order to control the
Interface PLD, the system is responsible for providing
Table 1.
some of the more typical address and control signals.
The definition of all pertinent signals, and the source
required to generate the signals, are included in Table
1. A timing diagram of a Read First Half Page operation is shown in Figure 2, and includes all of the signals
required by UltraNAND.
UltraNAND System Interface Signal Description
Signal
Source
INIT
Optional Boot Loader
PLD
ALE
Interface PLD
Address Latch Enable required for address latch cycles
CLE
Interface PLD
Command Latch Enable required to latch the command
OUTCE[0..2]#
Interface PLD
The Chip Enables used to select the UltraNAND bank(s)
RE#
Interface PLD
Read signal used by UltraNAND for all read cycles
READY
Interface PLD
Tri-state output to allow the system to read the state of the RY/BY# pin(s)
SE#
Interface PLD
Spare Area Enable to control access to the UltraNAND spare area
WE#
Interface PLD
Write signal used by UltraNAND for all write cycles
WP#
Interface PLD
Write Protect to prevent program/erase operations in UltraNAND
A[0..3]
System
Address bus used to select one of sixteen Interface PLD control ports
CE#
System
The Chip Enable used to select the UltraNAND and Interface PLD
I/O[0..7]
System/UltraNAND
RESET
System
A system reset signal which remains high until VCC is valid
READ#
System
Read signal used by the system for all read cycles
WRITE#
System
Write signal used by the system for all write cycles
RY/BY#
UltraNAND
Definition
From optional “Boot Loader for Simple System Interface” PLD to indicate that
the Boot Loader PLD is initializing UltraNAND
The eight I/O lines used to transfer commands, addresses, and data
Ready/Busy signal to indicate the current state of UltraNAND
OUTCE#
CLE
ALE
WE#
RE#
I/O[0..7]
00h
A0-A7
A9-A16
A17-A24
Dout N
Dout 527
SE#
WP#
RY/BY#
Figure 2. UltraNAND Read First Half Page Timing Diagram
Simple System Interface for UltraNAND™ Flash
3
Interface PLD Port Addresses
The UltraNAND Interface PLD occupies sixteen port
addresses. The port address locations are determined
by the CE# (Chip Enable) signal generated by the system. This allows the UltraNAND device, or devices, to
be set up as either a memory mapped or I/O mapped
system resource. The system sets the base address of
the device through the chip enable address decode
and the UltraNAND interface will then be accessible at
that address, and through the next fifteen sequential
addresses. As an example, if the chip enable decode
is set for I/O location 200h, the Interface PLD would reside at I/O locations 200h through 20Fh. A description
of each interface address and the operation performed
is included in Table 2.
Table 2. UltraNAND System Interface Control Port Definition
Port
Read
Write
Operation Performed
0
Data, ID, or Status
Address or Data
1
N/A
Command
2
N/A
Set ALE
3
N/A
Clear ALE
4
N/A
Set SE#
5
N/A
Clear SE#
6
N/A
Set WP#
Set WP# (low) to prevent program/erase cycles
7
N/A
Clear WP#
Clear WP# (high) to allow program/erase cycles
8
N/A
Set CE0#
Set CE0# (low) to enable the first UltraNAND bank
9
N/A
Clear CE0#
Clear CE0# (high) to disable the first UltraNAND bank
A
N/A
Set CE1#
Set CE1# (low) to enable the second UltraNAND bank
B
N/A
Clear CE1#
C
N/A
Set CE2#
D
N/A
Clear CE2#
E
N/A
N/A
No Function
F
RY/BY# Status
N/A
Read the state of all RY/BY# pins through this port
Read information depends on previous command loaded
Write addresses (ALE = high) or data (ALE = low)
All commands are written through this port with ALE cleared (low)
Set ALE (high) to allow addresses to be written
Clear ALE (low) to allow commands, or data, to be written
Set SE# (low) to allow access to the spare area of each page
Clear SE# (high) to prevent access to the spare area of each page
Clear CE1# (high) to disable the second UltraNAND bank
Set CE2# (low) to enable the third UltraNAND bank
Clear CE2# (high) to disable the third UltraNAND bank
Legend: X = Don’t Care
Interface PLD Theory of Operation
This section describes the functional blocks of the Interface PLD. The example AmPALLV16V8 and
AmPALLV22V10 PLDs generated are shown in Figure
4 and Figure 5 respectively. An application schematic
for three UltraNAND devices, supported by a single
AmPALLV22V10 PLD, is shown in Figure 6.
Port Decode
dress decode function. This allows the Interface PLD
to respond to address decodes 00h through 0Fh as an
offset from the base address determined by the CE# input. The decoder logic outputs are used to determine
when to drive the CLE, RE#, and WE# signals to UltraNAND directly, to set and clear transparent latches
for ALE, OUTCE[0..2]#, SE#, and WP#, or to allow the
system to read the state of the RY/BY# pin through the
Interface PLD READY output.
In the simple system interface design PLD examples,
combinatorial logic is used to perform the basic port ad-
4
Simple System Interface for UltraNAND™ Flash
Output Signal Generation
The simple system Interface PLDs use combinatorial
logic and transparent latches to generate all of the signals required by UltraNAND. CLE, RE#, and WE# are
generated dynamically and are not latched. ALE,
OUTCE[0..2]#, SE#, and WP# are latched in the design so that the system has the ability to set or clear
these signals as needed.
■ RE# is a dynamic signal which is generated whenever the system performs a read from the Interface
PLD port 00h or 0Fh. This allows the system to
read Data, ID, or Status information from UltraNAND through port 00h, or to read the state of
the RY/BY# pin(s) through the Interface PLD port
0Fh.
■ CLE is a dynamic signal which is generated whenever the system performs an access to port 01h.
This causes CLE to go active during both reads and
writes to port 01h. When the system writes a command out to port 01h, the command on the UltraNAND I/O bus will be written with CLE active,
allowing the command to be accepted by the device. Prior to a command being written to the device
ALE must be cleared (ALE = low) and the chip enable for the appropriate UltraNAND device must be
latched low.
■ READY is a dynamic, tri-state output from the Interface PLD that allows the system to read the state of
the UltraNAND RY/BY# pin(s). The Interface PLD
will drive the state of the RY/BY# pin(s) to the
READY pin when a read from Interface PLD port
0Fh is performed.
■ ALE is a latched signal which may be set or cleared
under software control and determines whether addresses, commands, or data are written to UltraNAND. ALE must be cleared when a command
or data is to be written. Once ALE is set, the address may be written to port 00h to load the address
into UltraNAND. ALE must be set prior to the first
address cycle written and must be cleared following
the last address write cycle. In the Interface PLD,
the latch is set and cleared by writing to ports 02h
and 03h respectively. Only a write to the port is required and the data written is irrelevant. In the
PLDs, ALE is latched low (cleared) following powerup.
■ OUTCE[0..2]# are latched signals which may be set
or cleared under software control and determine
whether an UltraNAND device is enabled or disabled. The appropriate chip enable output must be
set when a command, address, or data is to be written to any UltraNAND device. The appropriate chip
enable output must also be set for any read operation, and must be held asserted during all read latency periods to avoid aborting the requested read
operation. In the Interface PLD, the latch for
OUTCE0# is set and cleared by writing to ports 08h
and 09h, the latch for OUTCE1# is set and cleared
by writing to ports 0Ah and 0Bh, and OUTCE2# is
set and cleared by writing to ports 0Ch and 0Dh respectively. Only a write to the port is required and
the data written is irrelevant. In the PLDs, all
OUTCE[0..2]# outputs are high (cleared) following
power-up.
■ SE# is a latched signal which may be set or cleared
under software control and determines if the spare
area of each page (bytes 512 – 527) can be read or
written. Once SE# is set, the system may read or
write to the spare area through port 00h. SE# must
be set prior to the Read Spare Area command (50h)
being written to the device. If the spare area is to be
read or written along with the normal Flash page information (bytes 0 – 511) then SE# must be set at
least two cycles before the first spare area address
(512) is accessed. In the PLD, SE# is set and
cleared by writing to ports 04h and 05h respectively.
Only a write to the port is required and the data written is irrelevant. SE# is latched low (set) following
power-up.
■ WE# is a dynamic signal which is generated whenever the system performs a write to the Interface
PLD port 00h or 01h. This allows the system to
write Address or Data information to UltraNAND
through port 00h, or to write commands to UltraNAND through the Interface PLD port 01h.
■ WP# is a latched signal which is set or cleared
under software control, and determines whether or
not program or erase operations are allowed in UltraNAND. Once WP# is set (low) the system is unable to program or erase any location in the device,
and only read cycles are allowed. In the PLD, the
WP# latch is set or cleared by a write to port 06h or
07h respectively. Only a write to the port is required
and the data written is irrelevant.
WP# is latched low (set) following power-up. A
RESET signal, which remains low until power is
valid, should be used to guarantee that WP# is asserted during power transitions. This is a requirement of UltraNAND and NAND technology devices,
and is used to guarantee that there is no data corruption in the device during power transitions.
Simple System Interface for UltraNAND™ Flash
5
Other Signals (Generated by the System Logic)
■ A[0..3] are the four least significant address bits,
generated by the system, which are used to select
one of sixteen ports in the Interface PLD.
■ CE# is generated by the system logic and determines the address that the Interface PLD and UltraNAND devices will occupy. The system may
assign the CE# decode address to be any consecutive sixteen port address in either the I/O or memory address space.
■ INIT is generated by an optional “Boot Loader” PLD
which is only required if the system needs to read
from the device immediately after power-up. The
boot loader issues a Gapless Read (02h) command
sequence to the UltraNAND device, or devices, to
pre-load the data registers of each device with the
first page of information.
■ READ# is the system generated read strobe that is
used to read from the Interface PLD or UltraNAND
devices. In addition to the CE# input, the READ#
signal determines if the Interface PLD and UltraNAND read operations are I/O or memory
mapped.
■ RESET is generated by the system and is used to
initialize the Interface PLD. The RESET signal
should be asserted (high) whenever the system
power is ramping up or down. This allows the Interface PLD to assert WP# to protect the UltraNAND
devices from data corruption during power transitions.
■ RY/BY# is generated by the UltraNAND device to
indicate when the device is busy with an internal operation. The system may use the RY/BY# hardware
signal, or poll the RY/BY# status bit in the status
register, to determine when an operation is in process, or has completed.
■ WRITE# is the system generated write strobe used
to write to the Interface PLD or UltraNAND devices.
In addition to the CE# input, the WRITE# signal is
6
used to determine if the Interface PLD and UltraNAND write operations are I/O or memory
mapped.
Design Notes
With the simple interface described in this application
note, the system has full control of up to three UltraNAND devices. There are a number of basic modifications that can be made to the design to allow
different system configurations to be supported.
Modifications to WP# Circuit
In many applications, the WP# input to UltraNAND is
not dynamically controlled by the system. Instead it is
controlled by a jumper, or switch, that allows the circuit
to be hardware protected against program or erase cycles. For this modification to the simple system interface, the PLD output for WP# would be replaced with a
jumper or switch. Again, some form of RESET signal
must be used to force WP# active (low) during power
transitions.
Removing WP# from the Interface PLD would free up
an output pin and would allow a fourth chip enable output to be supported. This would allow the Interface
PLD to support up to four banks of UltraNAND instead
of only three banks.
Supporting Multiple UltraNAND Banks
The simple system interface provided supports up to
three UltraNAND banks with all of the signals generated by the Interface PLD, except the output chip enables common to all devices. The diagram in Figure 3
shows how two banks, with two UltraNAND devices in
each bank, can be supported. In this application, the
WP# signal is common to all of the Flash devices so
that the entire array is either protected or unprotected
as a block. If preferred, the logic to generate WP#
could be modified to provide a separate WP# for each
device.
Simple System Interface for UltraNAND™ Flash
System Address, Control, and Data Buses
I/O6
CE#
I/O[0..7]
D[8..15]
CLE
AmPALLV22V10-10PC
CE#
4
I/O[0..7]
D[0..7]
CLE
A[0..3]
WRITE#
OUTCE0#
CE#
OUTCE1#
CLE
CE#
OUTCE2#
READ#
CLE
CLE
CE#
ALE
ALE
RESET
WE#
WE#
INIT
RE#
RE#
SE#
SE#
WP#
WP#
RY/BY#
I/O[0..7]
D[8..15]
16
I/O[0..7]
D[0..7]
RY/BY#
READY
UltraNAND
VCC
Interface PLD
Figure 3.
Supporting Multiple UltraNAND Banks
Simple System Interface for UltraNAND™ Flash
7
Pseudo Code Example
Included below is an example of how the Interface PLD can be used to allow the system software to control all operations that UltraNAND supports. In this example, one 528 byte page of information will be input to one device and
then programmed. The following system configuration is assumed:
1. SOURCE – This is a 528 byte source buffer in system memory
2. DEST – This is the target page to be programmed in UltraNAND
3. PORTADDR – This is a system generated I/O mapped port address for the UltraNAND device to occupy
INIT:
SOURCE ADDRESS POINTER
DEST ADDRESS POINTER
START:
Write 00h to (PORTADDR + 8)
Write 00h to (PORTADDR + 3)
Write FFh to (PORTADDR + 1)
Write 00h to (PORTADDR + 1)
Write 00h to (PORTADDR + 4)
Write 00h to (PORTADDR + 7)
Write 80h to (PORTADDR + 1)
Write 00h to (PORTADDR + 2)
Write DEST[A7-A0] to (PORTADDR + 0)
Write DEST[A16-A9] to (PORTADDR + 0)
Write DEST[A24-A17] to (PORTADDR + 0)
Write 00h to (PORTADDR + 3)
;Set up the address for the 528 byte source system page
;Set up the address for the 528 byte target page in Flash
;Set OUTCE0# (low) to enable UltraNAND. Data is a don’t care
;Clear ALE (low) prior to issuing command. Data is a don’t care
;Send a reset command to reset the Flash (may be omitted)
;Send a “Read First Half Page” command to the Flash to set
;the internal pointer to the first half page region in the Flash
;Set SE# (low) to allow Spare Area access. Data is a don’t care
;Clear WP# (high) to allow Flash program. Data is a don’t care
;Send an “Input Data” command to the Flash
;Set ALE (high) prior to issuing addresses. Data is a don’t care
;Load the first address byte into the Flash
;Load the second address byte into the Flash
;Load the third address byte into the Flash
;Clear ALE (low) prior to writing data. Data is a don’t care
LOOP1:
Write [SOURCE] to (PORTADDR + 0)
Does SOURCE = 527
IF YES branch to PROG:
SOURCE = SOURCE + 1
Branch to LOOP1:
;This is where we fill the Flash buffer
;Write the data contents at the SOURCE location to the data port
;Has the last data byte been written?
;If the last byte is loaded go ahead and program the Flash
;If not point to the next address location and write another byte
PROG:
Write 10h to (PORTADDR + 1)
Write 70h to (PORTADDR + 1)
;All 528 bytes are loaded so program the Flash
;Send a “Page Program” command to the Flash
;Send a “Read Status” command to the Flash
CHKSTAT:
Read from (PORTADDR + 0)
Does D6 = 1
IF YES branch to DONE:
Branch to CHKSTAT:
;Read the device status to see if the program is done
;Check to see if the device is ready
;If the program operation is done go and check for pass/fail
;If not continue to check the status for a ready condition
DONE:
Write 00h to (PORTADDR + 6)
Read from (PORTADDR + 0)
Does D0 = 1
IF YES branch to FAIL:
Write 00h to (PORTADDR + 9)
Return (program successful)
;Set WP# (low) to re-protect the Flash. Data is a don’t care
;Read the device status again to see if the program passed
;Check to see if the program operation passed or failed
;A “1” in the D0 location indicates a failure condition
;Clear OUTCE0# (high) to disable UltraNAND. Data is a don’t care
;The program operation passed so return and report
FAIL:
Write 00h to (PORTADDR + 9)
Return (program failed)
;Clear OUTCE0# (high) to disable UltraNAND. Data is a don’t care
;The program operation failed so return and report
8
Simple System Interface for UltraNAND™ Flash
PLD Example Implementation
PLD Source Code for UNISA16
This Interface PLD, designed into a single AmPALLV16V8, allows one UltraNAND bank to be supported by a single
interface chip. This example includes the PLD source code and the simulation file used to verify the design. The
AMD AmPALLV16V8-10SC used in the example powers up in a known state which covers initial power-up conditions. The RESET input is used to initialize the transparent latches in the PLD. Figure 4 is a diagram showing the
pin-out of the AmPALLV16V8-10SC used in this design example.
Name
UNISA16;
Partno
PLD001;
Date
03/23/99;
Revision
0;
Designer
Ralph Gibson;
Company
Advanced Micro Devices;
Assembly
UltraNAND(TM) ISA Development Board Interface Solution;
Location
U1;
Device
G16V8;
Format
J;
/****************************************************************************\
**
This is a simple interface for UltraNAND allowing one UltraNAND to be
**
**
supported on a PC ISA bus. This device includes a RESET input to force
**
**
WP# asserted on power transitions.
**
**
and goes high when supply power ramps down.
RESET is high until Vcc is valid
**
\****************************************************************************/
/**
Inputs
**/
Pin 1
= !WRITE;
Pin 2
= !READ;
Pin [3..6]
= [A0..3];
Pin 7
= !CE;
Pin 8
= RY_BY;
/* RY/BY# input from UltraNAND */
Pin 9
= RESET;
/* RESET - high for reset and power transitions */
Pin 11
= INIT;
/**
Outputs
/* System Write Enable */
/* System Read Enable */
/* Address input to select port */
/* Chip Enable for the interface and UltraNAND */
/* INIT from the optional Boot Loader PLD */
**/
Pin 19
= READY;
/* Allows system to read RY/BY# pin state */
Pin 18
= CLE;
/* Command Latch Enable to UltraNAND */
Pin 17
= ALE;
/* Address Latch Enable to UltraNAND */
Pin 16
= !SE;
/* Spare Area Enable to UltraNAND */
Pin 15
= !WP;
/* Write Protect to UltraNAND */
Pin 14
= !OUTCE;
Pin 13
= !WE;
/* Write Enable to UltraNAND */
Pin 12
= !RE;
/* Read Enable to UltraNAND */
/* Chip Enable to UltraNAND */
Simple System Interface for UltraNAND™ Flash
9
/** Declarations and Intermediate Variable Definitions **/
PORT0 =
#
PORT1 =
#
PORT2 =
#
PORT3 =
#
PORT4 =
PORT5 =
PORT6 =
PORT7 =
PORT8 =
PORT9 =
PORTA =
PORTB =
PORTC =
PORTD =
PORTE =
PORTF =
/**
CE
INIT
CE
INIT
CE
INIT
CE
INIT
CE
CE
CE
CE
CE
CE
CE
CE
CE
CE
CE
CE
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
!A3
!A1
!A3
!A1
!A3
A1
!A3
A1
!A3
!A3
!A3
!A3
A3
A3
A3
A3
A3
A3
A3
A3
Logic Equations
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
!A2 &
!A0;
!A2 &
A0;
!A2 &
!A0;
!A2 &
A0;
A2 &
A2 &
A2 &
A2 &
!A2 &
!A2 &
!A2 &
!A2 &
A2 &
A2 &
A2 &
A2 &
!A1 & !A0
!A1 &
/* Data read/write port */
A0
/* CLE write port */
A1 & !A0
/* Used to set ALE */
A1 &
!A1
!A1
A1
A1
!A1
!A1
A1
A1
!A1
!A1
A1
A1
&
&
&
&
&
&
&
&
&
&
&
&
A0
!A0;
A0;
!A0;
A0;
!A0;
A0;
!A0;
A0;
!A0;
A0;
!A0;
A0;
/* Used to clear ALE */
/* Used to set SE#
/* Used to clear SE#
/* Used to set WP#
/* Used to clear WP#
/* Used to set OUTCE#
/* Used to clear OUTCE#
/* No Function
/* No Function
/* No Function
/* No Function
/* No Function
/* To read RY/BY# state
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
**/
READY.OE = PORTF & READ; /* READY is only driven during a PORTF read */
READY
= RY_BY; /* READY shows the state of RY/BY# */
CLE
= PORT1; /* Assert CLE on all PORT1 accesses */
ALE
= !RESET & ( WRITE & PORT2
/* Latch ALE on write to PORT2 */
# ALE & !( WRITE & PORT3 ) /* and clear on write to PORT3 */
# ALE & PORT2 );
/* Transparent latch cover term */
SE
=
#
#
#
RESET
WRITE & PORT4
SE & !( WRITE & PORT5 )
SE & PORT4;
/* Latch SE# asserted on RESET
/* Latch SE# on write to PORT4
/* and clear on write to PORT5
/* Transparent latch cover term
*/
*/
*/
*/
WP
=
#
#
#
RESET
WRITE & PORT6
WP & !( WRITE & PORT7 )
WP & PORT6;
/* Latch WP# asserted on RESET
/* Latch WP# on write to PORT6
/* and clear on write to PORT7
/* Transparent latch cover term
*/
*/
*/
*/
OUTCE
= !RESET &
#
#
#
( INIT
/* Latch OUTCE# asserted on INIT
WRITE & PORT8
/* Latch OUTCE# on write to PORT2 and
OUTCE & !( WRITE & PORT9 )
/* clear on write to PORT3
OUTCE & PORT8 );
/* Transparent latch cover term
*/
*/
*/
*/
WE
= WRITE & ( PORT0
# PORT1 );
RE
= READ & PORT0;
10
/* Drive WE# to UltraNAND for PORT0 or PORT1 */
/* Drive RE# to UltraNAND for PORT0 only */
Simple System Interface for UltraNAND™ Flash
PLD Simulation File for UNISA16
The simulation file included here is used to verify the design of the PLD supporting one UltraNAND bank.
Name
Partno
Date
Revision
Designer
Company
Assembly
Location
UNISA16;
PLD001;
03/23/99;
0;
Ralph Gibson;
Advanced Micro Devices;
UltraNAND(TM) ISA Development Board Interface Solution;
U1;
/************************************************************************\
** This is a simple interface for UltraNAND allowing one UltraNAND to **
** be supported on a PC ISA bus. This device includes a RESET input to **
** force WP# asserted on power transitions. RESET is high until Vcc
**
** is valid and goes high when supply power ramps down.
**
**************************************************************************
** Allowable Target Device Types:
AmPALCE16V8-10 **
\************************************************************************/
ORDER: RESET, %1, !WRITE, %1, !READ, %1, !CE, %1,
A3, %1, A2, %1, A1, %1, A0, %1, INIT, %1, RY_BY, %2,
CLE, %1, ALE, %1, !SE, %1, !WP, %1, !OUTCE, %1,
!WE, %1, !RE, %1, READY;
VECTORS:
$msg
$msg
$msg
$msg
$msg
$msg
$msg
$msg
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
"
"
"
"
"
"
"
"
V0001
V0002
V0003
V0004
V0005
V0006
V0007
V0008
V0009
V0010
V0011
V0012
V0013
V0014
V0015
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
R
E
S
E
T
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
!
W
R
I
T
E
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
!
R
E
A
D
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
!
C
E
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
A
3
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
A
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
A
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
I
N
I
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
Y
B
Y
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
L
E
L
L
L
H
L
L
L
H
H
L
L
L
L
L
L
A
L
E
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
!
S
E
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
!
W
P
L
L
L
L
L
L
L
L
L
L
L
L
L
L
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!
O
U
T
C
E
H
H
H
H
H
L
L
L
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W
E
H
H
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R
E
H
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H
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A
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Y
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
";
";
";
";
";
";
";
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
Simple System Interface for UltraNAND™ Flash
Reset the device
Reset the device
no function
no function
no function
Set OUTCE#
idle
Write command - CLE
idle
Set ALE
idle
Write address
idle
Write address
idle
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
11
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
12
V0016
V0017
V0018
V0019
V0020
V0021
V0022
V0023
V0024
V0025
V0026
V0027
V0028
V0029
V0030
V0031
V0032
V0033
V0034
V0035
V0036
V0037
V0038
V0039
V0040
V0041
V0042
V0043
V0044
V0045
V0046
V0047
V0048
V0049
V0050
V0051
V0052
V0053
V0054
V0055
V0056
V0057
V0058
V0059
V0060
V0061
V0062
V0063
V0064
V0065
V0066
V0067
V0068
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
X
X
X
X
X
X
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
L
Z
L
Z
L
Z
H
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
Simple System Interface for UltraNAND™ Flash
Write address
idle
Write address
idle
Clear ALE
idle
Clear SE#
idle
Clear WP#
idle
Write data
idle
Write data
idle
Set WP#
idle
Write command - CLE
idle
Set ALE
idle
Write address
idle
Write address
idle
Write address
idle
Clear ALE
idle
Set SE#
idle
Read RY/BY# status
idle
Read RY/BY# status
idle
Read RY/BY# status
idle
Read RY/BY# status
idle
Read data
idle
Read data
idle
Clear SE#
idle
Set SE#
idle
Initialize
Write command - CLE
idle
Set ALE
idle
Write address
idle
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
V0069
V0070
V0071
V0072
V0073
V0074
V0075
V0076
V0077
V0078
V0079
V0080
V0081
V0082
V0083
V0084
V0085
V0086
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
0
0
1
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
1
1
0
0
1
0
0
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
Write address
idle
Write address
idle
Clear ALE
idle
Read data
idle
Read data
idle
Reset the device
idle
Set OUTCE#
idle
idle
Clear OUTCE#
idle
idle
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
AmPALLV16V8-10SC
WRITE#
1
20
VCC
READ#
2
19
READY
A0
3
18
CLE
A1
4
17
ALE
A2
5
16
SE#
A3
6
15
WP#
CE#
7
14
OUTCE#
RY/BY#
8
13
WE#
RESET
9
12
RE#
10
11
INIT
VSS
Note:
The AmPALLV16V8-10SC is a 3.3 Volt PLD device.
Figure 4. Example PLD Implementation (One Bank Support)
Simple System Interface for UltraNAND™ Flash
13
PLD Source Code for UNISA22
This example includes the PLD source code and the simulation file used to verify a slightly modified PLD design.
The PLD circuit included below supports up to three UltraNAND banks. The AMD AmPALLV22V10-10PC used in
the example powers up in a known state which covers initial power-up conditions. The RESET input is used to initialize the transparent latches in the PLD. Figure 5 is a diagram showing the pin-out of the AmPALLV22V10-10PC
used in this design example.
Name
Partno
Date
Revision
Designer
Company
Assembly
Location
Device
Format
UNISA22;
PLD001;
03/23/99;
0;
Ralph Gibson;
Advanced Micro Devices;
UltraNAND(TM) ISA Development Board Interface Solution;
U1;
P22V10;
J;
/****************************************************************************\
** This is a simple interface for UltraNAND allowing one UltraNAND to be
**
** supported on a PC ISA bus. This device includes a RESET input to force **
** WP# asserted on power transitions. RESET is high until Vcc is valid
**
** and goes high when supply power ramps down.
**
\****************************************************************************/
/**
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Inputs
1
2
[3..6]
7
8
9
10
/**
Outputs
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
23
22
21
20
19
[18..16]
15
14
**/
=
=
=
=
=
=
=
!WRITE;
!READ;
[A0..3];
!CE;
RY_BY;
RESET;
INIT;
/* System Write Enable
/* System Read Enable
/* Address input to select port
/* Chip Enable for the interface and UltraNAND
/* RY/BY# input from UltraNAND
/* RESET - high for reset and power transitions
/* INIT from the optional Boot Loader PLD
*/
*/
*/
*/
*/
*/
*/
**/
=
=
=
=
=
=
=
=
READY;
CLE;
ALE;
!SE;
!WP;
[!OUTCE0..2];
!WE;
!RE;
/* Allows system to read RY/BY#
/* Command Latch Enable to
/* Address Latch Enable to
/* Spare Area Enable to
/* Write Protect to
/* Chip Enables to
/* Write Enable to
/* Read Enable to
pin state
UltraNAND
UltraNAND
UltraNAND
UltraNAND
UltraNAND
UltraNAND
UltraNAND
*/
*/
*/
*/
*/
*/
*/
*/
/** Declarations and Intermediate Variable Definitions **/
PORT0 =
#
PORT1 =
#
PORT2 =
#
14
CE
INIT
CE
INIT
CE
INIT
&
&
&
&
&
&
!A3
!A1
!A3
!A1
!A3
A1
&
&
&
&
&
&
!A2 & !A1 & !A0
!A0;
!A2 & !A1 & A0
A0;
!A2 & A1 & !A0
!A0;
/* Data read/write port */
/* CLE write port */
/* Used to set ALE */
Simple System Interface for UltraNAND™ Flash
PORT3 =
#
PORT4 =
PORT5 =
PORT6 =
PORT7 =
PORT8 =
PORT9 =
PORTA =
PORTB =
PORTC =
PORTD =
PORTE =
PORTF =
/**
CE
INIT
CE
CE
CE
CE
CE
CE
CE
CE
CE
CE
CE
CE
&
&
&
&
&
&
&
&
&
&
&
&
&
&
!A3
A1
!A3
!A3
!A3
!A3
A3
A3
A3
A3
A3
A3
A3
A3
Logic Equations
&
&
&
&
&
&
&
&
&
&
&
&
&
&
!A2 &
A0;
A2 &
A2 &
A2 &
A2 &
!A2 &
!A2 &
!A2 &
!A2 &
A2 &
A2 &
A2 &
A2 &
A1 &
!A1
!A1
A1
A1
!A1
!A1
A1
A1
!A1
!A1
A1
A1
&
&
&
&
&
&
&
&
&
&
&
&
A0
!A0;
A0;
!A0;
A0;
!A0;
A0;
!A0;
A0;
!A0;
A0;
!A0;
A0;
/* Used to clear ALE */
/* Used to set SE#
/* Used to clear SE#
/* Used to set WP#
/* Used to clear WP#
/* Used to set OUTCE#
/* Used to clear OUTCE#
/* No Function
/* No Function
/* No Function
/* No Function
/* No Function
/* To read RY/BY# state
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
**/
READY.OE = PORTF & READ;
/* READY is only driven during a PORTF read */
READY
= RY_BY; /* READY shows the state of RY/BY# */
CLE
= PORT1; /* Assert CLE on all PORT1 accesses */
ALE
= !RESET & ( WRITE & PORT2
/* Latch ALE on write to PORT2 */
# ALE & !( WRITE & PORT3 ) /* and clear on write to PORT3 */
# ALE & PORT2 );
/* Transparent latch cover term */
SE
=
#
#
#
RESET
WRITE & PORT4
SE & !( WRITE & PORT5 )
SE & PORT4;
/* Latch SE# asserted on RESET
/* Latch SE# on write to PORT4
/* and clear on write to PORT5
/* Transparent latch cover term
*/
*/
*/
*/
WP
=
#
#
#
RESET
WRITE & PORT6
WP & !( WRITE & PORT7 )
WP & PORT6;
/* Latch WP# asserted on RESET
/* Latch WP# on write to PORT6
/* and clear on write to PORT7
/* Transparent latch cover term
*/
*/
*/
*/
OUTCE0
= !RESET &
#
#
#
( INIT
/* Latch OUTCE# asserted on INIT
WRITE & PORT8
/* Latch OUTCE# on write to PORT2 and
OUTCE0 & !( WRITE & PORT9 ) /* clear on write to PORT3
OUTCE0 & PORT8 );
/* Transparent latch cover term
*/
*/
*/
*/
OUTCE1
= !RESET &
#
#
#
( INIT
/* Latch OUTCE# asserted on INIT
WRITE & PORTA
/* Latch OUTCE# on write to PORT2 and
OUTCE1 & !( WRITE & PORTB ) /* clear on write to PORT3
OUTCE1 & PORTA );
/* Transparent latch cover term
*/
*/
*/
*/
OUTCE2
= !RESET &
#
#
#
( INIT
/* Latch OUTCE# asserted on INIT
WRITE & PORTC
/* Latch OUTCE# on write to PORT2 and
OUTCE2 & !( WRITE & PORTD ) /* clear on write to PORT3
OUTCE2 & PORTC );
/* Transparent latch cover term
*/
*/
*/
*/
WE
= WRITE & ( PORT0
# PORT1 );
RE
= READ & PORT0;
/* Drive WE# to UltraNAND for PORT0 or PORT1 */
/* Drive RE# to UltraNAND for PORT0 only */
Simple System Interface for UltraNAND™ Flash
15
PLD Simulation File for UNISA22
The simulation file included here is used to verify the design of the PLD supporting up to three UltraNAND banks.
Name
Partno
Date
Revision
Designer
Company
Assembly
Location
UNISA22;
PLD001;
03/23/99;
0;
Ralph Gibson;
Advanced Micro Devices;
UltraNAND(TM) ISA Development Board Interface Solution;
U1;
/****************************************************************************\
** This is a simple interface for UltraNAND allowing one UltraNAND to be
**
** supported on a PC ISA bus. This device includes a RESET input to force **
** WP# asserted on power transitions. RESET is high until Vcc is valid
**
** and goes high when supply power ramps down.
**
******************************************************************************
** Allowable Target Device Types:
AmPALCE22V10-10 **
\****************************************************************************/
ORDER: RESET, %1, !WRITE, %1, !READ, %1, !CE, %1,
A3, %1, A2, %1, A1, %1, A0, %1, INIT, %1, RY_BY, %2,
CLE, %1, ALE, %1, !SE, %1, !WP, %1,
!OUTCE0, %1, !OUTCE1, %1, !OUTCE2, %1, !WE, %1, !RE, %1, READY;
VECTORS:
$msg
$msg
$msg
$msg
$msg
$msg
$msg
$msg
/*
/*
/*
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*/
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Simple System Interface for UltraNAND™ Flash
";
";
";
";
";
";
";
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
Reset the device
Reset the device
no function
no function
no function
Set OUTCE0#
idle
Set OUTCE1#
idle
Set OUTCE2#
idle
Write command-CLE
idle
Set ALE
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
V0015
V0016
V0017
V0018
V0019
V0020
V0021
V0022
V0023
V0024
V0025
V0026
V0027
V0028
V0029
V0030
V0031
V0032
V0033
V0034
V0035
V0036
V0037
V0038
V0039
V0040
V0041
V0042
V0043
V0044
V0045
V0046
V0047
V0048
V0049
V0050
V0051
V0052
V0053
V0054
V0055
V0056
V0057
V0058
V0059
V0060
V0061
V0062
V0063
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
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*/
*/
*/
*/
*/
*/
*/
*/
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*/
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*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
0
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Simple System Interface for UltraNAND™ Flash
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
idle
Write address
idle
Write address
idle
Write address
idle
Write address
idle
Clear ALE
idle
Clear SE#
idle
Clear WP#
idle
Write data
idle
Write data
idle
Set WP#
idle
Write command-CLE
idle
Set ALE
idle
Write address
idle
Write address
idle
Write address
idle
Clear ALE
idle
Set SE#
idle
Read RY/BY# status
idle
Read RY/BY# status
idle
Read RY/BY# status
idle
Read RY/BY# status
idle
Read data
idle
Read data
idle
Clear SE#
idle
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
17
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
18
V0064
V0065
V0066
V0067
V0068
V0069
V0070
V0071
V0072
V0073
V0074
V0075
V0076
V0077
V0078
V0079
V0080
V0081
V0082
V0083
V0084
V0085
V0086
V0087
V0088
V0089
V0090
V0091
V0092
V0093
V0094
V0095
V0096
V0097
V0098
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Simple System Interface for UltraNAND™ Flash
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set SE#
idle
Initialize
Write command-CLE
idle
Set ALE
idle
Write address
idle
Write address
idle
Write address
idle
Clear ALE
idle
Read data
idle
Read data
idle
Reset the device
idle
Set OUTCE0#
idle
Set OUTCE1#
idle
Set OUTCE2#
idle
idle
Clear OUTCE0#
idle
Clear OUTCE1#
idle
Clear OUTCE2#
idle
idle
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
AmPALLV22V10-10PC
WRITE#
1
24
VCC
READ#
2
23
READY
A0
3
22
CLE
A1
4
21
ALE
A2
5
20
SE#
A3
6
19
WP#
CE#
7
18
OUTCE0#
RY/BY#
8
17
OUTCE1#
RESET#
9
16
OUTCE2#
INIT
10
15
WE#
NC
11
14
RE#
VSS
12
13
NC
Note:
The AmPALLV22V10-10PC is a 3.3 Volt PLD device.
Figure 5.
Example PLD Implementation (Three Bank Support)
I/O[0..7]
UltraNAND
3.3VCC
VCC
U2
44
23
2
3
40
5
4
42
WRITE#
Simple System
Interface PLD
U1
READ#
A[0..3]
A[0..3]
WRITE#
READ#
A0
A1
A2
A3
CE#
RY/BY#
RESET
INIT
CE#
RESET
INIT
1
2
3
4
5
6
7
8
9
10
11
13
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
23
22
21
20
19
18
17
16
15
14
43
READY
CLE
ALE
SE#
WP#
OUTCE0#
OUTCE1#
OUTCE2#
WE#
RE#
READ
WRITE
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Data
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Status
Address (ALE set) or Data (ALE cleared)
Command
Set ALE
Clear ALE
Set SE#
Clear SE#
Set WP#
Clear WP#
Set CE0#
Clear CE0#
Set CE1#
Clear CE1#
Set CE2#
Clear CE2#
N/A
N/A
SE#
WP#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
18
19
20
21
24
25
26
27
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
VCC
R1
10K
WE#
RE#
CE#
RY/BY#
RY/BY#
41
U3
40
5
4
42
PORT
CLE
ALE
UltraNAND
44
23
2
3
SIMPLE SYSTEM INTERFACE PLD
VCC
VCCQ
Am30LV0064D
I/O6
AmPALCE22V10-10PC
I/O[0..7]
43
VCC
VCCQ
CLE
ALE
SE#
WP#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
18
19
20
21
24
25
26
27
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
WE#
RE#
CE#
RY/BY#
41
Am30LV0064D
UltraNAND
U4
44
23
2
3
40
5
4
42
43
VCC
VCCQ
CLE
ALE
SE#
WP#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
18
19
20
21
24
25
26
27
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
WE#
RE#
CE#
RY/BY#
41
Am30LV0064D
Ralph Gibson - Senior Strategic Marketing Engineer
AMD Mass Storage Memory Group
Title
ISA Development Board for UltraNAND(TM)
Size
B
Date:
Document Number
Rev
ISA CARD 2.DSN
Wednesday, March 24, 1999
Sheet
0
1
of
1
Figure 6. Schematic Diagram for PLD with Support for Three UltraNAND Banks
Simple System Interface for UltraNAND™ Flash
19
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Printed in USA
4/XX/99
22363A