NSC MM54HC27

MM54HC27/MM74HC27
Triple 3-Input NOR Gate
General Description
Features
These NOR gates utilize advanced silicon-gate CMOS technology, to achieve operating speeds similar to LS-TTL gates
with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs, providing
high noise immunity and the ability to drive 10 LS-TTL loads.
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Y
Y
Y
Y
Y
Typical propagation delay: 8 ns
Wide operating supply voltage range: 2 – 6V
Low input current: k 1 mA
Low quiescent supply current: 20 mA maximum
(74HC Series)
Fanout of 10 LS-TTL Loads
Connection and Logic Diagrams
Dual-In-Line Package
TL/F/5300 – 1
Top View
Order Number MM54HC27 or MM74HC27
TL/F/5300 – 2
C1995 National Semiconductor Corporation
TL/F/5300
RRD-B30M105/Printed in U. S. A.
MM54HC27/MM74HC27 Triple 3-Input NOR Gate
January 1988
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
DC Input or Output Voltage
(VIN,VOUT)
b 0.5 to a 7.0V
b 1.5 to VCC a 1.5V
Operating Temp. Range (TA)
MM74HC
MM54HC
b 0.5 to VCC a 0.5V
g 20 mA
g 25 mA
Min
2
Max
6
Units
V
0
VCC
V
b 40
b 55
a 85
a 125
§C
§C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(tr, tf)
VCC e 2.0V
VCC e 4.5V
VCC e 6.0V
g 50 mA
b 65§ C to a 150§ C
600 mW
500 mW
260§ C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA e 25§ C
VCC
74HC
TA eb40 to 85§ C
Typ
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
VOH
Minimum High Level
Output Voltage
VIN e VIL
lIOUTl s20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN e VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
IIN
Maximum Input
Current
VIN e VCC or GND
6.0V
g 0.1
g 1.0
g 1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN e VCC or GND
IOUT e 0 mA
6.0V
2.0
20
40
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and
IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Symbol
Parameter
tPHL, tPLH
Maximum Propagation
Delay
Conditions
Typ
Guaranteed
Limit
Units
8
15
ns
AC Electrical Characteristics VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
74HC
TA eb40 to 85§ C
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
tPHL, tPLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
45
9
8
90
18
15
113
23
19
134
27
23
ns
ns
ns
tTLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per gate)
36
5
pF
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.
Physical Dimensions inches (millimeters)
Order Number MM54HC27J or MM74HC27J
NS Package Number J14A
3
MM54HC27/MM74HC27 Triple 3-Input NOR Gate
Physical Dimensions inches (millimeters) (Continued)
Order Number MM74HC27N
NS Package Number N14A
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