REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 REV STATUS REV OF SHEETS SHEET PMIC N/A PREPARED BY Gary Zahn STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A 1 2 3 4 5 7 8 9 10 11 12 13 DEFENSE SUPPLY CENTER COLUMBUS POST OFFICE BOX 3990 COLUMBUS, OHIO 43216-5000 http://www.dscc.dla.mil CHECKED BY Michael C. Jones APPROVED BY Raymond Monnin 6 MICROCIRCUIT, LINEAR, PHASE SHIFT RESONANT CONTROLLER, MONOLITHIC SILICON DRAWING APPROVAL DATE 02-01-31 REVISION LEVEL SIZE A CAGE CODE 5962-02506 67268 SHEET DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 1 OF 15 5962-E164-02 14 1. SCOPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 Federal stock class designator \ RHA designator (see 1.2.1) 02506 01 Device type (see 1.2.2) / H Device class designator (see 1.2.3) X Case outline (see 1.2.4) X Lead finish (see 1.2.5) \/ Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 1/ Generic number 01 52447 Circuit function Phase shift resonant controller UVLO Turn-on UVLO Turn-off 10.75 V 9.25 V 1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class 1/ Device performance documentation K Highest reliability class available. This level is intended for use in space applications. H Standard military quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing version of the standard military quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C, and D). E Designates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature range. Device type may be similar to the device type on Standard Microcircuit Drawing (SMD) 5962-94555. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 2 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator X Terminals CQCC1-N28B Package style 28 Square leadless chip carrier with thermal pads 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 1/ Supply voltage (VC, VIN) .......................................................................... Output current, source or sink: DC ......................................................................................................... Pulse (0.5 µs) ........................................................................................ Analog I/O pins ....................................................................................... Operating junction temperature (TJ)........................................................ Storage temperature range..................................................................... Lead temperature (soldering, 10 seconds) ............................................. Thermal resistance, junction-to-case (θJC).............................................. Thermal resistance, junction-to-ambient (θJA): Case R .................................................................................................. Cases X and 3 ....................................................................................... 20 V 0.5 A 3A -0.3 V to 5.3 V 150°C -65°C to +150°C 300°C See MIL-STD-1835 85°C/W 65°C/W 1.4 Recommended operating conditions. Supply voltage (VC, VIN) .............................................................. Ambient operating temperature range (TA) ................................. 12 V -55°C to +125°C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. 1/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 3 HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all tests herein or as designated in the device manufacturer's Quality Management (QM) plan or as designated for the applicable device class. The performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Logic diagram(s). The logic diagram(s) shall be as specified on figure 2. 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's vendor similar PIN may also be marked in MIL-HDBK-103 and QML-38534. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DSCC-VA) upon request. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DSCC-VA shall affirm that the manufacturer's product meets the performance requirements of MIL-PRF-38534 and herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55°C ≤ TA ≤ +125°C unless otherwise specified Group A subgroups Device type Limits 2/ Min Unit Max Supply current section Input current startup IIS VIN = 8 V, VC = 20 V, RSLOPE = open, IDELAY = 0 mA 1,2,3 01 600 µA Output switch supply current startup IIS VIN = 8 V, VC = 20 V, RSLOPE = open, IDELAY = 0 mA 1,2,3 01 100 µA Input supply current IIN 1,2,3 01 40 mA Output switch supply current IC 1,2,3 01 30 mA 1 01 Voltage reference section Output voltage VOUT TA = +25°C Load regulation VLD VREF = -10 mA 1,2,3 01 20 mV Line regulation VLN +VIN = 11 V to 20 V 1,2,3 01 10 mV Total variation VT Line, load, temperature 1,2,3 01 5.1 V 4.92 5.08 V Error amplifier section Offset voltage VIO 1,2,3 01 15 mV Input bias current IIB 1,2,3 01 3 µA Open loop voltage gain AVOL VCOMP = 1 V to 4 V 4,5,6 01 60 dB Common mode rejection ratio CMRR VCM = 1.5 V to 5.5 V 4,5,6 01 75 dB Power supply rejection ratio PSRR VIN = 11 V to 20 V 4,5,6 01 85 dB Output sink current ISI VCOMP = 1 V 1,2,3 01 1 mA See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 5 TABLE I. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ -55°C ≤ TA ≤ +125°C unless otherwise specified Group A subgroups Device type Limits 2/ Min Unit Max Error amplifier section - Continued. Output source current ISO VCOMP = 4 V 1,2,3 01 Output voltage, high VOH ICOMP = -0.5 mA 1,2,3 01 4 5 V Output voltage, low VOL ICOMP = 1 mA 1,2,3 01 0 1 V Unity gain bandwidth 3/ UGBW 4,5,6 01 5 MHz Slew rate SR 4,5,6 01 6 V/µs 3/ -0.5 mA Pulse width modulator section Zero phase shift voltage VZPS 4/ 1,2,3 01 0.55 Pulse width modulator 5/ phase shift PS VCOMP > (ramp peak + ramp offset) 4,5,6 01 98 102 0 2 VCOMP < (zero phase shift voltage) Output skew 5/ tOS Ramp to output delay tOD VCOMP < 1 V V % 9,10,11 01 ±20 ns 9,10,11 01 125 ns 4 01 1.15 MHz Oscillator section Initial accuracy IA TA = +25°C Voltage stability VS VIN = 11 V to 20 V 4,5,6 01 Total variation VT Line, temperature 1,2,3 01 Clock output pulse width tCLKO RCLK/SYNC = 3.9 kΩ 4,5,6 01 Maximum frequency fMAX RfSET = 5 kΩ 4,5,6 01 0.85 2 0.80 % 1.20 MHz 100 ns 2 MHz See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 6 TABLE I. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ -55°C ≤ TA ≤ +125°C unless otherwise specified Group A subgroups Device type Limits 2/ Min Unit Max Ramp generator / slope compensation section µA Minimum ramp current IRMIN ISLOPE = 10 µA, VfSET = VREF 1,2,3 01 Maximum ramp current IRMAX ISLOPE = 1 mA, VfSET = VREF 1,2,3 01 -0.8 mA Ramp peak, clamping level voltage VCL RfSET = 100 kΩ 1,2,3 01 3.8 V Input bias current IIB C+C/S = 3 V 1,2,3 01 Threshold voltage VTH 1,2,3 01 Delay to output tDO 9,10,11 01 -14 Current limit section 2.4 5 µA 2.6 V 150 ns -3 µA SOFT-START / reset delay section Charge current ICH VS-S = 0.5 V 1,2,3 01 -20 Discharge current IDCH VS-S = 1 V 1,2,3 01 120 µA Restart threshold voltage VRTH 1,2,3 01 4.3 V OUTPUT drivers section Output low level voltage VOL IOUT = 50 mA 1,2,3 01 0.4 V Output high level voltage VOH IOUT = -50 mA 1,2,3 01 2.5 V See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 7 TABLE I. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ -55°C ≤ TA ≤ +125°C unless otherwise specified Group A subgroups Device type Limits 2/ Unit Min Max DELAY SET section DELAY SET voltage VDS IDELAY = -500 µA DELAY time tD IDELAY = -250 µA 6/ 1,2,3 01 2.3 2.6 V 9,10,11 01 150 600 ns 1/ Unless otherwise specified, VS = +VIN = 12 V, frequency set resistance RfSET = 12 kΩ, frequency set capacitance CfSET = 330 pF, slope resistance RSLOPE = 12 kΩ, ramp capacitance CRAMP = 200 pF, DELAY SET capacitance CDS A-B = CDS C-D = 0.01 µF, DELAY SET current IDS A-B = IDS C-D = -500 µA. 2/ The algebraic convention, whereby the most negative value is a minimum and the most positive is a maximum, is used in this table. Negative current shall be defined as conventional current flow out of a device terminal. 3/ Not production tested. 4/ Zero phase shift voltage has a temperature coefficient of about -2 mV/°C. 5/ Phase shift percentage (0% = 0°, 100% = 180°) is defined as: θ = (200/T) φ % . θ is the phase shift, and φ and T are defined in figure 3. At 0% phase shift, φ is the output skew. -12 6/ Delay time can be programmed via resistors from the delay set pins to ground. Delay time = (62.5 x 10 ) seconds/ IDELAY. IDELAY = delay set voltage/RDELAY. The recommended range for IDELAY is 25 µA ≤ IDELAY ≤ 1 mA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 8 Device type 01 Case outline X Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VIN PWR GND OUTPUT B (OUT B) OUTPUT A (OUT A) NC NC DELAY SET A/B FREQ SET CLOCK/SYNC SLOPE RAMP NC NC GND NC VREF E/A OUT NC NC E/A (-) E/A (+) C/S (+) SOFTSTART DELAY SET C/D NC OUTPUT D (OUT D) OUTPUT C (OUT C) VC NC = No connection FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 9 FIGURE 2. Logic diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 10 Phase shift, output skew and delay time definitions. Duty cycle = t/T. Period = T. TDHL (A to C) = TDHL (B to D) = φ FIGURE 3. Timing diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 11 TABLE II. Electrical test requirements. MIL-PRF-38534 test requirements Subgroups (in accordance with MIL-PRF-38534, group A test table) --- Interim electrical parameters Final electrical parameters 1*,2,3,4,5,6,9,10,11 Group A test requirements 1,2,3,4,5,6,9,10,11 Group C end-point electrical parameters 1,4 Group D end-point electrical parameters 1,4 Not applicable End-point electrical parameters for radiation hardness assurance (RHA) devices * PDA applies to subgroup 1. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38534 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. Screening shall be in accordance with MIL-PRF-38534 and conducted on all devices prior to Conformance inspection (CI). The following additional criteria shall apply: a. b. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition B. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to either DSCC-VA or the acquiring activity upon request. Also, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. (2) TA = +125°C, minimum. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Conformance and periodic inspections. Conformance inspection (CI) and periodic inspection (PI) shall be in accordance with MIL-PRF-38534 and as specified herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 12 4.3.1 Group A inspection (CI). Group A inspection shall be in accordance with MIL-PRF-38534 and as follows: a. Sample size shall be 116(0) for all tests. b. Tests shall be as specified in table II herein. c. Subgroups 7, and 8 shall be omitted. 4.3.2 Group B inspection (PI). Group B inspection shall be in accordance with MIL-PRF-38534 and as follows: a. Sample size for bond strength is 22(0), resistance to solvents and die sheer is 3(0) for each test. 4.3.3 Group C inspection (PI). Group C inspection shall be in accordance with MIL-PRF-38534 and as follows: a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test, method 1005 of MIL-STD-883. Sample size is 45(0). c. (1) Test condition B. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to either DSCC-VA or the acquiring activity upon request. Also, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. (2) TA = +125°C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. Subgroup 1 shall consist of the following: (1) Temperature cycle and thermal shock. (2) Mechanical shock, constant acceleration, and PIND. (3) Physical dimensions 15(0). 4.3.4 Group D inspection (PI). Group D inspection shall be in accordance with MIL-PRF-38534. Sample size is 15(0) 4.3.5 Radiation Hardness Assurance (RHA) inspection. RHA inspection is not currently applicable to this drawing. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38534. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished in accordance with MIL-PRF-38534. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Post Office Box 3990, Columbus, Ohio 432165000, or telephone (614) 692-0536. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 13 6.6 Sources of supply. Sources of supply are listed in MIL-HDBK-103 and QML-38534. The vendors listed in MIL-HDBK103 and QML-38534 have submitted a certificate of compliance (see 3.7 herein) to DSCC-VA and have agreed to this drawing. 6.7 Abbreviations, symbols, and definitions. GND Signal ground. All voltages are measured with respect to ground (GND). The timing capacitor, on the FREQ SET pin, and bypass capacitor on the VREF pin, bypass capacitors on VIN and the ramp capacitor, on the RAMP pin, should be connected directly to the ground plane near the signal ground pin. PWR GND Power ground. VC should be bypassed with a ceramic capacitor from the VC pin to the section of the ground plane that is connected to PWR GND. Any required bulk reservoir capacitor should parallel this one. Power ground and signal ground may be joined at a signal point to optimize noise rejection and minimize DC drops. VC Output switch supply voltage. This pin supplies power to the drivers and their associated bias circuitry. Connect VC to a stable source above 3 V for normal operation, above 12 V for best performance. This supply should be bypassed directly to the PWR GND pin with low ESR, low ESL capacitors. VIN Primary chip supply voltage. This pin supplies power to the logic and analog circuitry on the integrated circuitry that is not directly associated with driving the output stages. FREQ SET Oscillator frequency set pin. A resistor and a capacitor from FREQ SET to GND will set oscillator frequency according to the following relationship: f = 4/(RfSET x CRAMP). CLK/SYNC Bi-directional clock and synchronization pin. Used as an output, this pin provides a clock signal. As an input, this pin provides a synchronization point. SLOPE Set ramp slope.slope compensation. A resistor from this pin to VCC will set the current used to generate the ramp. Connecting this resistor to the DC input line will provide voltage feed forward. RAMP Voltage ramp. This pin is the input to the pulse width modulator comparator. Connect a capacitor from here to GND. A voltage ramp is developed at this pin with a slope: (dV/dT) = (sense voltage/RSLOPE x CRAMP). E/A OUT (COMP) Error amplifier output. This is the gain stage for overall feedback control. Error amplifier output voltage levels below 1 volt will force 0° phase shift. Since the error amplifier has a relatively low current drive capability, the output may be overridden by driving with a sufficiently low impedance source. E/A(+) This pin is normally connected to a reference voltage used for comparison with the sensed power supply output voltage level at the E/A(-) pin. E/A(-) This pin is normally connected to the voltage divider resistors which sense the power supply output level. SOFT START SOFT START will remain at GND as long as VIN is below the UVLO threshold. SOFT START will be pulled up to about 4.8 V by an internal 9 µA current source when VIN becomes valid (assuming a non-fault condition). In the event of a current-fault (C/S (+) voltage exceeding 2.5 V), SOFT START will be pulled to GND and then ramp to 4.8 V. If a fault occurs during the SOFT START cycle, the outputs will be immediately disabled and SOFT START must charge fully prior to resetting the fault latch. For paralleled controllers, the SOFT START pins may be paralleled to a single capacitor, but the change currents will be additive. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 14 CURRENT SENSE (+) The positive input to the current-fault comparator whose reference is set internally to fixed 2.5 V (separate from VREF). When the voltage at this pin exceeds 2.5 V, the current-fault latch is set, the outputs are forced off and a SOFT START cycle is initiated. If a constant voltage above 2.5 V is applied to this pin the outputs are disabled from switching and held in a low state until the C/S (+) pin is brought below 2.5 V. The outputs may begin switching at 0 degrees phase shift before the SOFT START pin begins to rise, this condition will not prematurely deliver power to the load. OUTPUTS A, B, C, D The outputs are 2 A totem-pole drivers optimized for both MOSFET gates and level shifting transformers. The outputs operate as pair with a nominal 50% duty cycle. The A-B pair is intended to drive one half bridge in the external power stage and is synchronized with the clock waveform. The C-D pair will drive the other half-bridge with switching phase shifted with respect to the A-B outputs. DELAY SET A-B, DELAY SET C-D Output delay control. The users programmed current flowing from these pins to GND set the turn-on delay for the corresponding output pair. This delay is introduced between turn-off of one switch and turn-on of another in the same leg of the bridge to provide a deed time in which the resonant switching of the external power switches takes place. Separate delays are provided for the two half bridges to accommodate differences in the resonant capacitor charging currents. VREF This pin is an accurate 5 V voltage reference. This output is capable of delivering about 60 mA to peripheral circuitry and is internally short circuit current limited. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-02506 A REVISION LEVEL SHEET 15 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 02-01-31 Approved sources of supply for SMD 5962-02506 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38534 during the next revisions. MIL-HDBK-103 and QML-38534 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revisions of MIL-HDBK-103 and QML-38534. 1/ 2/ 3/ Standard microcircuit drawing PIN 1/ 2/ Vendor CAGE number Vendor similar PIN 3/ 5962-0250601HXA 31757 52447 5962-0250601HXC 31757 52447 The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the Vendor to determine its availability. Device type may be similar to the device type on Standard Microcircuit Drawing (SMD) 5962-94555. Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 31757 Vendor name and address Micropac Industries, Incorporated 905 E. Walnut Street Garland, TX 75040 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.