ETC 74LVT32374EC

INTEGRATED CIRCUITS
DATA SHEET
74LVT32374
3.3 V 32-bit edge-triggered D-type
flip-flop; 3-state
Product specification
2002 Mar 20
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
FEATURES
DESCRIPTION
• 32-bit edge-triggered flip-flop
The 74LVT32374 is a high-performance BICMOS product
designed for VCC operation at 3.3 V.
• 3-state buffers
• Output capability: +64 mA/−32 mA
The 74LVT32374 is a 32-bit edge-triggered D-type flip-flop
featuring non-inverting 3-state outputs. The device can be
used as four 8-bit flip-flops, or two 16-bit flip-flops or one
32-bit flip-flop. On the positive transition of the clock (CP),
the Q outputs of the flip-flop take on the logic levels set-up
at the D inputs.
• TTL input and output switching levels
• Input and output interface capability to systems at 5 V
supply
• Bus-hold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-state
• No bus current loading when output is tied to 5 V bus
• Latch-up protection exceeds 500 mA in accordance with
JEDEC std 17
• ESD protection exceeds 2000 V in accordance with
MIL STD 883 method 3015 and 200 V in accordance
with Machine Model.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
propagation delay nCP to nQn
CL = 50 pF; VCC = 3.3 V
TYPICAL
2.9
UNIT
ns
CI
input capacitance
VI = 0 or 3.0 V
3
pF
CO
output capacitance
outputs disabled; VO = 0 or 3.0 V
9
pF
ICCZ
total supply current
output disabled; VCC = 3.6 V
140
µA
2002 Mar 20
2
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
FUNCTION TABLE
See note 1.
INPUTS
nOE
nCP
nDn
INTERNAL
REGISTER
L
↑
l
L
L
↑
OPERATING MODE
Load and read register
Hold
L
Disable outputs
H
OUTPUTS
L
nQn
h
H
H
X
NC
NC
X
NC
Z
nDn
nDn
Z
M
↑
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW OE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW OE transition;
NC = not connected;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH CP transition;
= not a LOW-to-HIGH CP transition.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
−40 to +125 °C
96
LFBGA96
plastic
SOT536-1
74LVT32374EC
PINNING
SYMBOL
nDn
2002 Mar 20
DESCRIPTION
data input
nCP
clock input
nQn
flip-flop output
GND
ground (0 V)
nOE
output enable input (active LOW)
VCC
supply voltage
3
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
MNA497
handbook, full pagewidth
6
1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D7 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6
5
1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D6 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7
4
1CP GND VCC GND GND VCC GND 2CP 3CP GND VCC GND GND VCC GND 4CP
3
1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE
2
1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q6 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7
1
1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q7 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Fig.1 Pin configuration.
handbook, full pagewidth
1D0
D
Q
2D0
1Q0
CP
D
FF 1
2CP
1OE
2OE
to 7 other channels
D
Q
to 7 other channels
4D0
3Q0
CP
D
Q
4Q0
CP
FF 17
FF 25
3CP
4CP
3OE
4OE
to 7 other channels
to 7 other channels
Fig.2 Logic symbol.
2002 Mar 20
2Q0
FF 9
1CP
3D0
Q
CP
4
MNA498
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
handbook, halfpage
VCC
handbook, halfpage
27 Ω
VCC
data
input
to internal circuit
output
27 Ω
MNA473
MNA676
Fig.3 Schematic of each output.
Fig.4 Bus hold circuit.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN.
−2.7
MAX.
UNIT
VCC
supply voltage
VI
input voltage
0
5.5
V
VIH
HIGH-level input voltage
2.0
−
V
VIL
LOW-level input voltage
−
0.8
V
IOH
HIGH-level output current
−
−32
mA
IOL
LOW-level output current
−
32
mA
current duty cycle ≤ 50%; f ≥ 1 kHz
−
64
mA
outputs enabled
−
10
ns/V
−40
+125
°C
−
−
mW
∆t/∆V
input transition rise or fall times
Tamb
operating ambient temperature
PD
power dissipation per package
note 1
note 2
+3.6
V
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 70 °C the value of PD derates linearly with 1.8 mW/K.
2002 Mar 20
5
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
−0.5
−
+4.6
V
VI < 0
−
−50
−
mA
note 2
−0.5
−
+7.0
V
−
−50
−
mA
−
+7.0
V
128
−
mA
−
−64
−
mA
−65
−
+150
°C
VCC
supply voltage
IIK
input diode current
VI
input voltage
IOK
output diode current
VO
output voltage
output in OFF or HIGH state; note 2 −0.5
IO
output current
output in LOW state
−
output in HIGH state
Tstg
storage temperature
Notes
1. The performance capability of a high-performance integrated circuit in conjuction with its thermal environment can
create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated
circuit should not exceed 150 °C.
2. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are
observed.
2002 Mar 20
6
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb (°C)
TEST CONDITIONS
SYMBOL
−40 to +85
PARAMETER
OTHER
VCC (V)
MIN.
UNIT
TYP.(1)
MAX.
VIK
input clamp voltage
IIK = −18 mA
2.7
−
−0.85
−1.2
V
VOH
HIGH-level output voltage
IOH = −32 mA
3.0
2.0
2.3
−
V
VOL
LOW-level output voltage
IOL = 64 mA
3.0
−
0.4
0.55
V
VRST
power-up output LOW
voltage
IO = −1 mA; VI = GND or VCC;
note 2
3.6
−
0.1
0.55
V
II
input leakage current
VI = VCC or GND; control pins
3.6
−
0.1
±1
µA
Ioff
output OFF current
Ihold
bus hold current D inputs
VI = 5.5 V
0 or 3.6
−
0.4
10
µA
VI = VCC; data pins; note 3
3.6
−
0.1
1
µA
VI = 0 V; data pins; note 3
3.6
−
−0.4
−5
µA
VI or VO = 0 to 4.5 V
0
−
0.1
±100
µA
VI = 0.8 V; note 4
3.0
75
135
−
µA
VI = 2.0 V; note 4
3.0
−75
−135
−
µA
VCC = 3.6 V; note 4
0 to 3.6
±500
−
−
µA
IEX
current into an output in the
HIGH state when VO > VCC
VO = 5.5 V
3.0
−
50
125
µA
Ipu/pd
power-up/down 3-state
output current
VO = 5.5 V to VCC;
VI = GND or VCC; VOE = don’t
care; note 5
≤ 1.2 V
−
1
±100
µA
IOZH
3-state output HIGH current VO = 3.0 V; VI = VIH or VIL
3.6
−
0.5
5
µA
IOZL
3-state output LOW current
VO = 0.5 V; VI = VIH or VIL
3.6
−
+0.5
−5
µA
ICCH
quiescent supply current
outputs HIGH; IO = 0;
VI = GND or VCC
3.6
−
0.14
0.24
mA
ICCL
quiescent supply current
outputs LOW; IO = 0;
VI = GND or VCC
3.6
−
8
12
mA
ICCZ
quiescent supply current
outputs disabled; IO = 0;
VI = GND or VCC; note 6
3.6
−
0.14
0.24
mA
∆ICC
additional supply current
per input pin
one input at VCC − 0.6 V; other 3.0 to 3.6 −
inputs at GND or VCC; note 7
0.1
0.2
µA
Notes
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
3. Unused pins at VCC or GND.
4. This is the bus hold overdrive current required to force the input to the opposite logic state.
5. This parameter is valid for any VCC between 0 and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to
VCC = 3.3 ±0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
6. ICCZ is measured with outputs pulled to VCC or GND.
7. This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
2002 Mar 20
7
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
SYMBOL
PARAMETER
VCC = 3.3 ±0.3 V
WAVEFORMS
TYP.(1)
MIN.
tPLH/tPHL
propagation delay
nCP to nQn
see Fig.5
tPZH/tPZL
output enable time to
HIGH and LOW level
see Figs 7 and 8
tPHZ/tPLZ
output disable time from
HIGH and LOW level
see Figs 7 and 8
fmax
maximum clock pulse
frequency
see Fig.5
VCC = 2.7 V
MAX.
UNIT
MAX.
1.5
3.0
5.3
6.2
ns
1.5
3.0
4.9
5.1
ns
1.5
3.5
5.6
6.9
ns
1.5
3.2
4.9
6.0
ns
1.5
3.5
5.4
5.7
ns
1.5
3.2
5.0
5.1
ns
150
−
−
−
MHz
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
AC SETUP REQUIREMENTS
GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 Ω; Tamb = −40 to +125 °C.
SYMBOL
PARAMETER
WAVEFORMS
VCC = 3.3 ±0.3 V
VCC = 2.7 V
TYP.(1)
MIN.
UNIT
MIN.
tsuH
set-up time nDn HIGH to nCP
tsuL
set-up time nDn LOW to nCP
see Fig.6
2.5
0.7
2.5
ns
thH
hold time nDn HIGH to nCP
see Fig.6
0.5
0
0
ns
thL
hold time nDn LOW to nCP
see Fig.6
0.5
0
0
ns
tWH
nCP HIGH pulse width
see Fig.6
1.5
0.6
1.5
ns
tWL
nCP LOW pulse width
see Fig.6
3.0
1.6
3.0
ns
2002 Mar 20
see Fig.6
2.5
8
0.7
2.5
ns
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
AC WAVEFORMS
1/fmax
handbook, full pagewidth
2.7 V
nCP input
VM
VM
t PHL
t PLH
0V
VOH
VM
nQn output
VOL
MNA677
VM = 1.5 V;
VM = GND to 3.0 V.
Fig.5
Clock (nCP) to output (nQn) propagation delays, the clock pulse width and the maximum clock pulse
frequency.
2.7 V
handbook, full pagewidth
nDn input
VM
0V
t hH
t hL
t suH
t suL
2.7 V
VM
nCP input
0V
t WH
t WL
MNA678
The shades areas indicate when the input is permitted to change for predicable output performance.
Fig.6 Set-up and hold times for inputs (nDn) to inputs (nCP).
2002 Mar 20
9
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
2.7 V
handbook, full pagewidth
VM
nOE input
VM
0V
t PHZ
t PZH
VOH
VOH − 0.3 V
VM
nQn output
0V
MNA679
Fig.7 3-state output enable time to HIGH level and output disable time from HIGH level.
2.7 V
handbook, full pagewidth
VM
nOE input
VM
0V
t PHZ
t PZH
3V
VM
nQn output
VOH
VOL + 0.3 V
MNA680
Fig.8 3-state output enable time to LOW level and output disable time from LOW level.
2002 Mar 20
10
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
6V
open
GND
handbook, full pagewidth
VCC
PULSE
GENERATOR
VIN
RL
VOUT
D.U.T.
RT
RL
CL
MNA681
TEST
S1
tPLH/tPHL
open
tPLZ/tPZL
6V
tPHZ/tPZH
GND
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.9 Load circuitry for switching times.
tW
handbook, full pagewidth
AMP (V)
90%
90%
negative
pulse
VM
VM
10%
0V
10%
tf
tr
AMP (V)
tf
tr
90%
positive
pulse
90%
VM
0V
VM
10%
10%
tW
MNA682
INPUT PULSE REQUIREMENTS
FAMILY
74LVT32xxx
AMPLITUDE
PULSE RATE
2.7 V
≤ 10 MHz
tW
500 ns
tr
≤ 2.5 ns
Fig.10 Input pulse definition.
2002 Mar 20
11
tf
≤ 2.5 ns
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
PACKAGE OUTLINE
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
A
B
D
ball A1
index area
A
A2
E
A1
detail X
e1
C
v M B
b
e
∅w M
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
y1 C
v M A
y
e
e2
X
1 2 3 4 5 6
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.5
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
0.8
4.0
12.0
0.15
0.1
0.1
0.2
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
5
10 mm
scale
EUROPEAN
PROJECTION
ISSUE DATE
99-12-02
00-03-04
SOT536-1
2002 Mar 20
0
12
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
SOLDERING
74LVT32374
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Mar 20
13
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Mar 20
14
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
DATA SHEET STATUS
DATA SHEET STATUS(1)
PRODUCT
STATUS(2)
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Mar 20
15
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SCA74
© Koninklijke Philips Electronics N.V. 2002
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Date of release: 2002
Mar 20
Document order number:
9397 750 08898