MF5 Universal Monolithic Switched Capacitor Filter General Description Features The MF5 consists of an extremely easy to use, general purpose CMOS active filter building block and an uncommitted op amp. The filter building block, together with an external clock and a few resistors, can produce various second order functions. The filter building block has 3 output pins. One of the output pins can be configured to perform highpass, allpass or notch functions and the remaining 2 output pins perform bandpass and lowpass functions. The center frequency of the filter can be directly dependent on the clock frequency or it can depend on both clock frequency and external resistor ratios. The uncommitted op amp can be used for cascading purposes, for obtaining additional allpass and notch functions, or for various other applications. Higher order filter functions can be obtained by cascading several MF5s or by using the MF5 in conjuction with the MF10 (dual switched capacitor filter building block). The MF5 is functionally compatible with the MF10. Any of the classical filter configurations (such as Butterworth, Bessel, Cauer and Chebyshev) can be formed. Y Y Y Y Y Y Y Y Y Y Low cost 14-pin DIP or 14-pin Surface Mount (SO) wide-body package Easy to use Clock to center frequency ratio accuracy g 0.6% Filter cutoff frequency stability directly dependent on external clock quality Low sensitivity to external component variations Separate highpass (or notch or allpass), bandpass, lowpass outputs fo c Q range up to 200 kHz Operation up to 30 kHz (typical) Additional uncommitted op-amp Block and Connection Diagrams TL/H/5066 – 1 All Packages Order Number MF5CN See NS Package Number N14A Order Number MF5CWM See NS Package Number M14B Top View C1995 National Semiconductor Corporation TL/H/5066 TL/H/5066 – 2 RRD-B30M115/Printed in U. S. A. MF5 Universal Monolithic Switched Capacitor Filter February 1995 Absolute Maximum Ratings See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface mount devices. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (V a b Vb) Input Voltage (any pin) 14V Power Dissipation TA e 25§ C (note 1) Storage Temp. Soldering Information: N Package: 10 sec. SO Package: Vapor phase (60 sec.) Infrared (15 sec.) 500 mW 150§ C Vb s Vin s V a Operating Temp. Range MF5CN, MF5CWM TMIN s TA s TMAX 0§ C s TA s 70§ C 260§ C 215§ C 220§ C Electrical Characteristics V a e 5V g 0.5%, Vb e b5V g 0.5% unless otherwise noted. Boldface limits apply over temperature, TMIN s TA s TMAX. For all other limits TA e 25§ C. Parameter Supply Voltage (V a b Vb) Tested Limit (Note 7) Design Limit (Note 8) Units Min 8 V Max 14 V Maximum Supply Current Clock Feedthrough Typical (Note 6) Conditions Clock applied to Pin 8 No Input Signal 4.5 6.0 mA Filter Output 10 mV Op-amp Output 10 mV Filter Electrical Characteristics V a e 5V g 0.5%, Vb e b5V g 0.5% unless otherwise noted. Boldface limits apply over temperature, TMIN s TA s TMAX. For all other limits TA e 25§ C. Parameter Typical (Note 6) Conditions Tested Limit (Note 7) Design Limit (Note 8) Units kHz Center Frequency Range (fo) Max 30 20 Min 0.1 0.2 Hz Clock Frequency Range (fCLK) Max 1.5 1.0 MHz 10 Hz Min 5.0 Clock to Center Frequency Ratio (fCLK/fo) Ideal Q e 10 Mode 1 fCLK/fo Temp. Coefficient Vpin9 e a 5V (50:1 CLK ratio) g 10 ppm/§ C Vpin9 e b5V (100:1 CLK ratio) g 20 ppm/§ C Q Accuracy (Max) (Note 2) Ideal Q e 10 Mode 1 Q Temperature Coefficient Vpin9 e a 5V FCLK e 250 kHz 50.11 g 0.2% 50.11 g 1.5% Vpin9 e b5V FCLK e 500 kHz 100.04 g 0.2% 100.04 g 1.5% Vpin9 e a 5V FCLK e 250 kHz g 10 % Vpin9 e b5V FCLK e 500 kHz g 10 % Vpin9 e a 5V (50:1 CLK ratio) Vpin9 e b5V (100:1 CLK ratio) DC Lowpass Gain Accuracy (Max) DC Offset Voltage (Max) (Note 3) b 200 ppm/§ C b 70 ppm/§ C Mode 1 R1 e R2 e 10 kX g 0.2 Vos1 dB g 5.0 mV Vos2 Vpin9 e a 5V b 185 mV Vos3 (50:1 CLK ratio) a 115 mV Vos2 Vpin9 e b5V b 310 mV Vos3 (100:1 CLK ratio) a 240 mV 2 Filter Electrical Characteristics V a e 5V g 0.5%, Vb e b5V g 0.5% unless otherwise noted. Boldface limits apply over temperature, TMIN s TA s TMAX. For all other limits TA e 25§ C. (Continued) Parameter Output Swing (Min) Conditions BP, LP pins RL e 5 kX RL e 3.5 kX N/AP/HP pin Dynamic Range (Note 4) Maximum Output Short Circuit Current (Note 5) Typical (Note 6) Tested Limit (Note 7) g 4.0 g 3.8 g 4.2 g 3.8 Design Limit (Note 8) Units V V Vpin9 e a 5V (50:1 CLK ratio) 83 dB Vpin9 e b5V (100:1 CLK ratio) 80 dB Source 20 mA Sink 3.0 mA OP-AMP Electrical Characteristics V a e a 5V g 0.5%, Vb e b5V g 0.5% unless other noted. Boldface limits apply over temperature, TMIN s TA s TMAX. For all other limits TA e 25§ C. Parameter Conditions Typical (Note 6) RL e 3.5 kX g 4.2 Gain Bandwidth Product Tested Limit (Note 7) Design Limit (Note 8) 2.5 Output Voltage Swing (Min) Slew Rate MHz g 3.8 V 7.0 DC Open-Loop Gain db g 5.0 Input Bias Current Maximum Output Short Circuit Current (Note 5) V/ms 80 Input Offset Voltage (Max) Source Sink Units g 20 mV 10 pA 20 mA 3.0 mA Logic Input Characteristics Boldface limits apply over temperature, TMIN s TA s TMAX. All other limits TA e 25§ C. Parameter CMOS Clock Input Min Logical ‘‘1’’ Input Voltage Max Logical ‘‘0’’ Input Voltage Min Logical ‘‘1’’ Input Voltage Max Logical ‘‘0’’ Input Voltage TTL Clock Input Min Logical ‘‘1’’ Input Voltage Max Logical ‘‘0’’ Input Voltage Typical (Note 6) Conditions Tested Limit (Note 7) Design Limit (Note 8) Units 3.0 V b 3.0 V 8.0 V 2.0 V 2.0 V 0.8 V V a e a 5V, Vb e b5V, VL.Sh. e 0V V a e a 10V, Vb e 0V, VL.Sh. e a 5V V a e a 5V, Vb e b5V, VL.Sh. e 0V Note 1: The typical junction-to-ambient thermal resistance (iJA) of the 14 pin N package is 160§ C/W, and 82§ C/W for the M package. Note 2: The accuracy of the Q value is a function of the center frequency (fo). This is illustrated in the curves under the heading ‘‘Typical Performance Characteristics’’. Note 3: Vos1, Vos2, and Vos3 refer to the internal offsets as discussed in the Application Information section 3.4. Note 4: For g 5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 mV rms for the MF5 with a 50:1 CLK ratio and 280 mV rms for the MF5 with a 100:1 CLK ratio. Note 5: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions. Note 6: Typicals are at 25§ C and represent most likely parametric norm. Note 7: Guaranteed and 100% tested. Note 8: Guaranteed, but not 100% tested. These limits are not used to calculate outgoing quality levels. 3 Pin Description LP(14), BP(1), N/AP/HP(2): INV1(3): S1(4): SA(5): 50/100(9): AGND(11): V a (6), Vb(10): The second order lowpass, bandpass, and notch/allpass/highpass outputs. The LP and BP outputs can typically sink 1 mA and source 3 mA. The N/AP/HP output can typically sink 1.5 mA and source 3 mA. Each output typically swings to within 1V of each supply. The inverting input of the summing op amp of the filter. This is a high impedance input, but the non-inverting input is internally tied to AGND, making INV1 behave like a summing junction (low impedance current input). S1 is a signal input pin used in the allpass filter configurations (see modes 4 and 5). The pin should be driven with a source impedance of less than 1 kX. If S1 is not driven with a signal it should be tied to AGND (mid-supply). This pin activates a switch that connects one of the inputs of the filter’s second summer to either AGND (SA tied to Vb) or to the lowpass (LP) output (SA tied to V a ). This offers the flexibility needed for configuring the filter in its various modes of operation. This pin is used to set the internal clock to center frequency ratio (fCLK/fo) of the filter. By tying the pin to V a an fCLK/fo ratio of about 50:1 (typically 50.11 g 0.2%) is obtained. Tying the 50/100 pin to either AGND or Vb will set the fCLK/fo ratio to about 100:1 (typically 100.04 g 0.2%). This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information (Section 3.2). For optimum filter performance a ‘‘clean’’ ground must be provided. CLK(8): L. Sh(7): INV2(12): Vo2(13): These are the positive and negative supply pins. The MF5 will operate over a total supply range of 8V to 14V. Decoupling the supply pins with 0.1 mF capacitors is highly recommended. This is the clock input for the filter. CMOS or TTL logic level clocks can be accomodated by setting the L. Sh pin to the levels described in the L. Sh pin description. For optimum filter performance a 50% duty cycle clock is recommended for clock frequencies greater than 200 kHz. This gives each op amp the maximum amount of time to settle to a new sampled input. This pin allows the MF5 to accommodate either CMOS or TTL logic level clocks. For dual supply operation (i.e., g 5V), a CMOS or TTL logic level clock can be accepted if the L. Sh pin is tied to mid-supply (AGND), which should be the system ground. For single supply operation the L. Sh pin should be tied to mid-supply (AGND) for a CMOS logic level clock. The mid-supply bias should be a very low impedance node. See Applications Information for biasing techniques. For a TTL logic level clock the L. Sh pin should be tied to Vb which should be the system ground. This is the inverting input of the uncommitted op amp. This is a very high impedance input, but the non-inverting input is internally tied to AGND, making INV2 behave like a summing junction (low-impedance current input). This is the output of the uncommitted op amp. It will typically sink 1.5 mA and source 3.0 mA. It will typically swing to within 1V of each supply. Typical Performance Characteristics Deviation of FCLK vs Nominal Q Fo Deviation of FCLK vs Nominal Q Fo OPAMP Output Voltage Swing vs Temperature TL/H/5066 – 3 4 observed as the frequency of a notch at the allpass output. (Figure 10 ). Typical Performance Characteristics (Continued) Q: ‘‘quality factor’’ of the 2nd order filter. Q is measured at the bandpass output of the MF5 and is equal to fo divided by the b3dB bandwidth of the 2nd order bandpass filter (Figure 1 ). The value of Q determines the shape of the 2nd order filter responses as shown in Figure 6 . Qz: the quality factor of the second order complex zero pair, if any. Qz is related to the allpass characteristic, which is written: Supply Current vs Temperature HOAP HAP(s) e #s 2b s0o a 0o2 Qz J s0o a 0o2 s2 a Q where Qz e Q for an all-pass response. HOBP: the gain (in V/V) of the bandpass output at f e fo. HOLP: the gain (in V/V) of the lowpass output as f x 0 Hz (Figure 2 ). HOHP: the gain (in V/V) of the highpass output as f x fclk/2 (Figure 3 ). HON: the gain (in V/V) of the notch output as f x 0 Hz and as f x fclk/2, when the notch filter has equal gain above and below the center frequency (Figure 4 ). When the lowfrequency gain differs from the high-frequency gain, as in modes 2 and 3a (Figures 11 and 8 ), the two quantities below are used in place of HON. HON1: the gain (in V/V) of the notch output as f x 0 Hz. HON2: the gain (in V/V) of the notch output as f x fclk/2. TL/H/5066 – 4 1.0 Definitions of Terms fCLK: the frequency of the external clock signal applied to pin 8. fo: center frequency of the second order function complex pole pair. fo is measured at the bandpass output of the MF5, and is the frequency of maximum bandpass gain. (Figure 1 ). fnotch: the frequency of minimum (ideally zero) gain at the notch output. fz: the center frequency of the second order complex zero pair, if any. If fz is different from fo and if Qz is high, it can be 0o s HOBP Q s0o 2 a 0o2 s a Q HBP(s) e Qe fo ; fH b fL # 2Q 0 # 2Q J 1 1 f # 2Q 0 # 2Q J fL e fo (a) TL/H/5066–5 (b) TL/H/5066 – 6 f o e 0f Lf H b1 1 a fH e o 2 a a1 2 a1 0 o e 2 q fo J J FIGURE 1. 2nd-Order Bandpass Response HOLP0o2 s0o a 0o2 Q HLP(s) e s2 a fc e fo c fp e fo (a) TL/H/5066–7 0 0 #1 1b a 1 2Q2 b 1 2 a1 2Q2 J 1 HOP e HOLP c (b) J 0 #1 1 2Q2 b 1 Q TL/H/5066 – 8 0 1 4Q2 1b FIGURE 2. 2nd-Order Low-Pass Response HHP(s) e HOHPs2 s0o a 0o2 Q s2 a fc e fo c Ð0 # fp e fo c (a) TL/H/5066–9 (b) TL/H/5066 – 10 FIGURE 3. 2nd-Order High-Pass Response 5 Ð0 1b 1b HOP e HOHP c J 0# ( 1 a 2Q2 1 2Q2 b1 1 1 Q 0 1b 1 4Q2 1b 1 2 a1 2Q2 J ( b1 1.0 Definition of Terms (Continued) HN(s) e Qe fo ; fH b fL fL e fo fH e fo TL/H/5066–11 HON(s2 a 0o2) s0o a 0o2 s2 a Q fo e 0fLfH # 2Q 0 # 2Q J 1 1 # 2Q 0 # 2Q J b1 1 a 2 a1 2 a1 a J J TL/H/5066 – 12 (a) (b) FIGURE 4. 2nd-Order Notch Response HOAP HAP(s) e #s 2b s2 a s0o a 0o2 Q s0o a 0o2 Q J TL/H/5066 – 14 TL/H/5066–13 (b) (a) FIGURE 5. 2nd-Order All-Pass Response (a) Bandpass (b) Low-Pass (d) Notch (c) High-Pass (e) All-Pass TL/H/5066 – 15 FIGURE 6. Responses of various 2nd-order filters as a function of Q. Gains and center frequencies are normalized to unity. 6 2.0 Modes of Operation The MF5 is a switched capacitor (sampled data) filter. To fully describe its transfer functions, a time domain approach is appropriate. Since this is cumbersome, and since the MF5 closely approximates continuous filters, the following discussion is based on the well known frequency domain. Each MF5 can produce a full 2nd order function. See Table 1 for a summary of the characteristics of the various modes. MODE 1: Notch 1, Bandpass, Lowpass Outputs: fnotch e fo (See Figure 7 ) fo fo R3 e BW R2 BW e the b3 dB bandwidth of the bandpass output. Circuit dynamics: HOBP or HOBP e HOLP c Q e HON c Q. HOLP e Q HOLP(peak) j Q c HOLP (for high Q’s) Q e MODE 1a: Non-Inverting BP, LP (See Figure 8 ) f f e CLK or CLK 100 50 R3 e Q R2 HOLP e b1; HOLP(peak) j Q c HOLP (for high Q’s) e center frequency of the complex pole pair fo f f e CLK or CLK 100 50 fnotch e center frequency of the imaginary zero pair e fo. R2 HOLP e Lowpass gain (as f x 0) e b R1 R3 HOBP e Bandpass gain (at f e fo) e b R1 HON e Notch output gain as f f x0 x fCLK/2 ( e R3 R2 HOBP2 e 1 (non-inverting) Circuit dynamics: HOBP1 e Q Note: VIN should be driven from a low impedance ( k1 kX) HOBP1 e b b R2 R1 TL/H/5066 – 16 FIGURE 7. MODE 1 TL/H/5066 – 17 FIGURE 8. MODE 1a 7 2.0 Modes of Operation (Continued) MODE 2: Notch 2, Bandpass, Lowpass: fnotchkfo (See Figure 9 ) fo MODE 3: Highpass, Bandpass, Lowpass Outputs (See Figure 10 ) f R2 fCLK R2 e CLK c c or fo 100 R4 50 R4 e quality factor of the complex pole pair Q R2 R3 e c R4 R2 fCLK R2 eb HOHP e Highpass gain as f x 2 R1 R3 HOBP e Bandpass gain (at f e fo) e b R1 R4 HOLP e Lowpass gain (as f x 0) e b R1 HOHP R2 e e ; HOBP Circuit dynamics: 0HOHP c HOLP c Q R4 HOLP HOLP(peak) j Q c HOLP (for high Q’s) HOHP(peak) j Q c HOHP (for high Q’s) 0 e center frequency fnotch e Q e e HOLP e e 0 0 f R2 R2 a 1 or CLK a1 100 R4 50 R4 fCLK fCLK or 100 50 quality factor of the complex pole pair 0R2/R4 a 1 R2/R3 Lowpass output gain (as f x 0) R2/R1 b R2/R4 a 1 f e CLK 0 HOBP e Bandpass output gain (at f e fo) e bR3/R1 HON1 e Notch output gain (as f x 0) R2/R1 e b R2/R4 a 1 f HON2 e Notch output gain as f x CLK e bR2/R1 2 Filter dynamics: HOBP e Q 0HOLP HON2 e Q 0HON1 HON2 # 0 # J J TL/H/5066 – 18 FIGURE 9. MODE 2 *In Mode 3, the feedback loop is closed around the input summing amplifier; the finite GBW product of this op amp causes a slight Q enhancement. If this is a problem, connect a small capacitor (10 pF–100 pF) across R4 to provide some phase lead. TL/H/5066 – 19 FIGURE 10. MODE 3 8 2.0 Modes of Operation (Continued) MODE 3a: HP, BP, LP and Notch with External Op amp (See Figure 11 ) R2 fCLK R2 f e CLK c c or fo 100 R4 50 R4 R2 R3 e c Q R4 R2 R2 HOHP e b R1 R3 HOBP e b R1 R4 HOLP e b R1 f Rh fCLK Rh e notch frequency e CLK or fn 100 Rl 50 Rl Rg Rg e e e b Hon gain of notch at f fo Q HOLP HOHP Rl Rh Rg c HOLP Hn1 e gain of notch (as f x 0) e Rl fCLK R e b g c HOHP Hn2 e gain of notch as f x 2 Rh 0 0 MODE 4: Allpass, Bandpass, Lowpass Outputs (See Figure 12 ) e center frequency fo f f e CLK or CLK; 100 50 f*z e center frequency of the complex zero pair j fo 0 0 0 Ó # # Q e fo R3 e ; BW R2 Qz e quality factor of complex zero pair e R3 R1 For AP output make R1 e R2 H*OAP e Allpass gain # at 0 f k f k CLK 2 0) J eb R2 e b1 R1 HOLP e Lowpass gain (as f x R2 e b a 1 e b2 R1 e Bandpass gain (at f e fo) HOBP R3 R2 R3 e b e b2 1a R2 R1 R2 Circuit dynamics: HOBP e (HOLP) c Q e (HOAP a 1) Q JÓ # J # J J # J *Due to the sampled data nature of the filter, a slight mismatch of fz and fo occurs causing a 0.4 dB peaking around fo of the allpass filter amplitude response (which theoretically should be a straight line). If this is unacceptable, Mode 5 is recommended. TL/H/5066 – 20 FIGURE 11. MODE 3a TL/H/5066 – 21 FIGURE 12. MODE 4 9 2.0 Modes of Operation (Continued) MODE 6a: Single Pole, HP, LP Filter (See Figure 14 ) e cutoff frequency of LP or HP output R2 fCLK R2 fCLK e or R3 100 R3 50 R3 HOLP e b R1 R2 HOHP e b R1 MODE 5: Numerator Complex Zeros, BP, LP (See Figure 13 ) R2 fCLK R2 fCLK e c c or 1 a 1a fo R4 100 R4 50 R1 fCLK R1 fCLK e b c b c or 1 1 fz R4 100 R4 50 R3 e 01 a R2/R4 c Q R2 R3 e 01 b R1/R4 c Qz R1 b R2 (R4 b R1) H0z1 e gain at C.Z. output (as f x 0 Hz) e R1 (R4 a R2) b R2 fCLK e H0z2 e gain at C.Z. output as f x 2 R1 R2 R3 eb e a c 1 HOBP R1 R2 a R2 R1 R4 c HOLP eb R2 a R4 R1 0 0 # # fc 0 0 J J # MODE 6b: Single Pole LP Filter (Inverting and NonInverting) (See Figure 15 ) e cutoff frequency of LP outputs fc R2 fCLK R2 fCLK j or R3 100 R3 50 HOLP1 e 1 (non-inverting) R3 HOLP2 e b R2 J TL/H/5066 – 22 FIGURE 13. MODE 5 TL/H/5066 – 23 FIGURE 14. MODE 6a TL/H/5066 – 24 FIGURE 15. MODE 6b 10 2.0 Modes of Operation (Continued) TABLE I. Summary of Modes. Realizable filter types (e.g. low-pass) denoted by asterisks. Unless otherwise noted, gains of various filter outputs are inverting and adjustable by resistor ratios. Mode BP LP 1 * * HP HOLP e a 1 2 * * 3 * * * 3a * * * 4 5 * * 6b HOLP e a 1 b R3 HOLP2 e R2 3 No 2 No 3 Yes (above fCLK/50 or fCLK/100) 4 Yes Universal StateVariable Filter. Best general-purpose mode. 7 Yes As above, but also includes resistortuneable notch. * 3 No Gives Allpass response with HOAP eb1 and HOLP eb2. * 4 Gives flatter allpass response than above if R1 e R2 e 0.02R4. 3 Single pole. 2 Single pole * * * (2) Adjustable fCLK/fo * * 6a Number of resistors AP * (2) HOBP1 e bQ HOBP2 e a 1 1a N * Notes May need input buffer. Poor dynamics for high Q. 3.0 Applications Information From the specifications, the filter parameters are: fo e 200 Hz, HOLP eb2, and, for Butterworth response, Q e 0.707. In section 2.0 are several modes of operation for the MF5, each having different characteristics. Some allow adjustment of fCLK/fo, others produce different combinations of filter types, some are inverting while others are non-inverting, etc. These characteristics are summarized in Table I. To keep the example simple, we will use mode 1, which has notch, bandpass, and lowpass outputs, and inverts the signal polarity. Three external resistors determine the filter’s Q and gain. From the equations accompanying Figure 7 , Q e R3/R2 and the passband gain HOLP e bR2/R1. Since the input signal is driving a summing junction through R1, the input impedance will be equal to R1. Start by choosing a value for R1. 10k is convenient and gives a reasonable input impedance. For HOLP e b2, we have: R2 e bR1HOLP e 10k c 2 e 20k. For Q e 0.707 we have: R3 e R2Q e 20k c 0.707 e 14.14k. Use 15k. For operation on g 5V supplies, V a is connected to a 5V, Vb to b5V, and AGND to ground. The power supplies should be ‘‘clean’’ (regulated supplies are preferred) and 0.1 mF bypass capacitors are recommended. The MF5 is a general-purpose second-order state variable filter whose center frequency is proportional to the frequency of the square wave applied to the clock input (fCLK). By connecting pin 9 to the appropriate DC voltage, the filter center frequency fo can be made equal to either fCLK/100 or fCLK/50. fo can be very accurately set (within g 0.6%) by using a crystal clock oscillator, or can be easily varied over a wide frequency range by adjusting the clock frequency. If desired, the fCLK/fo ratio can be altered by external resistors as in Figures 9, 10, 11, 13, 14 , and 15 . The filter Q and gain are determined by external resistors. All of the five second-order filter types can be built using the MF5. These are illustrated in Figures 1 through 5 along with their transfer functions and some related equations. Figure 6 shows the effect of Q on the shapes of these curves. When filter orders greater than two are desired, two or more MF5s can be cascaded. The MF5 also includes an uncommitted CMOS operational amplifier for additional signal processing applications. 3.1 DESIGN EXAMPLE An example will help illustrate the MF5 design procedure. For the example, we will design a 2nd order Butterworth low-pass filter with a cutoff frequency of 200 Hz, and a passband gain of b2. The circuit will operate from a g 5V power supply, and the clock amplitude will be g 5v (CMOS) levels). 11 3.0 Applications Information (Continued) TL/H/5066 – 25 FIGURE 16. 2nd-Order Butterworth Low-Pass Filter of Design fCLK e 50, Connect Pin 9 to a 5V, and Example. For f0 Change Clock Frequency to 10 kHz. TL/H/5066 – 26 FIGURE 17. Butterworth Low-Pass Circuit of Example, but Designed for Single-Supply Operation 12 3.0 Applications Information (Continued) TL/H/5066–27 (a) Resistive Divider with Decoupling Capaciter TL/H/5066 – 28 (b) Voltage Regulator FIGURE 18. Three Ways of Generating TL/H/5066 – 29 (c) Operational Amplifier with Divider Va for Single-supply Operation 2 these limits. If the MF5 is operating on g 5 volts, for example, the outputs will clip at about 8Vp-p. The maximum input voltage multiplied by the filter gain should therefore be less than 8Vp-p. Note that if the filter has high Q, the gain at the lowpass or highpass outputs will be much greater than the nominal filter gain (Figure 6 ). As an example, a lowpass filter with a Q of 10 will have a 20 dB peak in its amplitude response at fo. If the nominal gain of the filter HOLP is equal to 1, the gain at fo will be 10. The maximum input signal at fo must therefore be less than 800 mVp-p when the circuit is operated on g 5 volt supplies. Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely for a circuit such as the notch in Mode 1 (Figure 7 ). The notch output will be very small at fo, so it might appear safe to apply a large signal to the input. However, the bandpass will have its maximum gain at fo and can clip if overdriven. If one output clips, the performance at the other outputs will be degraded, so avoid overdriving any filter section, even ones whose outputs are not being directly used. Accompanying Figures 7 through 15 are equations labeled ‘‘circuit dynamics’’, which relate the Q and the gains at the various outputs. These should be consulted to determine peak circuit gains and maximum allowable signals for a given application. For a cutoff frequency of 200 Hz, the external clock can be either 10 kHz with pin 9 connected to V a (50:1) or 20 kHz with pin 9 tied to AGND or Vb (100:1). The voltage on the Logic Level Shift pin (7) determines the logic threshold for the clock input. The threshold is approximately 2V higher than the voltage applied to pin 7. Therefore, when pin 7 is grounded, the clock logic threshold will be 2V, making it compatible with 0–5 volt TTL logic levels and g 5 volt CMOS levels. Pin 7 should be connected to a clean, low-impedance (less than 1000X) voltage source. The complete circuit of the design example is shown for a 100:1 clock ratio in Figure 16 . 3.2 SINGLE SUPPLY OPERATION The MF5 can also operate with a single-ended power supply. Figure 17 shows the example filter with a single-ended power supply. V a is again connected to the positive power supply (8 to 14 volts), and Vb is connected to ground. The AGND pin must be tied to V a /2 for single supply operation. This half-supply point should be very ‘‘clean’’, as any noise appearing on it will be treated as an input to the filter. It can be derived from the supply voltage with a pair of resistors and a bypass capacitor (Figure 18a ), or a low-impedance half-supply voltage can be made using a three-terminal voltage regulator or an operational amplifier (Figures 18b and 18c ). The passive resistor divider with a bypass capacitor is sufficient for many applications, provided that the time constant is long enough to reject any power supply noise. It is also important that the half-supply reference present a low impedance to the clock frequency, so at very low clock frequencies the regulator or op-amp approaches may be preferable because they will require smaller capacitors to filter the clock frequency. The main power supply voltage should be clean (preferably regulated) and bypassed with 0.1mF. 3.4 OFFSET VOLTAGE The MF5’s switched capacitor integrators have a higher equivalent input offset voltage than would be found in a typical continuous-time active filter integrator. Figure 19 shows an equivalent circuit of the MF5 from which the output dc offsets can be calculated. Typical values for these offsets are: Vos1 e opamp offset e g 5mV 3.3 DYNAMIC CONSIDERATIONS The maximum signal handling capability of the MF5, like that of any active filter, is limited by the power supply voltages used. The amplifiers in the MF5 are able to swing to within about 1 volt of the supplies, so the input signals must be kept small enough that none of the outputs will exceed b 310mV @ 100:1 Vos2 e b185mV @ 50:1 a 240mV @ 100:1 Vos3 e a 115mV @ 50:1 The dc offset at the BP output is equal to the input offset of the lowpass integrator (Vos3). The offsets at the other outputs depend on the mode of operation and the resistor ratios, as described in the following expressions. 13 3.0 Applications Information (Continued) Mode 1 and Mode 4 Mode 2 and Mode 5 # Ó 1 a 1 a HOLP Q VOS(N) e VOS1 VOS(BP) VOS(LP) e VOS3 e VOS(N) b VOS2 ÓJ V b OS3 Q VOS(N) e # Rp 1 J V R2 OS1 c a VOS2 Mode 1a 1 1 a R2/R4 1 VOS3 b : 1 a R4/R2 Q01 a R2/R4 Rp e R1//R2//R4 VOS(N.INV.BP) e VOS(INV.BP) VOS(LP) a # 1 1a Q J VOS3 VOS1 b Q e VOS3 e VOS(N.INV.BP) b VOS2 VOS(BP) VOS(LP) e VOS3 e VOS(N) b VOS2 Mode 3 VOS(HP) VOS(BP) e VOS2 VOS(LP) e b e VOS3 b # R3 V R2 R4 1 V R2 # R J R4 R2 R2 OS3 a VOS2 a p J a OS1; Rp e R1//R3//R4 TL/H/5066 – 30 FIGURE 19. Block Diagram Showing MF5 Offset Voltage Sources TL/H/5066 – 31 FIGURE 20. Method for Trimming VOS, See Text, Section 3.4 14 3.0 Applications Information (Continued) ing’’, and can be reduced or eliminated by limiting the input signal spectrum to less than fs/2. This may in some cases require the use of a bandwidth-limiting filter ahead of the MF5 to limit the input spectrum. However, since the clock frequency is much higher than the center frequency, this will often not be necessary. Another characteristic of sampled-data circuits is that the output signal changes amplitude once every sampling period, resulting in ‘‘steps’’ in the output voltage which occur at the clock rate. (Figure 21 ) If necessary, these can be ‘‘smoothed’’ with a simple R-C low-pass filter at the MF5 output. The ratio of fCLK to fc (normally either 50:1 or 100:1) will also affect performance. A ratio of 100:1 will reduce any aliasing problems and is usually recommended for wideband input signals. In noise sensitive applications, however, a ratio of 50:1 may be better as it will result in 3 dB lower output noise. The 50:1 ratio also results in lower DC offset voltages, as discussed in 3.4. The accuracy of the fCLK/fo ratio is dependent on the value of Q. This is illustrated in the curves under the heading ‘‘Typical Performance Characteristics’’. As Q is changed, the true value of the ratio changes as well. Unless the Q is low, the error in fCLK/fo will be small. If the error is too large for a specific application, use a mode that allows adjustment of the ratio with external resistors. It should also be noted that the product of Q and fo should be limited to 300 kHz when fo k 5 kHz, and to 200 kHz for fo l 5 kHz. For most applications, the outputs are AC coupled and DC offsets are not bothersome unless large signals are applied to the filter input. However, larger offset voltages will cause clipping to occur at lower ac signal levels, and clipping at any of the outputs will cause gain nonlinearities and will change fo and Q. When operating in Mode 3, offsets can become excessively large if R2 and R4 are used to make fCLK/fo significantly higher than the nominal value, especially if Q is also high. An extreme example is a bandpass filter having unity gain, a Q of 20, and fCLK/fo e 250 with pin 9 tied to Vb (100:1 nominal). R4/R2 will therefore be equal to 6.25 and the offset voltage at the lowpass output will be about a 1.9V. Where necessary, the offset voltage can be adjusted by using the circuit of Figure 20 . This allows adjustment of Vos1, which will have varying effects on the different outputs as described in the above equations. Some outputs cannot be adjusted this way in some modes, however (Vos(BP) in modes 1a and 3, for example). 3.5 SAMPLED DATA SYSTEM CONSIDERATIONS The MF5 is a sampled data filter, and as such, differs in many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the sampling frequency. (The MF5’s sampling frequency is the same as its clock frequency). If a signal with a frequency greater than one-half the sampling frequency is applied to the input of a sampled data system, it will be ‘‘reflected’’ to a frequency less than one-half the sampling frequency. Thus, an input signal whose frequency is fs/2 a 100 Hz will cause the system to respond as though the input frequency was fs/2 - 100 Hz. This phenomenon is known as ‘‘alias- TL/H/5066 – 32 FIGURE 21. The Sampled-Data Output Waveform 15 MF5 Universal Monolithic Switched Capacitor Filter Physical Dimensions inches (millimeters) SO Package Order Number MF5CWM NS Package Number M14B Molded Dual-In-Line Package (N) Order Number MF5CN NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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