ETC 82C499

OPTi
®
82C499
DX System Controller
Data Book
Version 1.0
912-3000-001
August, 1994
Copyright
Copyright © 1994, OPTi Inc. ALL RIGHTS RESERVED.
No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of OPTi Inc.
Disclaimer
The information contained in the manual is provided for the general use of the customers of OPTi Inc. OPTi Inc. makes no
claims or guarantees as to the accuracy of this documentation and assumes no responsibility for any errors. OPTi Inc. reserves
the right to make changes to this documentation and the product described herein without notice or obligation.
In no event will OPTi Inc. be liable for damages, direct or indirect, resulting from any error, defect, or omission in this manual.
Trademarks
OPTi and OPTi Inc. are registered trademarks of OPTi Incorporated.
All other trademarks and copyrights are the property of their respective holders.
OPTi Inc.
2525 Walsh Avenue
Santa Clara, CA 95051
Tel: (408) 980-8178
Fax: (408) 980-8860
BBS: (408) 980-9774
Table of Contents
1.0
2.0
3.0
Features
Overview
Signal Definitions
3.1
4.0
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
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. . . . . . 13
. . . . . . 13
. . . . . . 13
. . . . . . 14
. . . . . . 14
. . . . . . 14
. . . . . . 14
. . . . . . 14
. . . . . . 16
. . . . . . 17
. . . . . . 17
. . . . . . 18
. . . . . . 18
. . . . . . 18
. . . . . . 18
. . . . . . 19
. . . . . . 19
. . . . . . 19
. . . . . . 19
. . . . . . 19
. . . . . . 19
21
I/O Port 60h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I/O Port 64h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Maximum Ratings
6.1
6.2
6.3
6.4
7.0
13
Reset Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . .
CPU Burst Mode Control . . . . . . . . . . . . . . . . . . . . . . . .
Cache Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1 Cache Bank Interleave . . . . . . . . . . . . . . . . . . .
4.4.2 Write-Back Cache . . . . . . . . . . . . . . . . . . . . . . .
4.4.3 Tag RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4 Dirty Bit Mechanism. . . . . . . . . . . . . . . . . . . . . .
Local DRAM Control Subsystem . . . . . . . . . . . . . . . . . .
Parity Generation/Detection Logic . . . . . . . . . . . . . . . . .
Refresh Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shadow RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System ROM BIOS Cycles and Flash EPROM Support
AT Bus State Machine . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Arbitration Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Numeric Coprocessor Cycles (NPX) . . . . . . . . . . . . . . .
Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Bus Conversion/Data Path Control Logic. . . . . . . .
Turbo/Slow Mode Operations . . . . . . . . . . . . . . . . . . . . .
Fast GATEA20 and RESET Emulation. . . . . . . . . . . . . .
Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers Descriptions
5.1
5.2
6.0
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.1 CPU Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.2 AT Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.3 Bus Arbitration Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.4 Numeric Processor Interface Signals . . . . . . . . . . . . . . . . . . . . . 8
3.1.5 Cache Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.6
DRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.7 82C206 Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.8 Buffer Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.9 Reset Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.10 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.11 Miscellaneous Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.12 Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Description
4.1
4.2
4.3
4.4
5.0
1
2
3
29
Absolute Maximum Ratings . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . .
AC Timing Characteristics . . . . . . . . . .
AC Timing Waveforms . . . . . . . . . . . . .
Mechnical Package Outline
......
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.......
.......
.......
.......
......
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......
. . . . . . 29
. . . . . . 29
. . . . . . 30
. . . . . . 33
65
iii
iv
List of Figures
Figure 1-1
Address and Data Path Clock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 3-1
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 6-1
2-1-1-1 Double Bank Cache Read Hit Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 6-2
3-1-1-1 Single Bank Cache Read Hit Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 6-3
Zero-Wait State Write Hit Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 6-4
One-Wait State Cache Write Hit Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 6-5
DMA/ISA Master Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 6-6
One-Wait State DRAM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 6-7
One-Wait State DRAM Page Hit Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 6-8
One-Wait State DRAM Burst Read, RAS# Inactive . . . . . . . . . . . . . . . . . . . . . . 40
Figure 6-9
One-Wait State DRAM Page Miss Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6-10
Zero-Wait State DRAM Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 6-11
One-Wait State DRAM Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 6-12
ISA Bus Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 6-13
Keyboard Controller Access Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 6-14
CPU Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 6-15
Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 6-16
Cache Read Miss Dirty: 2 banks of cache and 0/0 DRAM wait state (1 of 2) . . 48
Figure 6-17
Cache Read Miss Dirty: 2 banks of cache and 0/0 DRAM wait state (2 of 2) . . 49
Figure 6-18
Cache Read Miss Dirty: 1 bank of cache and 0/0 DRAM wait state (1 of 2) . . . 50
Figure 6-19
Cache Read Miss Dirty: 1 bank of cache and 0/0 DRAM wait state (2 of 2) . . . 51
Figure 6-20
Cache Read Miss Dirty: 2 banks of cache and 1/1 DRAM wait state (1 of 2) . . 52
Figure 6-21
Cache Read Miss Dirty: 2 banks of cache and 1/1 DRAM wait state (2 of 2) . . 53
Figure 6-22
Cache Read Miss Dirty: 1 bank of cache and 1/1 DRAM wait state (1 of 2) . . . 54
Figure 6-23
Cache Read Miss Dirty: 1 bank of cache and 1/1 DRAM wait state (2 of 2) . . . 55
Figure 6-24
Cache Read Miss Not Dirty: 2 banks of cache and 0 DRAM read wait state . . . 56
Figure 6-25
Cache Read Miss Not Dirty: 2 banks of cache and 1 DRAM read wait state . . . 57
Figure 6-26
ROM Access Cycle (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 6-27
ROM Access Cycle (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 6-28
DMA Device Read from VESA Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 6-29
DMA Device Write to VESA Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 6-30
ISA Master Read from VESA Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 6-31
ISA Master Write to VESA Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
v
vi
List of Tables
Table 3-1
Numerical Pin Cross-Reference List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3-2
Alphabetical Pin Cross-Reference List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4-1
Address to Tag Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4-2
Cache SRAM Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4-3
SRAM Speed Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4-4
DRAM Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4-5
CPU Address to MA Bus Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5-1
Control Register 1 - Index: 20h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5-2
Control Register 2 - Index: 21h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5-3
Shadow RAM Control Register I - Index: 22h. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5-4
Shadow RAM Control Register II - Index: 23h . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5-5
DRAM Control Register I - Index: 24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 5-6
DRAM Control Register II - Index: 25h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 5-7
Shadow RAM Control Register III - Index: 26h. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5-8
Control Register 3 - Index: 27h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5-9
Non-Cacheable Block 1 Register - Index: 28h . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5-10
Non-Cacheable Block 1 Register II - Index: 29h . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5-11
Non-Cacheable Block 2 Register I - Index: 2Ah . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 5-12
Non-Cacheable Block 2 Register II - Index: 2Bh . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 5-13
ROM Chip Select (ROMCS#) Control Register - Index: 2Dh . . . . . . . . . . . . . . . 26
Table 5-14
I/O Port 61h(Port B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5-15
I/O Port 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5-16
Port 92h - System Controller Port A, PS/2 Compatibility Port . . . . . . . . . . . . . . 27
Table 6-1
82C499 B1 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
vii
viii
OPTi
82C499
®
DX System Controller
1.0
•
•
•
•
•
•
•
•
•
•
Features
Supports Intel® 486 SX/DX/DX2, 487SX, and Intel
386DX/Cyrix® 486DLC/IBM 486DLC microprocessors
Single-chip PC/AT® solution: one 208-pin Plastic
Flat Package (PFP)
1X and 2X clock source, supporting systems running from 16MHz to 50MHz
Write-back direct mapped, bank interleave cache
with size selections: 64KB, 128KB, 256KB, and
512KB
Supports 2-1-1-1, 3-1-1-1, 2-2-2-2, and 3-2-2-2
cache burst cycles
Support for two programmable non-cacheable
regions
Built-in tag auto-invalidation circuitry
Option for write-protected, cacheable video and
system BIOS
Programmable cache and DRAM read/write cycles
Supports four banks of 256KB, 1MB, and 4MB
Figure 1-1
•
•
•
•
•
•
•
•
•
•
•
•
DRAMs for configurations up to 64MB
Shadow RAM option
Flash ROM support
Hidden refresh and slow refresh supported using
the CAS-before-RAS refresh method
Comprehensive VESA VL and OPTi high-performance local bus support
Turbo/slow speed selection
Synchronous AT bus clock with programmable
clock division options:
CLKI(/6, /5 /4, /3), or CLK2I(/6, /5, /4, /3)
Zero or one wait state options for 16-bit AT bus
cycles
Transparent 8042 emulation for fast CPU reset and
GATEA20 generation
Supports the 80387 numeric coprocessor
Low-power, high-speed 0.8-micron CMOS technology
Integrated peripherals controller
Address and Data Path Clock Diagram
Local Bus
Peripherals
FPU
Cache SRAM
CA[18:4]
Control Bus
CPU
Cache
Control
CD[31:0]
Control Bus
CD[31:0]
CD[31:0]
CA[31:2]
CA[31:0]
LA[23:17]
SA[19:0]
CA[23:0]
MA[10:0]
RAS, CAS
DRAM
1-64MB
OPTi
82C499
SA[9:2]
ISA Bus
SD[15:8]
CD[23:16]
BIOS
ROM
Keyboard
Controller
CD[23:16]
SD[7:0]
RTC
XD[7:0]
912-3000-001
SD[7:0]
SD[7:0]
SD[15:0]
Page 1
82C499
2.0
Overview
The OPTi 82C499 provides a highly integrated solution
for fully compatible, high-performance PC/AT platforms. This chip will support the Intel 486SX/DX/DX2/
487SX, Intel 386DX and IBM/Cyrix 486DLC microprocessors in the most cost effective and power efficient
designs available today. Since the device is so critical
to the performance and cost structure of a PC, this
highly integrated approach provides the foundation for
a very cost effective platform without compromising
performance. For power users, this chip offers opti-
mum performance for systems running up to 50MHz.
The OPTi DXSC chip provides a solution positioned to
deliver value, without neglecting quality, compatibility,
or reliability.
The 82C499 integrates a write-back cache controller, a
local DRAM controller, an integrated peripherals controller (82C206), the CPU state machine, the AT bus
state machine, and data buffers all in a single 208-pin
PFP. New on-chip hardware provides the hooks for
OPTi and VESA local bus device support.
OPTi
®
Page 2
912-3000-001
82C499
Signal Definitions
Pin Diagram
SYSTEM CONTROLLER
64
63
62
61
60
59
58
57
56
55
54
53
41
42
43
44
45
46
47
48
49
50
51
52
197
198
199
200
201
202
203
204
205
206
207
208
DX PC/AT
XD14
XD15
VCC
TC
KBDCS#/LGNT#
RTCAS
RTCCS#
SPKD
ROMCS#
0WS#
CHRDY
A20M
DRQ5
DRQ6
OSC
GND
VCC
DRQ7
DACK0
DACK1
DACK2
IRQ1
IRQ43
IRQ6
82C499
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
IRQ75
IRQ8
IRQ9
IRQ1110
IRQ14
IRQ1512
RFSH#
ALE
ATCLK
VCC
XD0
XD1
XD2
XD3
GND
GND
XD4
XD5
XD6
XD7
IORD#
IOWR#
MRD#
MWR#
MCS16#
CLK2
GND
CLK1
IOCS16#
SA0
SA1
SBHE#
XD8
XD9
XD10
XD11
GND
GND
XD12
XD13
CA32S#
CA3
CA2
DRTYW#
TAGWE#
BEOE#
BOOE#
GND
VCC
ECAWE#
OCAWE#
BE0#
BE1#
BE2#
BE3#
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
CAS0#
CAS1#
GND
CAS2#
CAS3#
MA8
MA9
MA10
RAS0#
RAS1#
RAS2#
RAS3#
DWE#
DRQ0
DRQ1
DRQ2
DRQ3
117
116
115
114
113
112
111
110
109
108
107
106
105
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
DRTY
TAG7
TAG6
TAG5
TAG4
TAG3
TAG2
TAG1
TAG0
VCC
A31
DRAMS#/LREQ#
A25
A24
GND
GND
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
GND
A13
A12
A11
A10
A9
A8
A7
A6
A5
GND
GND
A4
A3
Figure 3-1
A2
CPURST
VCC
RDY#
BRDY#/PREQO
ADS#
W/R#
M/IO#
D/C#
ERR#/KEN#
EADS#/NPRST
BLST#/PREQI
3.0
INTR
HLDA
HOLD
RDYI#
LDEV#
TURBO
NMI
VCC
GND
BUSY#/IGERR#
NPERR#
NBUSY#
D31
D30
D29
D28
D27
D26
D25
D24
D15
D14
D13
D12
D11
GND
GND
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MP3
MP2
MP1
MP0
SYSRST#
VCC
GND
P WRGD
CHCK#
HLBOE2#
HLBOE1#
HLBLTH#
XDIR#
LMGCS#/
KBLMCS#
OPTi
®
912-3000-001
Page 3
82C499
Table 3-1
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Numerical Pin Cross-Reference List
Name
IRQ75
IRQ8
IRQ9
IRQ1110
IRQ14
IRQ1512
RFSH#
ALE
ATCLK
VCC
XD0
XD1
XD2
XD3
GND
GND
XD4
XD5
XD6
XD7
IORD#
IOWR#
MRD#
MWR#
MCS16#
CLK2
GND
CLK1
IOCS16#
SA0
SA1
SBHE#
XD8
XD9
XD10
XD11
GND
GND
XD12
XD13
XD14
XD15
VCC
TC
KBDCS#/LGNT#
RTCAS
RTCCS#
SPKD
ROMCS#
0WS#
CHRDY
A20M
Pin
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Name
LMGCS#/KBLMCS#
XDIR#
HLBLTH#
HLBOE1#
HLBOE2#
CHCK#
PWRGD
GND
VCC
SYSRST#
MP0
MP1
MP2
MP3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
GND
GND
D11
D12
D13
D14
D15
D24
D25
D26
D27
D28
D29
D30
D31
NBUSY#
NPERR#
BUSY#/IGERR#
GND
VCC
NMI
TURBO
LDEV#
RDYI#
HOLD
HLDA
INTR
Pin
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Name
BLST#/PREQI
EADS#/NPRST
ERR#/KEN#
D/C#
M/IO#
W/R#
ADS#
BRDY#/PREQO
RDY#
VCC
CPURST
A2
A3
A4
GND
GND
A5
A6
A7
A8
A9
A10
A11
A12
A13
GND
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
GND
GND
A24
A25
DRAMS#/LREQ#
A31
VCC
TAG0
TAG1
TAG2
TAG3
TAG4
TAG5
TAG6
TAG7
DRTY
Pin
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Name
CA32S#
CA3
CA2
DRTYW#
TAGWE#
BEOE#
BOOE#
GND
VCC
ECAWE#
OCAWE#
BE0#
BE1#
BE2#
BE3#
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
CAS0#
CAS1#
GND
CAS2#
CAS3#
MA8
MA9
MA10
RAS0#
RAS1#
RAS2#
RAS3#
DWE#
DRQ0
DRQ1
DRQ2
DRQ3
DRQ5
DRQ6
OSC
GND
VCC
DRQ7
DACK0
DACK1
DACK2
IRQ1
IRQ43
IRQ6
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Page 4
912-3000-001
82C499
Table 3-2
Pin
116
117
118
121
122
123
124
125
126
127
128
129
131
132
133
134
135
136
137
52
138
139
140
143
144
146
111
8
9
168
169
170
171
162
105
163
112
95
159
158
157
180
181
183
184
58
51
28
26
115
67
68
Alphabetical Pin Cross-Reference List
Name
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A20M
A21
A22
A23
A24
A25
A31
ADS#
ALE
ATCLK
BE0#
BE1#
BE2#
BE3#
BEOE#
BLST#/PREQI
BOOE#
BRDY#/PREQO
BUSY#/IGERR#
CA2
CA3
CA32S#
CAS0#
CAS1#
CAS2#
CAS3#
CHCK#
CHRDY
CLK1
CLK2
CPURST
D0
D1
Pin
69
70
71
72
73
74
75
76
77
80
81
82
83
84
85
86
87
88
89
90
91
92
108
203
204
205
145
193
194
195
196
197
198
202
156
160
192
106
166
107
15
16
27
37
38
60
78
79
96
119
120
130
Name
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D24
D25
D26
D27
D28
D29
D30
D31
D/C#
DACK0
DACK1
DACK2
DRAMS#/LREQ#
DRQ0
DRQ1
DRQ2
DRQ3
DRQ5
DRQ6
DRQ7
DRTY
DRTYW#
DWE#
EADS#/NPRST
ECAWE#
ERR#/KEN#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin
141
142
164
182
200
55
56
57
103
102
104
206
2
3
208
5
207
1
4
6
29
21
22
45
100
53
109
172
173
174
175
176
177
178
179
185
186
187
25
63
64
65
66
23
24
93
98
94
167
199
59
188
Name
GND
GND
GND
GND
GND
HLBLTH#
HLBOE1#
HLBOE2#
HLDA
HOLD
INTR
IRQ1
IRQ8
IRQ9
IRQ6
IRQ14
IRQ43
IRQ75
IRQ1110
IRQ1512
IOCS16#
IORD#
IOWR#
KBDCS#/LGNT#
LDEV#
LMGCS#/KBLMCS#
M/IO#
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MCS16#
MP0
MP1
MP2
MP3
MRD#
MWR#
NBUSY#
NMI
NPERR#
OCAWE#
OSC
PWRGD
RAS0#
Pin
189
190
191
113
101
7
49
46
47
30
31
32
48
62
44
99
148
149
150
151
152
153
154
155
161
10
43
61
97
114
147
165
201
110
11
12
13
14
17
18
19
20
33
34
35
36
39
40
41
42
54
50
Name
RAS1#
RAS2#
RAS3#
RDY#
RDYI#
RFSH#
ROMCS#
RTCAS
RTCCS#
SA0
SA1
SBHE#
SPKD
SYSRST#
TC
TURBO
TAG0
TAG1
TAG2
TAG3
TAG4
TAG5
TAG6
TAG7
TAGWE#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W/R#
XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7
XD8
XD9
XD10
XD11
XD12
XD13
XD14
XD15
XDIR#
0WS#
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®
912-3000-001
Page 5
82C499
3.1
Signal Descriptions
3.1.1
CPU Interface Signals
Name
Pin
Type
BLST#/PREQI
105
I
BRDY#/
PREQO
112
O
8mA
Burst Ready: An output for the CPU to sample the read data during
burst cycles. This pin becomes PREQO for the Intel 386DX and IBM/
Cyrix 486DLC Mode of operation.
BE[3:0]#
171:168
I/O
4mA
Byte Enables 3 through 0: These signals are inputs during CPU
cycles and are outputs during non-CPU cycles.
A31, A[25:24]
156,
144:143
I
A[23:17]
140-134
I/O
4mA
CPU Address Lines 23 through 17: These signals are inputs during
CPU, refresh and Master cycles. They become outputs during DMA
cycles.
A[16:8]
133:131,
129:124
I/O
4mA
CPU Address Lines 16 through 8:These signals are inputs during
non-DMA cycles. A[16:9] become outputs which convey DMA
address lines A[16:9] by latching XD[7:0] during 16-bit DMA cycles.
A[15:8] convey DMA address lines A[15:8] by latching XD[7:0] during
8-bit DMA cycles.
A[7:2]
123:121,
118:116
I/O
4mA
CPU Address Lines 7 through 2: These signals become outputs
during DMA cycles.
80:92,
67:77
I/O
4mA
CPU Data Bus bits 31 through 24 and 15 through 0.
D/C#
108
I
M/IO#
109
I/O
8mA
CPU Memory or I/O Cycle Status: When high, this signal indicates a
memory cycl. When low, it indicates an I/O cycle. M/IO# becomes an
output during DMA/master cycles for local device accesses and IBM
486DLC snooping cycles.
W/R#
110
I/O
8mA
CPU Write or Read Cycle Status: This signal indicates a write cycle
if high and read cycle if low. It becomes an output during DMA/master
cycles for local device accesses and IBM 486DLC snooping cycles.
A20M#
52
O
4mA
Emulation of GateA20 OR'ed with internal fast GATEA20 output to
Intel 486, IBM/Cyrix 486DLC CPU. This signal must remain high
during the power-up CPU reset period. In Intel 386DX Mode, this is
the GA20 signal indirectly buffered to the AT bus line LA20.
LDEV#
100
I
Local Bus Device Cycle Indication: This signal is sampled at the
end of the first T2, or at the end of the second T2 at 50MHz.
DRAMS#/
LREQ#
145
I
A[30:25] are low decode, connected to A26 normally, except during
local bus master support, when MP1 is sampled low by RST4’s rising
edge, this signal becomes LREQ# (Local Bus Master Request).
D[31:24],
D[15:0]
IOL
Description
486 Burst Last Cycle Indication: The 82C499 terminates the burst
cycle as long as BLST# sampled low at the end of each T2 when
BRDY# is active. During Intel 386DX and IBM/Cyrix 486DLC Mode,
this is the PREQI signal from the 387.
CPU Address Lines 31, 25, and 24.
CPU Data or Code Cycle Status: When high, this signal indicates
data transfer operations. When low, it indicates control operations
(code fetch, halt, etc.).
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82C499
3.1.1
CPU Interface Signals (cont.)
Name
Pin
Type
RDYI#
101
I
RDY#
113
I/O
8mA
Ready Output for the CPU to terminate the current cycle. This pin
becomes an input during local device cycles if a tristated local bus
device's ready was connected.
ADS#
111
I/O
8mA
Address Strobe: A status input from CPU. This active low signal
indicates the CPU is starting a new cycle. It becomes an output pin
during DMA/master cycles for local device accesses and IBM
486DLC snooping cycles.
TURBO
99
I
3.1.2
IOL
Description
Local Device Ready Input: This signal is synchronized by the
82C499 before sending it to CPU.
Turbo Mode Selection: If the TURBO pin is tied low, the CPU will be
forced idle for 2/3 period.
AT Bus Interface
Name
Pin
Type
IOL
Description
MCS16#
25
I/O
18mA
IOCS16#
29
I
ALE
8
O
18mA
AT Bus Address Latch Enable: Represents that an AT cycle has
started.
SBHE#
32
I/O
18mA
AT Bus High Byte Enable: This signal is an input pin during master
cycles.
XD[15:0]
42:39,
36:33,
20:17,
14:11
I/O
18mA
AT Data Bus lines.
IORD#
21
I/O
24mA
AT I/O Read Command: This pin is an input during master cycles
and an output for CPU and DMA cycles.
IOWR#
22
I/O
24mA
AT I/O Write Command: This pin is an input during master cycles
and an output for CPU and DMA cycles.
MRD#
23
I/O
18mA
AT Memory Read Command: This pin is an input during master
cycles and an output for CPU and DMA cycles.
MWR#
24
I/O
18mA
AT Memory Write Command: This pin is an input during master
cycles and an output for CPU and DMA cycles.
ROMCS#
49
O
4mA
BIOS ROM Output Enable: System BIOS ROM accesses could be
either 8- or 16-bit. This signal will be asserted from the end of the first
T2 to the end of the last T2.
CHRDY
51
I/O
18mA
Channel Ready: This pin is a Schmitt-trigger input from the AT bus.
LMGCS#/
KBLMCS#
53
O
4mA
Lower Memory Space (below one megabyte) Indicator: This
signal is active during refresh cycles. When MP1 is sampled low, this
pin becomes KBLMCS# only during I/O cycles. This pin must be
qualified with M/IO# before it goes to the 8042 chip select.
16-bit AT Memory Slave Cycle Status: This pin is a Schmitt-trigger
input pin normally and is driven low during master cycle.
16-bit I/O Slave Cycle Status: This is a Schmitt trigger input pin.
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Page 7
82C499
3.1.2
AT Bus Interface (cont.)
Name
Pin
Type
IOL
SA0
30
I/O
24mA
System Address Line 0: This pin is an input during master cycles;
an output during CPU, DMA, or refresh cycles.
SA1
31
I/O
24mA
System Address Line 1: This pin is an input during master cycles
and output during CPU, DMA, or refresh cycles.
0WS#
50
I
3.1.3
Zero Wait State: This pin is a Schmitt-trigger input pin from the AT
bus. Note that the system BIOS ROM is accessed as a one wait state
AT cycle.
Bus Arbitration Interface Signals
Name
Pin
Type
IOL
RFSH#
7
I/O
18mA
HLDA
103
I
HOLD
102
O
3.1.4
Description
AT Refresh Cycle Indication: This signal is an input pin master or
DMA cycles. Note that the 82C499 will not HOLD the CPU during AT
refresh cycles. The 82C499 puts the CPU on "waiting" if an AT
refresh cycle is underway.
Hold Acknowledge from CPU.
4mA
HOLD Request to CPU: Hidden refresh will not hold the CPU.
Numeric Processor Interface Signals
Name
Pin
Type
NPBUSY#
93
I
EADS#/
NPRST
106
O
NPERR#
94
I
BUSY#/
IGERR#
95
O
3.1.5
Description
IOL
Description
Numeric Processor Busy: also used to determine Intel 386, IBM/
Cyrix 486DLC, or Intel 486 Mode. A high indicates an Intel 386 or
IBM/Cyrix 486 DLC. A low indicates an Intel 486.
4mA
486 Address Snooping Strobe: This signal is asserted for two Tstates during DMA or master cycles. In the Intel 386DX or IBM/Cyrix
486DLC Mode, a reset of the numeric coprocessor can be generated
by an I/O write to Port F1h, which will trigger NPRST.
Numeric Processor Error Indication: Used to generate IGERR# for
the Intel 486 CPU. Also, it generates NPINT for AT/PC-compatability
and will generate BUSY# for the Intel 386 or IBM/Cyrix 486DLC.
4mA
Busy or Ignore Error: This is a normally high signal and will become
low as soon as the NPERR# is asserted. An I/O write to Port F0h, or a
CPU reset will force this signal back to high. During the Intel 386DX
or IBM/Cyrix486DLC Mode, this signal is the BUSY# signal to the
CPU.
Cache Interface Signals
Name
Pin
Type
IOL
ERR#/KEN#
107
O
4mA
Description
Error/Cache Enable: Cacheable or non-cacheable status for the
internal cache of Intel 486 and IBM/Cyrix 486DLC. This signal is low
normally and is brought high at the end of T1. The 82C499 asserts
KEN# again if it is a cacheable cycle. During the Intel 386 Mode, this
pin is ERR# to the CPU. ERR# for the IBM/Cyrix 486DLC needs to be
generated externally.
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Page 8
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82C499
3.1.5
Cache Interface Signals (cont.)
Name
Pin
Type
IOL
158:159
O
8mA
CPU Address Lines 3 and 2.
DRTY
156
I/O
4mA
Dirty bit of tag RAM to indicate its line has been written into.
CA32S#
157
O
4mA
External Cache Address line 3 and line 2 Select.
BEOE#
162
O
8mA
External Cache Output Enable.
BOOE#
163
O
8mA
External Cache Output Enable.
ECAWE#
166
O
8mA
External Cache Write Enable for the even Cache bank.
OCAWE#
167
O
8mA
External Cache Write Enable for the odd Cache bank.
TAG[7:0]
155:148
I/O
4mA
Tag RAM Output lines 7 through 0.
TAGWE#
161
O
4mA
Tag RAM Write Enable: Used to update the tag RAM.
DRTYW#
160
O
8mA
Write Strobe to Dirty bit of tag RAM.
CA[3:2]
3.1.6
Description
DRAM Interface Signals
Name
Pin
Type
IOL
184, 183,
181, 180
O
8mA
DRAM Column Address Strobe bits 3 through 0.
66-63
I/O
4mA
DRAM Parity bits 3 through 0: In addition, MP1 is used to enable the
internal VESA bus arbitration circuitry. This pin must be pulled down
with a 1K resistor if the internal VESA bus arbitration is to be used.
MP2 is used to determine the Intel 386 or IBM/Cyrix 486DLC. This pin
must be pulled down with a 1K resistor if the IBM/Cyrix 486DLC is
used. MP1 and MP2 are sampled on the rising edge of RST4.
RAS[3:0]#
188:191
O
8mA
DRAM Row Address Strobe bits 3 through 0.
MA[10:0]
187:185,
179:172
O
8mA
DRAM Row/Column Address lines 10 through 0.
192
O
8mA
DRAM Write Enable signal.
Pin
Type
IOL
DRQ[7:0]
202,
198:193
I
DACK[2:0]
205:203
O
5mA
Encoded DMA Acknowledgement lines 2 through 0.
INTR
104
O
4mA
Interrupt Request
IRQ1
206
I
Interrupt Request line 1: Schmitt-trigger input.
IRQ43
207
I
Interrupt Request lines 4 and 3: Schmitt-trigger input.
IRQ6
208
I
Interrupt Request line 6: Schmitt-trigger input.
IRQ75
1
I
Interrupt Request lines 7 and 5: Schmitt-trigger input.
CAS[3:0]#
MP[3:0]
DWE#
3.1.7
Description
82C206 Signal
Name
Description
DMA request lines
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®
912-3000-001
Page 9
82C499
3.1.7
82C206 Signal (cont.)
Name
Pin
Type
IRQ8
2
I
Interrupt Request line 8: Schmitt-trigger input.
IRQ9
3
I
Interrupt Request line 9: Schmitt-trigger input.
IRQ1110
4
I
Interrupt Request lines 11 and 10: Schmitt-trigger input.
IRQ14
5
I
Interrupt Request line 14: Schmitt-trigger input.
IRQ1512
6
I
Interrupt Request lines 15 and 12: Schmitt-trigger input.
TC
44
O
12mA
3.1.8
IOL
Description
Terminate Count.
Buffer Control Signals
Name
Pin
Type
IOL
HLBOE1#
56
O
4mA
Description
Byte 2 Data Buffer Output Enable: This signal becomes active
when:
CPU DRAM cycles for parity checking and generation,
CPU AT byte 2 write cycle at 486 Mode,
DMA or master byte 2 read DRAM or,
Local device cycle.
HLBLTH#
55
O
4mA
Byte 2 Data Latch Enable: This signal becomes high when:
CPU AT byte 2 read cycle,
DMA or master cycle.
HLBOE2#
57
O
4mA
Byte 2 Data Latch Output Enable: This signal becomes active
when:
CPU AT byte 2 read cycle
DMA or master byte 2 write to local DRAM or local device.
XDIR#
3.1.9
54
O
4mA
SD[7:0] to XD[7:0] Direction Control: This signal is normally high
and is driven low when the devices located on XD[7:0] are read.
Reset Signals
Name
Pin
Type
IOL
Description
CPURST
115
O
8mA
CPU Reset for the microprocessor.
SYSRST#
62
O
8mA
Debounced PWRGD# output.
PWRGD
59
I
Power good status or reset switch on indication.
3.1.10 Clock Signals
Name
Pin
Type
OSC
199
I
IOL
Description
14.3MHz Oscillator input.
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Page 10
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82C499
3.1.10 Clock Signals (cont.)
Name
Pin
Type
IOL
Description
ATCLK
9
O
18mA
CLK2
26
I
Clock Input which has a frequency equal to twice the rated CPU
clock if the 2X-clock scheme is chosen. This signal is used for
secondary cache early write option only. If the 1X clock scheme is
used, this pin is connected to the same clock source as CLKI.
CLK1
28
I
Single phase clock input for the 82C499 internal state machine.
ATCLK to AT bus. This is a free running clock output. It could be
CLKI/3, CLKI/4, CLKI/5 or CLKI/6 ( indicates that 82C499 is running
at 50MHz and LDEV# will be sampled at the end of second T2 clock
cycle).
3.1.11 Miscellaneous Interface Signals
Name
Pin
Type
IOL
Description
CHCK#
58
O
KBDCS#/
LGNT#
45
O
4mA
Keyboard Controller Chip Select or Local Grant: When I/O to Port
60h or 64h is detected, this signal is decoded for the keyboard A[9:0].
When MP1 is pulled low, this signal becomes the VESA bus local
grant signal.
NMI
98
O
4mA
Non-Maskable Interrupt: Sent to the CPU and caused by system
parity error or AT bus channel check.
RTCAS
46
O
4mA
Real-time Clock Address Strobe.
RTCCS#
47
O
4mA
Real-time Clock Chip Select.
SPKD
48
O
4mA
Speaker Data Output: Generated by OUT2 and Port 61h, bit 1.
Channel Check: An input from the AT bus to indicate that a parity
error was generated by the AT memory card. (NMI interrupt request.)
3.1.12 Power and Ground Pins
Name
Pin
Type
IOL
Description
VCC
10, 43, 61,
97, 114,
147, 165,
201
PWR
Power Connection: +5V
GND
15, 16, 27,
37, 38, 60,
78, 79, 96,
119, 120,
130, 141,
142, 164,
182, 200
GND
Ground Connection
OPTi
®
912-3000-001
Page 11
82C499
OPTi
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Page 12
912-3000-001
82C499
4.0
Functional Description
4.1
Reset Logic
The RST1# input to the 82C499 is used to generate the
CPU reset (CPURST), the numeric coprocessor reset
(NPRST), and the system reset (SYSRST#) signals.
RST1# is a “cold reset” which is generated when either
PWRGD goes low (from the power supply, indicating a
low power condition) or when the system reset button
is activated. This reset signal is used to force the system to begin execution at a known state. When RST1#
is sensed active, the 82C499 will assert CPURST,
NPRST, and SYSRST#. CPURST is also generated
when a shutdown condition is decoded from the CPU
bus definition signals. CPURST, NPRST, and
SYSRST# are asserted for (128) CLK2 cycles.
CLK is a master single-phase clock which is used to
drive all host CPU synchronous signals and the
82C499's internal state machines. CLK2 is used by the
cache/DRAM controller logic and to maintain the clock
phase between the CPU and the 82C499 by controlling
the CPU reset timing.
The 82C499 generates the AT bus clock (ATCLK) from
an internal division of CLK or CLK2. The ATCLK frequency is programmable and can be set to any of four
clock division options by programming Index Register
25h[1:0]. This allows the system designer to tailor the
AT bus clock frequency to support a wide range of system designs and performance platforms.
A 2X clock is necessary for running the system with
zero-wait-state-cache-write enabled and to conform to
the timing requirements specified by t100a and t100b.
The 82C499 emulates the keyboard reset function. The
keyboard reset is intercepted by monitoring the I/O
write cycle “FE” command to Port 64h. This fast CPU
reset from the chipset will be generated directly after
the I/O write is decoded unless bit 1 of Index Register
20h is disabled, in which case the reset will not start
until a “halt” instruction is executed.
At 40MHz, Intel 386 or IBM 486DLC applications CLKI,
CLK2I, and CPUCLK must be within 1ns clock skew of
each other. This is required for the proper setup of hold
time to be met for the CPU and proper synchronization
of CLKI to the system.
When configured to interface with a math coprocessor,
the 82C499 will generate the NPRST signal when
CPURST is activated or if an I/O write to Port F1h is
issued.
The DXSC chipset fully supports 486 burst cycles. The
82C499 cache and DRAM controllers insure that data
is burst into the CPU whenever the 486 requests a
burst linefill. The secondary cache provides data on
read-hits and the DRAM supplies the data during
cache read-misses.
4.2
System Clock Generation
The 82C499 has two high frequency clock inputs, CLK
and CLK2. This clocking scheme provides both single
and double frequency operation to support all 486 platforms at system speeds up to 50MHz.
The 486 is driven by a 1X clock as opposed to the 2X
clock required by the 486DLC and 386 microprocessor.
Single frequency clocking is only necessary during 486
40MHz and 50MHz operation. In this mode, CLK and
CLK2 are generated by the same source so that the
82C499 will receive only a single 1X clock source (this
avoids the necessity of a 100MHz oscillator for 486
50MHz operation). Double frequency operation
requires that the CLK2 input be fed directly by the crystal oscillator, while the CLK input is derived from the
oscillator output divided by two externally. In this mode,
the 82C499 will receive both a 1X and 2X clock source.
Typically for Intel 486 CPUs, a double frequency clock
is recommended for 20, 25, and 33MHz operation,
while 40 or 50MHz operation requires a single frequency clocking scheme.
4.3
CPU Burst Mode Control
For the cache read-hit cycle, BRDY# is asserted at the
middle of the first T2 state when a 2-1-1-1 (zero wait
state) cache burst cycle is chosen, otherwise it is
asserted at the middle of the second T2 state when
one wait state is required. If a read-miss occurs, the
DRAM data is first written into cache memory, then it is
burst from the cache to the 486 CPU. BRDY# is
asserted after cache memory is updated for cache
read-misses. Once asserted, BRDY# stays active until
BLST# is detected during a zero wait state burst cycle.
BRDY# is never active during DMA or master cycles.
The 82C499 contains separate burst counters to support DRAM and external cache burst cycles. The
DRAM burst counter performs the cache read-miss linefill (DRAM to external cache) and the cache burst
counter supports the 486 burst linefill (external cache
to the 486 CPU). The burst order of the cache burst
counter exactly matches the double-word address
sequencing expected by the 486 CPU. The DRAM
burst counter is used for cache read-miss cycles and
dirty linefill write operations.
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4.4
Cache Subsystem
The integrated cache controller, which uses a directmapped, bank-interleaved scheme dramatically
boosts the overall performance of the local memory
subsystem by caching writes as well as reads (writeback mode). Cache memory can be configured as one
or two banks, and sizes of 64, 128, 256, and 512KB
are supported. Provisions for two programmable noncacheable regions are provided. The cache controller
operates in non-pipeline mode, with a fixed 16-byte line
size (optimized to match a 486 burst linefill) in order to
simplify the motherboard design without increasing
cost or degrading system performance. For 486 systems, the secondary cache operates independently
and in addition to the CPU's internal cache.
The cache controller works as the front-end for both
the DRAM and AT bus controllers. ADS# from the CPU
must pass through the cache logic first. When the
cache is disabled, ADS# just falls through the cache
controller and delivers an internal MADS# to the DRAM
and AT bus controllers. When the cache is enabled,
ADS# is blocked when a cache cycle is detected. If this
cycle is determined to be a NCA (non-cacheable
address) or a cache miss cycle, ADS# is delayed one
CLK before outputting an internal MADS# due to the
time needed for NCA and cache hit/miss detections.
4.4.1 Cache Bank Interleave
In order to support cache burst cycles at elevated frequencies and still utilize conventional speed SRAMs, a
bank interleave cache access method is employed.
The addresses are applied to the cache memory one
cycle earlier, while cache output enable signals control
even/odd bank selection and enable cache RAM data
to the CPU data bus. Since the output enable time is
about one-half of the address access time, the 82C499
can achieve a high performance cache burst mode
without using the more expensive high speed SRAMs.
The 82C499 supports one or two cache banks. Two
cache banks are required to interleave and realize the
performance advantages of this cache scheme. Cache
sizes of 128KB and 512KB are single-bank caches,
while 64KB and 256KB cache sizes are double-bank.
When using a double-bank configuration, the even and
odd banks receive the same address lines. Signals
A2/A3, ECAWE#/OCAWE#, and BEOE#/BOOE# are
used to dictate the even or odd bank access.
4.4.2 Write-Back Cache
The write-back cache scheme derives its superior performance by optimizing write cycles. There is no performance penalty in the cache write cycle, since the
cache controller does not need to wait for the much
slower DRAM controller to finish its cycle before proceeding to the next cycle.
4.4.3 Tag RAM
A built-in tag comparator improves system performance while reducing component count on the system
board. The comparator internally detects the cache hit/
miss status by comparing the high-order address bits
(for the memory cycle in progress) with the stored tag
bits from previous cache entries (see Table 4-1).
When a match is detected, and the location is cacheable, a cache hit cycle takes place. If the comparator
does not match, or a non-cacheable location is
accessed (based on the internal non-cacheable region
registers), the current cycle is a cache miss. The tag is
invalidated automatically during memory reads when
the cache is disabled; each memory read will write into
the corresponding tag location a non-cacheable
address (such as A0000 or B0000 of the video memory
area). To invalidate the cache, simply disable the
cache in Configuration Register 21h, bit 4, and read a
block of memory equal to the size of the cache. The
advantage of this invalidation scheme is that no valid
bit is necessary and expensive SRAM can be conserved. To flush the cache, simply read a block twice
the size of the cache. This will guarantee that every
dirty cache location is flushed to DRAM.
The following table details which CPU address bits are
stored as tags for the various cache sizes supported in
the 82C499 and how the tag RAM bits are addressed
for different cache sizes.
Table 4-1
Address to Tag Bit Mapping
Tag Bit
64KB
128KB
256KB
512KB
7
A22
A22
A22
A22
6
A21
A21
A21
A21
5
A20
A20
A20
A20
4
A19
A19
A19
A19
3
A18
A18
A18
X
2
A17
A17
A25
A25
1
A16
A24
A24
A24
0
A23
A23
A23
A23
4.4.4 Dirty Bit Mechanism
The “dirty bit” is a mechanism for monitoring coherency
between the cache system and DRAM. Each tag entry
has a corresponding dirty bit to indicate whether the
data in the represented cache line has been modified
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since it was loaded from system memory. This allows
the 82C499 to determine whether the data in memory
is “stale” and needs to be updated before a new memory location is allowed to overwrite the currently
indexed cache entry. The write-back cycle causes an
entire cache line (16 bytes) to be written back to memory, followed by a line burst from the new memory location into the cache, and then the final line burst from
the cache to the CPU. Normally, the performance
advantage of completing fast writes to the cache outweigh the “write-back” read-miss penalties which are
incurred while operating the write-back scheme.
Cache Read-Hit
The secondary cache provides data to the CPU. For
486 systems, the 82C499 follows the CPU's burst protocol to fill the processor's internal cache line.
Cache Read-Miss (DIRTY bit negated)
The cache controller does not need to update the system memory with the cache's current data because that
data has not been modified (evidenced by the dirty bit
negation). The cache controller asserts TAGWE#
causing the tag RAMs to update with the new address,
and asserts ECAWE#/OCAWE# causing the cache
memory to update with data from DRAM. This data is
then presented to the CPU (following burst protocol for
486 systems).
Table 4-2
Cache Read-Miss (DIRTY Bit Asserted)
The cache controller must update the system memory
with data from the cache location that is going to be
overwritten. The controller writes the 16-byte line from
cache memory into DRAM, then reads the new line
from DRAM into the cache memory and deasserts the
DIRTY bit. The cache controller asserts TAGWE#,
ECAWE#/OCAWE#, and DRTYW# during this linefill.
This new data is presented to the CPU (following burst
protocol for 486 systems).
Cache Write-Hit
Because this is a write-back cache, the cache controller does not need to update the much slower DRAM
memory. Instead, the controller updates the cache
memory and sets the DIRTY bit. DIRTY may already
be set, but that does not affect this cycle. The contents
of the tag RAM remains unmodified.
Cache Write-Miss
The cache controller bypasses the cache entirely and
writes the data directly into DRAM.
DIRTY is
unchanged.
Table 4-2 shows the cache sizes supported by the
82C499, with the corresponding tag RAM address bits,
tag RAM size, cache RAM address bits, cache RAM
size, and cacheable main memory size.
Cache SRAM Requirements
Cache Size
TAG Field Address /
TAG RAM Size
Dirty SRAMs
Size
Cache SRAM Address Qty
/ Cache RAM Size
Cacheable Main
Memory
64KB
A[23:16] / 8Kx8
16Kx1
A[15:2] / 8ea, 8Kx8
16MB
128KB
A[24:17] / 8Kx8
16Kx1
A[16:2] / 4ea, 32Kx8
32MB
256KB
A[25:18] / 32Kx8
16Kx1
A[17:2] / 8ea, 32Kx8
64MB
512KB
A[25:19] / 32Kx8
64Kx1
A[18:2] / 4ea, 128Kx8
64MB
Table 4-3 shows what speed SRAM and TAG SRAM to use for a particular CPU clock rate.
Table 4-3
SRAM Speed Requirements
Note*
Speed
OSC
Cache SRAM
Tag SRAM
DRAM speed
16MHz
32MHz
25ns
25ns
80ns
Cache Write 0ws, Cache read burst 2-1-1-1
20MHz
40MHz
25ns
25ns
80ns
Cache Write 0ws, Cache read burst 2-1-1-1
25MHz
50MHz
25ns
25ns
80ns
Cache Write 0ws, Cache read burst 2-1-1-1
33MHz
66/33MHz
20ns
15ns
80ns
Cache Write 0ws, Cache read burst 2-2-2-2
1 bank of cache
33MHz
66/33MHz
20ns
15ns
80ns
Cache Write 0ws, Cache read burst 2-1-1-1
2 banks of cache
40MHz
80MHz
20ns
15ns
80ns
Cache Write 1ws, Cache read burst 3-2-2-2
50MHz
50MHz
20ns
15ns
80ns
Cache Write 1ws, Cache read burst 3-2-2-2
*.
For the Intel 386 or IBM/Cyrix 486DLC, only the lead-off cycles of the above corresponding cache read burst cycles
will be used (i.e., 33MHz and below: 2).
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Note
DRAM and cache cycles are at their minimum
wait states.
4.5
Local DRAM Control Subsystem
The 82C499 supports up to four banks of page-mode
local DRAM memory for configurations of up to 64MB.
256KB, 1MB, or 4MB page-mode DRAM devices may
be used. The DRAM configuration is programmable
Table 4-4
through Configuration Register 24h. DRAM performance features are programmable through Configuration Register 25h. Table 4-4 illustrates the DRAM
configurations supported.
Table 4-5 describes how the DRAM address lines are
multiplexed when different memory device types are
used.
DRAM Configurations
Bank0
Bank1
Bank2
Bank3
Total
Register Bits
[7:4] - [2:0]
256KB
x
x
x
1MB
0000-111
256KB
256KB
x
x
2MB
0001-111
1MB
x
x
x
4MB
1000-111
256KB
1MB
x
x
5MB
0010-111
1MB
1MB
x
x
8MB
1001-111
1MB
1MB
1MB
x
12MB
1001-000
256KB
1MB
1MB
1MB
13MB
0010-001
1MB
1MB
1MB
1MB
16MB
1001-001
4MB
x
x
x
16MB
1100-111
256KB
256KB
4MB
x
18MB
0001-100
1MB
4MB
x
x
20MB
1010-111
4MB
1MB
x
x
20MB
1011-111
1MB
1MB
4MB
1MB
28MB
1001-011
1MB
4MB
1MB
1MB
28MB
1010-001
4MB
1MB
1MB
1MB
28MB
1011-001
4MB
4MB
x
x
32MB
1101-111
1MB
1MB
4MB
4MB
40MB
1001-101
1MB
4MB
4MB
1MB
40MB
1010-011
4MB
1MB
4MB
1MB
40MB
1011-011
4MB
4MB
1MB
1MB
40MB
1101-001
4MB
4MB
4MB
x
48MB
1101-100
1MB
4MB
4MB
4MB
52MB
1010-101
4MB
1MB
4MB
4MB
52MB
1011-101
4MB
4MB
4MB
1MB
52MB
1101-011
4MB
4MB
4MB
4MB
64MB
1101-101
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Table 4-5
CPU Address to MA Bus Mapping
256KB
4.6
1MB
Column
Row
Column
Row
Column
Row
MA0
A2
A11
A2
A21
A2
A21
MA1
A3
A12
A3
A12
A3
A23
MA2
A4
A13
A4
A13
A4
A13
MA3
A5
A14
A5
A14
A5
A14
MA4
A6
A15
A6
A15
A6
A15
MA5
A7
A16
A7
A16
A7
A16
MA6
A8
A17
A8
A17
A8
A17
MA7
A9
A18
A9
A18
A9
A18
MA8
A10
A19
A10
A19
A10
A19
MA9
X
X
A11
A20
A11
A20
MA10
X
X
X
X
A12
A22
Parity Generation/Detection Logic
During local DRAM write cycles, the 82C499 generates
a parity bit for each byte of write data from the processor. Parity bits are stored into local DRAM along with
each data byte. During a DRAM read, the parity bit is
checked for each data byte. If the logic detects incorrect parity, the 82C499 will generate NMI to the CPU.
The parity error will invoke the NMI, providing that the
parity check is enabled in the Configuration Register
21h, bit 5. Parity check must also be enabled in the
Port B (61h) register, bits [2:3].
4.7
4MB
Memory
Address
Refresh Logic
The 82C499 supports both normal and hidden refresh.
Normal refresh refers to the classical refresh implementation which places the CPU on “hold” while a
refresh cycle takes place to both the local DRAM and
any AT bus memory. This is the default condition at
power-up. However, hidden refresh is performed independent of the CPU and does not suffer from the performance restriction of losing processor bandwidth by
forcing the CPU into its hold state. Hidden refresh
delivers higher system performance and is recommended over normal refresh. As long as the CPU does
not try to access local memory or the AT bus during a
hidden refresh cycle, refresh will be transparent to the
CPU. The CPU can continue to execute from its internal and secondary caches as well as execute internal
instructions during hidden refresh without any loss in
performance due to refresh arbitration. If a local memory or AT bus access is required during hidden refresh,
wait states will be added to the CPU cycle until the
resource becomes available. Hidden refresh also separates refreshing of the AT bus and local DRAM. The
DRAM controller arbitrates between CPU DRAM
accesses and DRAM refresh cycles, while the AT bus
controller arbitrates between CPU accesses to the AT
bus, DMA, and AT refresh. The AT bus controller
asserts the RFSH# and MEMR# commands and outputs the refresh address during AT bus refresh cycles.
The 82C499 implements refresh cycles to the local
DRAM using CAS-before-RAS timing. CAS-beforeRAS refresh has lower power consumption than RASonly refresh, which is important when dealing with large
memory arrays. CAS-before-RAS refresh is used for
both normal and hidden refresh to local memory.
The output of internal counter 1/timer 1 (OUT1) inside
the 82C499 is programmed as a rate generator to produce the periodic refresh request signal which occurs
every 15.9µs. Requests for refresh cycles are generated by two sources: counter1/timer1, or 16-bit ISA
masters that activate refresh when they have bus ownership. These ISA masters supply refresh cycles
because the refresh controller cannot preempt the bus
master to perform the necessary refresh cycles. 16-bit
ISA masters that hold the bus longer than 15µs must
supply refresh cycles.
By programming Configuration Register 25h, bit 1,
slow refresh is enabled which will further divide the
15.9µs period by four to provide a 63.6µs “slow refresh”
interval (slow refresh DRAMs must be used with the
slow refresh feature).
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4.8
Shadow RAM
Since accesses to local DRAM are much faster than
those to EPROM, the 82C499 provides shadow RAM
capability. With this feature, code from slow devices
like ROM and EPROM memories can be copied to
local DRAM to speed up memory accesses. Accesses
to the specified EPROM space are redirected to the
corresponding DRAM location.
Shadow RAM
addresses range from C0000h-FFFFFh. 16KB granularity is provided for the address range C0000hEFFFFh, while the 64KB range from F0000h-FFFFFh
(the location of system BIOS) can be shadowed as an
entire segment.
The shadow RAM control is setup in the configuration
registers. First, the ROM contents must be copied into
the shadow RAM area. Next, the shadow RAM enable
bit is set in the configuration register. For the system
BIOS area, once the bit is set, the RAM area becomes
read-only. For the video and adapter BIOS area, the
user can select read-only or read/write by setting the
write protect bit in Index Register 26h accordingly.
Video BIOS at the C0000h-C8000h area can be shadowed and cached if bit 4 of Register 27h is set to 1.
System BIOS at F0000-FFFFF can also be shadowed
if Register 22h bit 7 is set to 1. The system BIOS at
F0000-FFFFF is non-cacheable.
4.9
System ROM BIOS Cycles and Flash
EPROM Support
The 82C499 supports both 8- and 16-bit EPROM
cycles. If the system BIOS is 16 bits wide, ROMCS#
should be connected to M16# through an open collector gate indicating to the 82C499 that a 16-bit EPROM
is responding. The system BIOS resides on the XD
bus. The XD to SD data buffer is normally disabled
(XDIR# inactive) except during I/O read cycles at
addresses below 100h (byte-wide I/O), INTA cycles,
and 8-bit ROM BIOS cycles.
ROMCS# is generated for the both the E0000-EFFFFh
and F0000-FFFFFh segments. If a combined video/
system ROM BIOS is desired, these two segments
should be used.
For flash EPROM support, Register 26h, bit 7, can be
set to 1 to enable write cycles for ROMCS# to support
flash EPROMs.
The desired segment must be
selected via register 2Dh. Memory shadowing and
caching should be disabled prior to making write
accesses to the flash EPROM.
4.10
AT Bus State Machine
The AT bus state machine gains control when the
82C499's decoding logic detects a non-local memory
cycle. It monitors status signals M16#, IO16#, CHRDY,
and NOWS# and performs the necessary synchronization of control and status signals between the AT bus
and the microprocessor. The 82C499 supports 8- and
16-bit memory and I/O devices located on the AT bus.
An AT bus cycle is initiated by asserting ALE in AT-TS1
state. On the trailing edge of ALE, M16# is sampled for
a memory cycle to determine the bus size. It then
enters AT-TC state and provides the command signal.
For an I/O cycle, IO16# is sampled after the trailing
edge of ALE until the end of the command. Typically,
the wait state for an AT 8/16-bit transaction is 5/1,
respectively. The command cycle is extended when
CHRDY is detected inactive, or the cycle is terminated
when zero wait state request signal (NOWS#) from the
AT bus is active. Upon expiration of the wait states, the
AT state machine terminates itself and passes an internal Ready to the CPU state machine for outputting a
synchronous RDY# to the CPU. Bit 2 of Index Register
20h allows for the addition of an AT cycle wait state; bit
3 of this same register allows for the generation of a
single ALE instead of multiple ALEs during bus conversion cycles. The AT bus state machine also routes data
and address when an AT bus master or DMA controller
accesses memory.
4.11
Bus Arbitration Logic
The 82C499 provides arbitration between the CPU,
DMA controller, AT bus masters, and the refresh logic.
During DMA, AT bus master, and conventional refresh
cycles, the 82C499 asserts HOLD to the CPU. The
CPU will respond to an active HOLD signal by generating HLDA (after completing its current bus cycle) and
placing most of its output and I/O pins in a high impedance state. After the CPU relinquishes the bus, the
82C499 responds by issuing RFSH# (refresh cycle) or
HLDA (AT bus master or DMA cycle), depending on the
requesting device. During hidden refresh, HOLD
remains negated and the CPU continues its current
program execution as long as it services internal
requests or achieves cache hits (please refer to the
refresh section for additional information).
The AT bus controller in the 82C499 arbitrates
between hold and refresh requests, deciding which will
own the bus once the CPU relinquishes control with the
HLDA signal. The arbitration between refresh and
DMA/master is based on a FIFO (first in-first out) priority. However, a refresh request (RFSH#) will be inter-
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nally latched and serviced immediately after DMA/
master finishes its request if queued behind HRQ.
HRQ must remain active to be serviced if a refresh
request comes first. DMA and bus masters share the
same request pin, HRQ.
4.12
Numeric Coprocessor Cycles (NPX)
The 82C499 monitors NPERR# and NPBUSY# to provide support for the 80387 coprocessor. A coprocessor
asserts NPERR# during a power-on reset to indicate its
presence. The coprocessor asserts NPBUSY# while
executing a floating-point calculation and asserts
RDYI# to the chipset when it is finished. If NPBUSY# is
active and a coprocessor error occurs, (coprocessor
asserts NPERR#) the 82C499 latches NPBUSY# and
generates INT13. Latched BUSY# and INT13 can be
cleared by an I/O Port F0h write command. If the NPU
is not installed, the 82C499 treats any access to the
NPU address space as an AT cycle. With the NPU in
place, CPU accesses to the NPU address space are
direct, except for the re-synchronizing of the numerics
coprocessor ready signal (RDYI#) before sending
READY# back to the CPU.
4.13
Local Bus Interface
The 82C499 allows peripheral devices to share the
“local bus” with the CPU and numerics coprocessor.
The performance of these devices (which may include
the video subsystem, hard disk adapters, LAN and
other PC/AT controllers) will dramatically increase
when allowed to operate in this high-speed environment. These devices are responsible for their own
address and bus cycle decode and must be able to
operate compatibly at the elevated frequencies
required for operation on the local CPU bus.
The LDEV# input signal to the 82C499 indicates that a
local device is intercepting the current cycle. If this signal is sampled at the end of the first T2 clock cycle (end
of the second T2 at 50MHz, whenever ATCLK = CLKI/
6), then the 82C499 will allow the responding local
device to assume responsibility for the current local
cycle. When the device has completed its operation, it
must terminate the cycle by asserting the RDYI# pin of
the 82C499. The RDYI# signal is synchronized by the
82C499 before being sent to the CPU via the RDY#
line. Alternatively, the local bus device may drive RDY#
directly to the CPU. In this case, the local READY signal should be connected to the CPU and 82C499
READY signal. The 82C499 READY signal is bidirectional.
4.14
Data Bus Conversion/Data Path
Control Logic
The 82C499 performs data bus conversion when the
CPU accesses 16- or 8-bit devices through 16- or 32bit instructions. It also handles DMA and AT master
cycles that transfer data between local DRAM or cache
memory and locations on the AT bus. The 82C499 provides all of the signals to control external bidirectional
data buffers.
4.15
Turbo/Slow Mode Operations
Turbo Mode is controlled through pin 99 of 82C499. If
the TURBO input is asserted high, (the jumper on the
board is opened) the system will always run at full
speed and Non-turbo (slow) Mode when the TURBO
input is pulled low (jumper is closed). Slow mode operation is implemented by applying a periodic clock to the
HOLD input of the CPU. OSC12 is the clock source
used for this operation. OSC12 is internally derived
from the 14.31818MHz OSC clock input to the 82C499.
The HOLD is maintained for approximately two-thirds
of the time, while the CPU is allowed to perform normal
external operations during the remaining one-third
interval. For system design, the TURBO pin should be
pulled high through a 10Kohm resistor.
4.16
Fast GATEA20 and RESET Emulation
The 82C499 will intercept commands to Ports 60h and
64h so that it can emulate the keyboard controller,
allowing the generation of the fast GATEA20 and fast
CPURST signals. The decode sequence is software
transparent and requires no BIOS modifications to
function. The fast GATEA20 generation sequence
involves writing “D1h” to Port 64h, then writing data
“02h” to Port 60h. The fast CPU “warm reset” function
is generated when a Port 64h write cycle with data
“FEh” is decoded. A write to Port 64h with data “D0h”
will enable the status of GATEA20 (bit 1 of Port 60h)
and the warm reset (bit 0 of Port 60h) to be readable.
4.17
Special Cycles
The 486 microprocessors provide special bus cycles to
indicate that certain instructions have been executed,
or certain conditions have occurred internally. Special
cycles such as Shutdown and Halt cycles are covered
by dedicated handling logic in the 82C499. Based on
the operating microprocessor mode, this logic decodes
the CPU bus status signals M/IO#, D/C# and W/R# and
takes the appropriate action.
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5.0
Registers Descriptions
Table 5-1
Control Register 1 - Index: 20h
Bit(s)
Default
Function
7:6
00
Revision of 82C499 and is read-only.
5
0
Burst Wait State Control:
1 = Secondary Cache Read-Hit Cycle is x-2-2-2.
0 = Secondary Cache Read-Hit Cycle is x-1-1-1.
No effect on Intel 386, IBM/Cyrix 486DLC.
4
0
AT Clock Source Selections:
0 = Source from CLK2I
3
0
2
0
Single ALE Enable: 82C499 will activate single ALE instead of multiple ALEs during bus conversion
cycle if this bit is enabled.
0 = Disable
1 = Enable
Extra AT Cycle Wait State Enable: Insert one extra wait state for the command signals in standard AT
bus cycle.
0 = Disable
1
0
1 = Source from CLK1
1 = Enable
Emulation keyboard Reset Control:
1 = CPU reset is generated immediately after a write to Port 64h.
0 = A “halt” instruction needs to execute after a write to Port 64h in order to cause a CPU reset.
0
0
Fast Reset: The 82C499 generates a CPU reset whenever a “halt” instruction is executed.
0 = Disable
Table 5-2
1 = Enable
Control Register 2 - Index: 21h
Bits
Default
7
0
Function
Master Mode Byte Swap Enable:
0 = Disable
6
0
1 = Enable
Cache Write Wait States Control
1 = 2 wait states, bit 1 of Index Register 21h will be ignored
0 = Either 0 or 1 wait state, refer to bit 1 of Index Register 21h
5
0
Parity Check:
0 = Enable
4
0
1 = Disable
Cache Enable:
0 = cache is disabled and DRAM burst mode is enabled
1 = cache enable and DRAM burst mode is disabled
3:2
00
Cache Size:
3
0
0
1
1
1
00
2
0
1
0
1
Cache Size
64KB
128KB
256KB
512KB
Cache Write 0/1 Wait State Control with bit 6 of Index Register 21h = 0:
0 = 1 wait state
1 = 0 wait state
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82C499
Bits
Default
0
00
Function
Cache Read Wait State Control:
For Intel 486:
0 = 3-x-x-x cycle
1 = 2-x-x-x cycle
For Intel 386, IBM/Cyrix 486DLC:
0 = 1ws
Table 5-3
1 = 0ws
Shadow RAM Control Register I - Index: 22h
Bit(s)
Default
7
1
Function
ROM(F0000-FFFFFh) Enable:
1 = Read from ROM, write to DRAM. ROMCS# is generated during read access only.
0 = Read/write on DRAM and DRAM is write-protected.
6
0
Shadow RAM at D0000h-DFFFFh Area:
0 = Disable
5
0
1 = Enable
Shadow RAM at E0000h-EFFFFh Area:
0 = Disable shadow RAM, enable ROMCS#. The E0000-EFFFFh ROM is defaulted to reside on XD
bus.
1 = Enable shadow RAM and disable ROMCS# generation.
4
0
Shadow RAM at D0000h-DFFFFh Area Write Protect Enable:
0 = Disable
3
0
Shadow RAM at E0000h-EFFFFh Area Write Protect Enable:
0 = Disable
2
1
0
1 = Enable
Hidden Refresh Enable (without holding CPU):
1 = Disable
1
1 = Enable
0 = Enable.
Fast GATEA20/A20M#:
Intel 386 Mode:
1 = GA20 is high
0 = Controlled by keyboard emulation
0
0
Slow Refresh Enable (four times slower than the normal refresh)
0 = Disable
Table 5-4
Intel486 IBM/Cyrix 486DLC Mode:
1 = A20M# is always high, no address wraps around
0 = Controlled by keyboard emulation
1 = Enable
Shadow RAM Control Register II - Index: 23h
Bit
Default
7
0
Function
Shadow RAM at EC000h-EFFFFh Area:
0 = Disable
6
0
Shadow RAM at E8000h-EBFFFh Area:
0 = Disable
5
0
0
1 = Enable
Shadow RAM at E4000h-E7FFFh Area:
0 = Disable
4
1 = Enable
1 = Enable
Shadow RAM at E0000h-E3FFFh Area:
0 = Disable
1 = Enable
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82C499
Bit
Default
3
0
Function
Shadow RAM at DC000h-DFFFFh Area:
0 = Disable
2
0
Shadow RAM at D8000h-DBFFFh Area:
0 = Disable
1
0
0
1 = Enable
Shadow RAM at D0000h-D3FFFh area
0 = Disable
Table 5-5
1 = Enable
Shadow RAM at D4000h-D7FFFh Area:
0 = Disable
0
1 = Enable
1 = Enable
DRAM Control Register I - Index: 24h
Bit(s)
Default
7
1
0 = 256KB DRAM mode
1 = 1MB and 4MB DRAM mode. See Table 4, “DRAM Configurations,” on page 16.
6:4
000
DRAM types used for Bank 0 and Bank 1. Refer to Table 4-4 for detailed description.
3
0
2:0
111
Table 5-6
Function
Unused
DRAM types used for Bank 2 and Bank 3. Refer to Table 4-4 for detailed description.
DRAM Control Register II - Index: 25h
Bit(s)
Default
7:6
11
Function
CAS# Wait State Control for DRAM Read Cycle:
7
0
6
0
CAS# Pusle
width Cycle TimeNotes
n/a
n/a
Not used.
0
1
3 CLKs 7-5-5-5 CAS# will shift later by 1 CLK and the CAS# pulse width will
increase by 1 CLK
1
1
5:4
3
11
0
0
1
4 CLKs 8-6-6-6 Only CAS# pulse width increases
5 CLKs 9-7-7-7 Only CAS# pulse width increases
CAS# Wait State Control for DRAM Write Cycle:
5
4
CAS# PulseCAS#Cycle
Width PrechargeTime
0
0
1
1
0
1
0
1
2 CLKs
2 CLKs
3 CLKs
4 CLKs
1 CLK
3 CLKs
3 CLKs
3 CLKs
6-3-3-3
8-5-5-5
9-6-6-6
10-7-7-7
Fast Decode Enable. This function may be enabled in 20/25MHz operation to speed up the DRAM
access.
0 = Disable fast decode, DRAM base wait states is not changed
1 = Enable fast decode, DRAM base wait states is decreased by 1
This bit is automatically disabled even when it is set to 1 when bit 4 of Index register 21h (cache
enable bit) is enabled. It only affects the DRAM lead-off cycle.
2
0
CAS# Delay for DMA/Master Cycles:
0 = Disable - CAS# will be generated one CPUCLK after RAS# is asserted.
1 = Enable - CAS# will be generated after RAS# is asserted for two CPUCLKs.
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82C499
Bit(s)
Default
1:0
00
Table 5-7
Function
ATCLK Selection (refer to bit 4 of Index Register 20h):
1
0
0
0
0
1
1
1
0
1
ATCLK Selection
CLKI/6
(Default, indicate 82C499 is running at 50MHz, LDEV# will be
sampled at the end of the second T2)
CLKI/5
CLKI/4
CLKI/3
Shadow RAM Control Register III - Index: 26h
Bit(s)
Default
7
0
Function
Enable ROMCS# for Write Cycles:
1 = Enable, generates ROMCS# for write cycles to support flash ROMs.
0 = Disable
6
0
Shadow RAM copy enable for address area C0000h-CFFFFh:
0 = Read/write at AT bus
1 = Read from AT bus and write into shadow RAM
5
0
Shadow write protect at address area C0000h-CFFFFh:
0 = Write protect disable
1 = Write protect enable
4
0
Shadow RAM enable at C0000h-CFFFFh Area:
0 = Disable
3
0
Enable shadow RAM at CC000h-CFFFF Area:
0 = Disable
2
0
0
0
1 = Enable
Enable shadow RAM at C0000h-C3FFFh Area:
0 = Disable
Table 5-8
1 = Enable
Enable shadow RAM at C4000h-C7FFFh Area:
0 = Disable
0
1 = Enable
Enable shadow RAM at C8000h-CBFFF Area:
0 = Disable
1
1 = Enable
1 = Enable
Control Register 3 - Index: 27h
Bit(s)
Default
7
1
Function
Global Cache Enable: This bit determines whether all cycles are cacheable in L1 and L2 cache.
0 = Disable L1 and L2 cache
6
1
1 = Enable L1 and L2 cache
Fast AT Cycle:
0 = Disable, BALE# will be asserted 1 ATCLK late as standard AT cycles
1 = Enable, standard AT cycles
5
0
Back-to-Back I/O Delay Control:
0 = Three BLK back-to-back I/O delay
1 = Zero back-to-back I/O delay
4
1
Video BIOS at C0000h-C8000h area non-cacheable:
0 = Cacheable
1 = Non-cacheable
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82C499
Bit(s)
Default
3:0
0001
Note
Function
Cacheable Address Range for Local Memory:
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Cacheable Address Range
0-64MB
0-4MB
0-8MB
0-12MB
0-16MB
0-20MB
0-24MB
0-28MB
0-32MB
0-36MB
0-40MB
0-44MB
0-48MB
0-52MB
0-56MB
0-60MB
Note
If total memory is 1MB or 2MB, the cacheable range is 0-1 or 0-2MB respectively
and independent of the value of bits [3:0] of Index Register 27h.
Memory area at 640KB-1MB is defaulted to be non-cacheable.
Table 5-9
Non-Cacheable Block 1 Register - Index: 28h
Bit(s)
Default
7:5
100
Function
Size of Non-cachable Memory Block 1:
7
0
0
0
0
1
6
0
0
1
1
X
5
0
1
0
1
X
Block Size
64KB
128KB
256KB
512KB
Disabled
4:2
000
Unused
1:0
00
Address bits of A25 and A24 of Non-cachable Memory Block 1
This register is used in conjunction with Index Register 29h to define a non-cacheable block. The starting address
for the non-cacheable block must have the same granularity as the block size. For example, if a 512KB noncacheable block is selected, its starting address is a multiple of 512KB; consequently, only address bits of
A[23:19] are significant, A18:16] are "don't care".
Table 5-10 Non-Cacheable Block 1 Register II - Index: 29h
Bit(s)
Default
7:0
0001
XXXX
Function
Address bits A[23:16] of Non-cacheable Memory Block 1
Block Size
64KB
128KB
256KB
512KB
A23
A22
V
V
V
V
V
V
V
V
Valid Starting Address Bits
A21
A20
A19
A18
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
X
A17
A16
V
V
X
X
V
X
X
X
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82C499
X = Don't Care
V = Valid Bit
Table 5-11 Non-Cacheable Block 2 Register I - Index: 2Ah
Bit(s)
Default
7:5
100
Function
Size of Non-cacheable Memory Block 2:
7
0
0
0
0
1
4:3
00
6
0
0
1
1
X
5
0
1
0
1
X
Block Size
64KB
128KB
256KB
512KB
Disabled
ECAWE#/OCAWE# Pulse Width for Master Cache Write-Hit Cycles:
4
0
1
1
0
3
0
0
1
1
Selections
3 CLKs (default)
1 CLK
Unused
Unused
2
0
Unused, must be set to 1 by BIOS.
1:0
0
Address bits of A25 and A24 of Non-cacheable Memory Block 2
This register is used in conjunction with Index Register 2Bh to define a non-cacheable block. The starting address
for the non-cacheable block must have the same granularity as the block size. For example, if a 512KB noncacheable block is selected, its starting address is a multiple of 512KB; consequently, only address bits of A[23:19]
are significant, [A18:16] are "don't care".
Table 5-12 Non-Cacheable Block 2 Register II - Index: 2Bh
Bit(s)
Default
7:0
0001
XXXX
Function
Address bits A[23:16] of Non-cacheable Memory Block 2
Block Size
64KB
128KB
256KB
512KB
A23
A22
V
V
V
V
V
V
V
V
Valid Starting Address Bits
A21
A20
A19
A18
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
X
A17
A16
V
V
X
X
V
X
X
X
X = Don't Care
V = Valid Bit
Table 5-13 ROM Chip Select (ROMCS#) Control Register - Index: 2Dh
Bit(s)
Default
Function
7
0
Unused
6
1
0 = IBM 486DLC CPU. This bit is write-only.
Note: This bit must be cleared to 0 by the BIOS to support the IBM 486DLC (Blue Lightning) CPU.
5
0
Enable ROMCS# at E8000h-EFFFFh Segment:
0 = Disable
1 = Enable
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82C499
4
0
Enable ROMCS# at E0000h-E7FFFh Segment:
0 = Disable
3
0
1 = Enable
Enable ROMCS# at D8000h-DFFFFh Segment:
0 = Disable
2
0
Enable ROMCS# at D0000h-D7FFFh Segment:
0 = Disable
1
0
1 = Enable
Enable ROMCS# at C8000h-CFFFFh Segment:
0 = Disable
0
0
1 = Enable
Enable ROMCS# at C0000h-C7FFFh Segment:
0 = Disable
5.1
1 = Enable
1 = Enable
I/O Port 60h
Port 60h and 64h emulate the registers of a keyboard controller, allowing the generation of a fast gate A20 signal.
The sequence here is BIOS transparent and there is no need for the modification of the current BIOS. The
sequence involves writing data D1h to Port 64h, then writing data 02h to Port 60h.
Table 5-14 I/O Port 61h(Port B)
Bit(s)
Type
0
R/W
Timer 2 Gate
1
R/W
Speaker Output Enable
2
R/W
Parity Check Enable
3
R/W
I/O Channel Check Enable
4
R
Refresh Detect
5
R
Timer OUT2 Detect
6
R
I/O Channel Check
7
R
System Parity Check
5.2
Function
I/O Port 64h
I/O Port 64h emulates the register inside a keyboard controller by generating a fast reset pulse. Writing data FEh to
Port 64h asserts the reset pulse. The pulse is generated immediately after the I/O write if bit 6 of Index Register
21h is set, otherwise the pulse is asserted 2µs after the write.
Table 5-15 I/O Port 70h
Bit(s)
Default
7
0
Function
NMI Enable
Table 5-16 Port 92h - System Controller Port A, PS/2 Compatibility Port
Bit(s)
Default
Function
1
1 = Set Alernate Fast GATEA20 Active
0
1 = Set Alternate Fast Reset Active
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82C499
6.0
Maximum Ratings
Stresses above those listed in the following tables may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification are not implied.
6.1
Absolute Maximum Ratings
Symbol
Parameter
VCC
Supply Voltage
Min
Max
Unit
+6.5
V
VI
Input Voltage
-0.5
VCC + 0.3
V
VO
Output Voltage
-0.5
VCC + 0.3
V
TOP
Operating Temperature
-25
+70
°C
TSTG
Storage Temperature
-40
+125
°C
6.2
DC Characteristics
Ta = -25°C to +70°C, Vcc = 5.0V ±5%
Symbol
Parameter
Min
Max
Unit
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.3
V
0.4
V
LOL = 4.0mA
V
IOH = -1.6mA
VOL
Output Low Voltage
VOH
Output High Voltage
IIL
Input Leakage Current
10
µA
IOZ
Tristate Leakage Current
10
µA
CIN
Input Capacitance
10
pF
COUT
Output Capacitance
10
pF
ICC
Power Supply Current
80
mA
2.4
Condition
VIN = VCC
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82C499
6.3
AC Timing Characteristics
Preliminary - Temperature: 0°C to +70°C, VCC: 5V +/- 5%
Table 6-1
82C499 B1 AC Characteristics
Sym
Description
t100a
CLKIá delay from CLK2Iá
t100b
t103
t103a
t104
t104a
t201
t202
t203
CLKIâ delay from CLK2Iá
CPURST active delay from CLKI á
CPURST active delay from CLK2I á
CPURST inactive delay from CLKIá
CPURST inactive delay from CLK2Iá
CLKIá to CAS# active delay, refresh
CLKIâ to CAS# inactive delay, refresh
CLKIá or CLKIâ to RAS# active delay, refresh
Min
Typ
Max
Units
7
ns
3
7
ns
4
20
ns
3
7
ns
4
20
ns
3
3
7
ns
7
21
ns
7
21
ns
7
21
ns
21
ns
t204
CLKIá or CLKIâ to RAS# inactive delay, refresh
t205
RAS# pulsh width, refresh
4CLKs
t206
CAS# pulsh width, refresh
5.5CLKs
t210
t211
LDEV# setup time to CLKIá
LDEV# hold time to CLKIá
t213
KEN# active delay from CLKI á
t214
KEN# inactive delay from Address
7
4
ns
5
ns
15
ns
20
ns
RDYI# setup time to CLKI á
4
t216
RDYI hold time to CLKIá
5
t301
D(31:0) valid to SD(15:0) valid delay
10
100
ns
t302
D(31:0) valid to MP(3:0) valid delay
15
30
ns
t303
D(31:0) invalid to SD(15:0) invalid delay
10
25
ns
t304
D(31:0) invalid to MP(3:0) invalid delay
15
30
ns
t305
SD(15:0) valid to D(31:0) valid delay
10
20
ns
t306
SD(15:0) invalid to D(31:0) invalid delay
10
20
ns
t313
A(9:0) to KBDCS# active delay
10
100
ns
t314
A(9:0) to KBDCS# inactive delay
10
30
ns
t402
CPU address and status valid to BEOE# active delay
5
21
ns
t403
CLKIá to BEOE# /BOOE# inactive delay
5
13
ns
5
14
ns
t215
t404
t405
t406
t407
t408
t411
CLKIá to BEOE#/BOOE# active delay
CLKIá to CA32S# inactive delay
CLKIá to CA32S# active delay
CLKIá (from TAG address valid) to BRDY# active delay
CLKIá to BRDY# inactive delay
CLK2Iá to ECAWE#/OCAWE# active delay, 0WS (requires 2X
clock input)
ns
ns
5
14
ns
5
14
ns
5 (9)
15 (15)
ns
5
15
ns
5
10
ns
t412
CLK2Iá to ECAWE#/OCAWE# inactive delay, 0WS (requires 2X
clock input)
5
10
ns
t413
CLKIâ to ECAWE#/OCAWE# active delay, 1WS
20
22
ns
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Table 6-1
82C499 B1 AC Characteristics (cont.)
Sym
Description
t413a
CLKIá to ECAWE#/OCAWE# active delay, cache line fill
t414
t414a
t415
t416
t417
t418
t419
t420
CLKIâ to ECAWE#/OCAWE# inactive delay, 1WS
CLKIá/CLKI â to ECAWE#/OCAWE# inactive delay, cache line fill
CLK2Iá to DTYWE# active delay, 0WS (requires 2X clock input)
CLK2Iá to DTYWE# inactive delay, 0WS (requires 2X clock input)
CLKIâ to DTYWE# active delay, 1WS
CLKIâ to DTYWE# inactive delay, 1WS
CLKIá (from TAG address valid) to RDY# active delay
CLKIá to RDY# inactive delay
Min
Typ
7
Max
Units
21
ns
10
12
ns
7
21
ns
5
10
ns
5
10
ns
20
22
ns
10
12
ns
5 (9)
15 (15)
ns
5
15
ns
t421
DTYWE# active to DRTY active
2
4
ns
t422
DTYWE# inactive to DRTY inactive
2
4
ns
t423
CLKIâ to TAGWE# active delay
20
22
ns
10
12
ns
5 (7)
15 (21)
ns
5
15
ns
t424
t425
t425a
CLKIâ to TAGWE# inactive delay
CLKIá to BEA3/BEA2OA3 active delay, cache hit (cache line fill)
CLKIâ to BEA3/BEA2OA3 active delay, cache hit
t426
CLKIá to BEA3/BEA2OA3 hi-Z
5
15
ns
t427
TAGWE# active to TAG data active
2
4
ns
t428
t429
t430
t433
t434
TAGWE# inactive to TAG data inactive
CLKIá to CAS# active delay
CLKIá to CAS# inactive delay
CLKIá to RAS# inactive delay
CLKIá to RAS# active delay
t435
CLKIá to column address valid delay
t436
CPU address valid to row/column address valid delay
t437
t438
CLKIá to DWE# active delay
CLKIâ to DWE# inactive delay
t439
CLKIá to new row address delay
t440
RAS# precharge time
t441
CAS# precharge time
t442
CLKIá to ROMCS# active delay
2
4
ns
5
15
ns
5
15
ns
5
15
ns
5
15
ns
5
15
ns
5
15
ns
5
15
ns
5
15
ns
10
25
ns
7
21
ns
7
21
ns
3 CLKI
1 CLKI
t443
CLKIá to ROMCS# inactive delay
t454
MEMR# active to BEOE#/BOOE# active delay, DMA
10
20
ns
t455
MEMR# inactive to BEOE#/BOOE# inactive delay, DMA
10
20
ns
t456
CLKIá to EADS# active delay, DMA
CLKIá to EADS# inactive delay, DMA
6
18
ns
t457
6
18
ns
t458
MEMR#/MEMW# active to RAS# active delay, DMA
10
20
ns
t459
MEMR#/MEMW# inactive to CAS# inactive delay, DMA
10
20
ns
t465
MEMW# active to DWE# active delay, DMA
10
20
ns
t466
MEMW# inactive to DWE# inactive delay, DMA
10
20
ns
t467
DRTY set up time to CLKIá
4
ns
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82C499
Table 6-1
82C499 B1 AC Characteristics (cont.)
Sym
Description
t468
DRTY hold time to CLKIá
5
BCLKá to ALE inactive delay
2
20
ns
2
20
ns
2
20
ns
2
20
ns
2
20
ns
t501
t502
t503
t504
t505
t506
t507
t508
t509
t510
t511
t512
t513
t515
t516
t517
t518
t519
t520
t521
BCLKâ to ALE active delay
BCLKâ to CMD active delay
BCLKá to CMD inactive delay
BCLKá to CMD active delay
MCS16# to BCLKá setup time
MCS16# to BCLKá hold time
IOCS16# to BCLKá setup time
IOCS16# to BCLKá hold time
OWS# to BCLKâ setup time
OWS# to BCLKâ hold time
CHRDY to BCLKá setup time
CHRDY to BCLKá hold time
CLKá to HOLD active delay
CLKá to HOLD inactive delay
BCLKá to REF# active delay
BCLKá to REF# inactive delay
BCLKá to MEMR# active delay, refresh
BCLKá to MEMR# inactive delay, refresh
BCLKá to SA[1:0] active delay
Min
Typ
Max
Units
ns
10
ns
10
ns
10
ns
10
ns
10
ns
20
ns
10
ns
20
ns
7
21
ns
7
21
ns
8
30
ns
8
30
ns
5
25
ns
5
25
ns
7
21
ns
t522
BCLKá to SA[1:0] inactive delay
7
21
ns
t523
CMD# active to XDIR# active delay
5
15
ns
t524
CMD# inactive to XDIR# inactive delay
5
15
ns
6
18
ns
t530
CLKá to ADS# active delay, DMA
t531
CLKá to ADS# inactive delay, DMA
6
18
ns
t532
MEMR#/MEMW# active to M/IO valid delay, DMA
7
21
ns
t533
MEMR#/MEMW# inactive to M/IO invalid delay, DMA
7
21
ns
t534
MEMR#/MEMW# active to W/R valid delay, DMA
7
21
ns
7
21
t535
t536
t537
t538
t539
t540
Note
MEMR#/MEMW# inactive to W/R invalid delay, DMA
LREQ# setup time to CLKá
LREQ# hold time to CLKá
HLDA setup time to CLKá
HLDA hold time to CLKá
CLKá to LGNT# active delay
ns
4
ns
5
ns
4
ns
5
10
ns
25
ns
Notes:1.á means rising edge
Note
2.â means falling edge
Note
3.The capacitance loading is 50pF
OPTi
®
Page 32
912-3000-001
82C499
6.4
AC Timing Waveforms
Figure 6-1
2-1-1-1 Double Bank Cache Read Hit Cycle
t408
T2
t425
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t407
t425a
t425a
t405
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t402
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t408
t426
t426
t406
t403
T1
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
t404
t403
T2
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
t425
t403
t404
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t425
t405
t404
t403
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t407a
t425a
t402
T2
t425a
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t426
t426
T1
t406
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
RDY#
DRTY
DRTYW#
TAGWE#
ECAWE#/OCAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
BEOE#
BOOE#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
OPTi
®
912-3000-001
Page 33
82C499
Figure 6-2
3-1-1-1 Single Bank Cache Read Hit Cycle
t408
t426
t426
t406
t403
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t407
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t408
t425
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
t407
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t408
t425
T2
t425
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
t407
AAAA
A
AA
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
RDY#
DRTY
DRTYW#
TAGWE#
ECAWE#/OCAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
BEOE#
BOOE#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
AAAA
A
AA
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
OPTi
®
Page 34
912-3000-001
82C499
Figure 6-3
Zero-Wait State Write Hit Cycle
t408
t420
t422
T1
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t407
t419
t416
t415
t421
t412
t411
T2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T1
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAAAA
BRDY#
RDY#
TAGWE#
DRTY (from '499)
DRTYW#
ECAWE#/OCAWE#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
912-3000-001
Page 35
82C499
t408
One-Wait State Cache Write Hit Cycle
t420
Figure 6-4
t407
t419
T2
t414
t418
t422
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t417
BRDY#
RDY#
TAGWE#
DRTY (from '499)
DRTYW#
ECAWE#/OCAWE#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
T2
t413
t421
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
Page 36
912-3000-001
82C499
only for ISA master when bit 4,3 of 2A =1
DMA/ISA master write to DRAM & cache, with RAS#, CAS#, DWE# generated as above and ECAWE#/OCAWE#
DMA/ISA master write to DRAM, with RAS#, CAS# generated as above and the DWE#
DMA/ISA Master Transfer
T
Figure 6-5
default for ISA master
(bit 4,3 of 2a = 00and DMA
t466
t455
t459
t459
T2
t433
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
DMA/ISA master read from cache, only BOOE#/BEOE# is generated only
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
bit 2 of 25h = 1
bit 2 of 25h = 0, default
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
DMA/ISA master read from DRAM, RAS# & CAS# are generated
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t414a
t429
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t429
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t457
t414a
t457
t435
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t413a
t456
t465
t454
t458
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t456
t413a
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
t439
T2
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
EADS#
ECAWE#/OCAWE#
ECAWE#/OCAWE#
EADS#
DWE#
BOOE#/BEOE#
CAS[3:0]#
CAS[3:0]#
MA[10:0]
RAS#x
MEMR#/MEMW#
IOR#/IOW#
ATCLK
CLKI
CLK2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
OPTi
®
912-3000-001
Page 37
82C499
Figure 6-6
One-Wait State DRAM Read
t430
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
Page Hit
t420
t419
T1 T2 T2 T2T2 T2 T2 T2 T2 T2 T2T2 T1 T2 T2 T2 T2 T2 T2 T2 T2T2 T1 T2 T2 T2 T2 T2 T2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t434
t435
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t439
t436
t433
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
Page Miss
Different Banks
t420
t419
t436
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t419
t420
t430
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
t429
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t439
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t436
t433
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
Page Miss
t434
t435
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
BRDY#
RDY#
BLAST#
DWE#
MA[10:0]
CAS[3:0]#
RAS1#
RAS0#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AA
AAAA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
OPTi
®
Page 38
912-3000-001
82C499
Figure 6-7
One-Wait State DRAM Page Hit Burst Read
t430
Ti Ti Ti Ti Ti T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2T2 T2 T2 T2 T2 T2 Ti Ti
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t419
t420
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t420
t420
t419
t419
t436
t430
t429
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t429
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
t430
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t419
t420
t435
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
t430
t429
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t436
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
RDY#
BRDY#
BLAST#
DWE#
MA[10:0]
CAS[3:0]#
RAS0#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
912-3000-001
Page 39
82C499
Figure 6-8
One-Wait State DRAM Burst Read, RAS# Inactive
t430
Ti Ti Ti T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2T2 T2 T2 T2 T2 T2 Ti Ti
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t419
t420
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t420
t420
t419
t419
t436
t430
t429
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t419
t420
t435
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
t430
t429
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t434
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
t436
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
RDY#
BRDY#
BLAST#
DWE#
MA[10:0]
CAS[3:0]#
RAS0#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
OPTi
®
Page 40
912-3000-001
82C499
t420
t419
One-Wait State DRAM Page Miss Burst Read
t430
Figure 6-9
T2 T2 T2 T2 T2 Ti
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t420
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t436
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
T2 T2 T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t429
t419
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t420
t419
T2 T2 T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t430
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t420
t419
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t435
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
t429 t430
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t434
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t439
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t433
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t436
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
RDY#
BRDY#
BLAST#
DWE#
MA[10:0]
CAS[3:0]#
RAS0#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
OPTi
®
912-3000-001
Page 41
82C499
t430
Figure 6-10 Zero-Wait State DRAM Write
t438
T2 T2 T1 T2 T2 T2 T2 T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t420
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t437
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t438
t436
t430
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
Page Hit
t419
t429
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t419
t420
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2 T2 T1 T2 T2 T2
t434
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t437
t439
t433
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t438
t436
t430
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
Page Miss
Different Banks
t429
t435
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
t419
t420
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t435
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AA
T1 T2 T2 T2 T2 T2 T2
t434
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t439
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t433
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t437
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AA
t436
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
Page Miss
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
BRDY#
RDY#
DWE#
MA[10:0]
CAS[3:0]#
RAS1#
RAS0#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
AAAA
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AA
OPTi
®
Page 42
912-3000-001
82C499
Figure 6-11 One-Wait State DRAM Write
t419
t430
t429
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
Page Hit
t420
T1 T2 T2 T2 T2 T2 T2 T2 T2 T1 T2 T2 T2 T2 T2 T2 T1 T2 T2 T2 T2 T2 T2 T2
t438
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t437
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t430
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t420
t438
t436
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t419
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t437
t439
t434
t433
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t438
t436
t430
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
Page Miss
Different Banks
t435
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t420
t419
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
t429
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
t439
t434
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t433
t437
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
t436
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
Page Miss
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
BRDY#
RDY#
DWE#
MA[10:0]
CAS[3:0]#
RAS1#
RAS0#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
912-3000-001
Page 43
82C499
one more ATCLK delay if AT extra WS is set
BALE will be generated 1 ATCLK late if fast AT cycle option is disabled
Figure 6-12 ISA Bus Cycles
0WS#, IOCHRDY will be sampled the same way as in the 8-bit cycle
one more ATCLK delay if AT extra WS is set
t420
t419
t504
one more ATCLK delay if AT extra WS is set
t512
t513
T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAA
A
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
8-bit ISA bus cycles
t511
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t510
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t420
t419
t504
t504
16-bit ISA bus cycles
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAA
A
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t503
t503
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t505
t502
t506
t508
t507
t509
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t501
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAA
A
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
A
RDY#
IOCS16#
MCS16#
16-bit IOR#/IOW#
16-bit MEMR#/MEMW#
RDY#
IOCHRDY
0WS#
IOCS16#
MCS16#
8 -bit ISA bus CMD#s
BALE
MIO, DC, WR, A[31..2]
ADS#
ATCLK
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
Page 44
912-3000-001
82C499
Figure 6-13 Keyboard Controller Access Cycles
t314
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t419
t420
t504
T1 T2T2 T2T2 T2T2 T2 T2 T2 T2 T2T2 T2T2 T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2T2 T2 T2
t524
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t503
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t523
t502
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t501
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t313
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
RDY#
IOR#/IOW#
KBCS#
XDIR#
BALE
SA[9:2]
MIO, DC, WR, A[31..2]
ADS#
ATCLK
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
OPTi
®
912-3000-001
Page 45
82C499
Figure 6-14 CPU Reset
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAA
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
f2
f2
Ti
t104
f1
f1
f1
CPURST
CLKI
CLK2
CPURST
CLKI
CLK2
CPURST
CLKI
CLK2
CPURST
CLKI
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
CLK2
f1
t103
Ti
f2
t104a
Ti
f2
t103a
Ti
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
CPURST for 1X clock CPUs
Ti
f1
Ti
f2
f1
CPURST for 2X clock CPUs
f1
Ti
f2
AAAA
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
f2
f1
Ti
f2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
OPTi
®
Page 46
912-3000-001
82C499
T
Figure 6-15 Refresh Cycle
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
Ti
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t204
Ti
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t204
Ti
t204
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t202
Ti
t204
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
Ti
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AA
t203
t205
Ti
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t203
t203
t206
Ti
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t203
Ti
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
Ti
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AA
t204
t201
Ti
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t204
Ti
t204
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
Ti
t204
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
Ti
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AA
RAS3#
RAS2#
RAS1#
RAS0#
CAS[3:0]#
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
912-3000-001
Page 47
82C499
Figure 6-16 Cache Read Miss Dirty: 2 banks of cache and 0/0 DRAM wait state (1 of 2)
OPTi
®
Page 48
912-3000-001
82C499
T2
t43
Figure 6-17 Cache Read Miss Dirty: 2 banks of cache and 0/0 DRAM wait state (2 of 2)
t430
t438
t403
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t429
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
T2
t430
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
t404
T2
t403
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t430
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
t403
T2
t404
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t430
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
t404
T2
t403
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
T2
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t435
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t434
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t439
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t428
t424
T2
t418
t422
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t427
t423
t421
t417
T2
t433
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t425a
t426
t437
t425a
t426
T2
t405
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t436
t402
t406
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T1
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
TAG[7:0] (from '499)
TAGWE#
DRTY (from '499)
DRTYW#
RDY#
CAS[3:0]#
RASx#
MA[10:0]
DWE#
BOOE#
BEOE#
OCAWE#
ECAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
912-3000-001
Page 49
82C499
Figure 6-18 Cache Read Miss Dirty: 1 bank of cache and 0/0 DRAM wait state (1 of 2)
t404
t406
t408
t403
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t403
T2
t403
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t404
T2
t425
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
t408
t407
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t407
t404
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
t429
t435
t414a
t413a
T2
t425
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t414a
T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
t429
t430
T2
t435
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AA
t425
T2
t425
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
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AAAAAAAA
AAAA
AA
t430
t413a
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
t435
T2
t414a
t413a
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
t414a
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t435
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
t413a
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t435
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t434
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t439
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
TAG[7:0] (from '499)
TAGWE#
DRTY (from '499)
DRTYW#
RDY#
CAS[3:0]#
RASx#
MA[10:0]
DWE#
BOOE#
BEOE#
OCAWE#
ECAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
OPTi
®
Page 50
912-3000-001
82C499
T2
t43
Figure 6-19 Cache Read Miss Dirty: 1 bank of cache and 0/0 DRAM wait state (2 of 2)
t430
t438
T2
t403
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t429
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
T2
t430
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t425
t435
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t430
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
T2
t425
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t425
AAAA
A
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
T2
t430
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
T2
t425
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
AAAA
A
A
T2
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t435
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t434
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t439
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t428
t424
T2
t418
t422
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t427
t423
t421
t417
T2
t433
AAAA
A
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t437
t425a
t425a
T2
t405
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t436
t402
t426
t426
t406
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T1
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
TAG[7:0] (from '499)
TAGWE#
DRTY (from '499)
DRTYW#
RDY#
CAS[3:0]#
RASx#
MA[10:0]
DWE#
BOOE#
BEOE#
OCAWE#
ECAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
912-3000-001
Page 51
82C499
t407
t408
t408
Figure 6-20 Cache Read Miss Dirty: 2 banks of cache and 1/1 DRAM wait state (1 of 2)
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t403
t425
t406
T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2
CLKI
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t408
t407
t425
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t404
t408
t407
t407
t425
t425
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t413a
t414a
t414a
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t435
t429
t430
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t425
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t430
AAAA
AA
A
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
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AA
A
t429
t435
t413a
t425
t425
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t430
AAAA
AA
A
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
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AA
A
t429
t435
t414a
t413a
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t430
t425
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t429
t414a
t435
AAAA
AA
A
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
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AA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t434
t413a
t435
AAAA
AA
A
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
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AA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t439
TAG[7:0] (from '499)
TAGWE#
DRTY (from '499)
DRTYW#
RDY#
CAS[3:0]#
RASx#
MA[10:0]
DWE#
BOOE#
BEOE#
OCAWE#
ECAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
MIO, DC, WR, A[31..2]
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
ADS#
CLK2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
Page 52
912-3000-001
82C499
Figure 6-21 Cache Read Miss Dirty: 2 banks of cache and 1/1 DRAM wait state (2 of 2)
t429
t413a
T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t434
t433
t439
t435
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
t429
t438
t403
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
t435
t404
t403
AA
AAAA
AA
AA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
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AAAAAAAA
AAAAAAAA
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AAAAAAAA
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AAAAAAAA
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AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AA
AA
AAAA
AAAA
AAAA
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AAAA
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AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
t429
t435
t403
t404
t425
t425
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
t435
t435
t404
t403
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
AA
AAAA
AA
AA
AAAAAAAA
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AA
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AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t428
t427
t424
t423
t422
t421
t418
t417
t439
t437
t425a
t426
t425a
t426
t405
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAA
AA
AA
AAAAAAAA
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AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t436
t406
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t402
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAA
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AAA
AA
AA
AAAA
AA
AA
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AA
AA
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AAAAAAAA
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AAAAAAA
AAA
AA
TAG[7:0] (from '499)
TAGWE#
DRTY (from '499)
DRTYW#
RDY#
CAS[3:0]#
RASx#
MA[10:0]
DWE#
BOOE#
BEOE#
OCAWE#
ECAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
OPTi
®
912-3000-001
Page 53
82C499
Figure 6-22 Cache Read Miss Dirty: 1 bank of cache and 1/1 DRAM wait state (1 of 2)
t403
t408
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t406
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t403
t404
t425
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t403
t408
t407
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
t435
t404
t404
t425
T2 T2 T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t414a
t407
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
t413a
T2 T2
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
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AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t414a
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
T2 T2
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
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AA
t435
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t413a
T2 T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
t425
t425
AAAA
A
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A
AAAA
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AA
t430
t414a
T2 T2 T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t435
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
t413a
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
t414a
T2 T2
AAAA
A
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A
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AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t435
CLKI T2 T2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
TAG[7:0] (from '499)
TAGWE#
DRTY (from '499)
DRTYW#
RDY#
CAS[3:0]#
RASx#
MA[10:0]
DWE#
BOOE#
BEOE#
OCAWE#
ECAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
MIO, DC, WR, A[31..2]
ADS#
CLK2
AAAA
A
AAAA
AA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
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AA
OPTi
®
Page 54
912-3000-001
82C499
Figure 6-23 Cache Read Miss Dirty: 1 bank of cache and 1/1 DRAM wait state (2 of 2)
t430
t438
t433
t403
T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
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A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
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t429
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
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A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
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A
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t430
t425
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
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A
t429
t435
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A AAAA
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A
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t430
t435
t425
t425
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A
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A
t429
A
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A
A
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A
A
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A
t430
A
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A
t425
t435
t435
A
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A
t429
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A
A
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A
t428
t427
t422
t421
A
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A
t424
t439
t418
t417
A
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A
t423
t437
AAAA
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A
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A
A
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A
A
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A
t436
t402
t425a
t426
t425a
t426
t405
t406
AAAA
A
A
A AAAA
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AAAAAAAA
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A
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A
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A
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A
MIO, DC, WR, A[31..2]
TAG[7:0] (from '499)
TAGWE#
DRTY (from '499)
DRTYW#
RDY#
CAS[3:0]#
RASx#
MA[10:0]
DWE#
BOOE#
BEOE#
OCAWE#
ECAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
ADS#
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
CLKI
CLK2
AAAA
A
A
A AAAA
AAAA
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A
A
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A
OPTi
®
912-3000-001
Page 55
82C499
Figure 6-24 Cache Read Miss Not Dirty: 2 banks of cache and 0 DRAM read wait state
t406
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t403
t408
t407
t408 t408
t407 t407
CLKI T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t430
t435
t404
t414a
t425
t425
t425
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
A
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A
t408
t407
t425
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
t429
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t425
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
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t430
t413a
t414a
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
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A
t429
t413a
t435
AAAA
AA
A
AA AAAA
AAAA
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A
AA
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A
t425
t425
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t430
AAAA
AA
A
AA AAAA
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AA
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t435
t414a
t413a
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
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A
AA
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A
t425
t429
t430
AAAA
AA
A
AA AAAA
AAAA
AAAAAAAA
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A
AA
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A
t435
t414a
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA AAAA
AAAA
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A
AA
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A
A
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A
t429
t413a
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAA
A
AA AAAA
AAAA
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A
t435
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
TAG[7:0] (from '499)
TAGWE#
DRTY (from '499)
DRTYW#
RDY#
CAS[3:0]#
t434
RASx#
t439
MA[10:0]
DWE#
BOOE#
BEOE#
OCAWE#
ECAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
MIO, DC, WR, A[31..2]
ADS#
CLK2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
Page 56
912-3000-001
82C499
Figure 6-25 Cache Read Miss Not Dirty: 2 banks of cache and 1 DRAM read wait state
t403
t404
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2 T2
t406
t408
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t403
A
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A
t435
t403
t404
T2 T2 T2
t425
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
t408
t407
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t430
t404
t414a
t425
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
T2
t407
AAAA
A
A AAAA
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A
t429
t430
t413a
T2 T2 T2
A
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A
t435
t414a
AAAA
A
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A
A
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A
t430
t429 t429
t413a
t425
T2 T2
t425
AAAA
A
A AAAA
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t435
t414a
A
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T2
AAAA
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A
T2
t413a
A
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A
t430
t435
t414a
T2 T2 T2
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A
t429
t413a
A
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A
t428
t422
t421
t434
t435
T2 T2
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t427
t433
T2 T2
t439
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t425a
t425
t425
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t402 t403
T1 T2 T2
t405
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
t436
t426
t426
t425a
t406
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
TAG[7:0] (from '499)
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
TAGWE#
DRTY (from '499)
DRTYW#
RDY#
CAS[3:0]#
RASx#
MA[10:0]
DWE#
BOOE#
BEOE#
OCAWE#
ECAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
912-3000-001
Page 57
82C499
Figure 6-26 ROM Access Cycle (1 of 2)
t403
t406
t408
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t430
t436
t403
t404
t404
t403
t404
t414a
t407
t408
t407
t425
t425
T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
t429
t430
t413a
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA
A
t430 t429
t436
t414a
t413a
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t414a
t425
t425
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
t413a
t436
AAAA
A
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
t436
t414a
t430
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t429
t434
t439 t436
t413a
AAAA
A
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t422
t421
t428
t427
AAAA
A
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t433
t403
t425
t425
t405
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
TAG[7:0] (from '499)
t436
t402
t426
t426
t406
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA
A
TAGWE#
DRTY (from '499)
RDY#
DRTYW#
CAS[3:0]#
RASx#
MA[10:0]
DWE#
BOOE#
BEOE#
OCAWE#
ECAWE#
BRDY#
BEA2OA3
BEA3
CA32S#
MIO, DC, WR, A[31..2]
ADS#
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
Page 58
912-3000-001
82C499
Figure 6-27 ROM Access Cycle (2 of 2)
T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T
t5
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
t503
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t501 t502
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t524
t521
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
t504
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t523
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t503
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t502
t501
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAA
t524
t521
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t504
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t523
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t503
t502
t521
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t501
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA
AAAA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
RDY#
MEMR#
BALE
XDIR#
SA[1:0]
t442
ROMCS#
MIO, DC, WR, A[31..2]
ADS#
ATCLK
CLKI
CLK2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
912-3000-001
Page 59
82C499
Figure 6-28 DMA Device Read from VESA Slave
t420
t443
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
t524
t419
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
t504
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AA
AAAAAAAA
T2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
t523
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t503
t502
T2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
t501
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
t524
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
t521
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
T2
t504
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
RDY#
MEMR#
BALE
XDIR#
SA[1:0]
ROMCS#
MIO, DC, WR, A[31..2]
ADS#
ATCLK
CLKI
CLK2
T2
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
OPTi
®
Page 60
912-3000-001
82C499
Figure 6-29 DMA Device Write to VESA Slave
t420
t419
t535
t533
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t504
t504
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t215
t216
t543
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t210
t211
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t531
t530
t505
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t542
AAAA
A
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
t505
t534
t532
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
RDY#
LRDY# (from VESA slave)
IOCHRDY
MEMR#
IOW#
EADS#
LDEV#
W/R
M/IO
ADS#
ATCLK
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
OPTi
®
912-3000-001
Page 61
82C499
t420
Figure 6-30 ISA Master Read from VESA Slave
t419
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t504
t504
t535
t533
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t543
t210
t211
t215
t216
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
t530
t531
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
t457
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
t542
t456
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
t505
t534
t532
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t505
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
A
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
A
A AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
RDY#
LRDY# (from VESA slave)
IOCHRDY
MEMW#
IOR#
EADS#
LDEV#
W/R
M/IO
ADS#
ATCLK
CLKI
CLK2
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
Page 62
912-3000-001
82C499
Figure 6-31 ISA Master Write to VESA Slave
t420
t419
t535
t533
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
t504
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t215
t216
t543
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t210
t211
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t531
t530
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
t542
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
t505
t534
t532
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
RDY#
LRDY# (from VESA slave)
IOCHRDY
MEMR#
EADS#
LDEV#
W/R
M/IO
ADS#
ATCLK
CLKI
CLK2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
OPTi
®
912-3000-001
Page 63
82C499
t420
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
t419
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t504
t535
t533
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t543
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t210
t211
t215
t216
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t457
t456
t531
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
t542
t530
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
t505
t534
t532
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
AA
AA AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
RDY#
LRDY# (from VESA slave)
IOCHRDY
MEMW#
EADS#
LDEV#
W/R
M/IO
ADS#
ATCLK
CLKI
CLK2
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
OPTi
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82C499
7.0
Mechnical Package Outline
He
A2
E
A1
c
0.08(0.003) M
e
L
L1
D
Hd
Υ
b
Millimeter
q
Inch
Symbol
Min
Nom
Max
Min
Nom
Max
A1
0.05
0.25
0.50
0.002
0.010
0.020
A2
3.17
3.32
3.47
0.125
0.131
0.137
b
0.10
0.20
0.30
0.004
0.008
0.012
c
0.10
0.15
0.20
0.004
0.006
0.008
D
27.90
28.00
28.10
1.098
1.102
1.106
E
27.90
28.00
28.10
1.098
1.102
1.106
e
0.50
0.020
Hd
30.35
30.60
30.85
1.195
1.205
1.215
He
30.35
30.60
30.85
1.195
1.205
1.215
L
0.35
0.50
0.65
0.014
0.020
0.026
L1
1.30
Υ
θ
0.051
0.08
0
10
0.003
0
10
OPTi
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Page 65
82C499
OPTi
®
Page 66
912-3000-001