ETC 84C30A

Full Duplex
84C30A
4-Port 84C30A
4-Port
Ethernet Controller
96339
Features
Note: Check for latest Data Sheet revision
before starting any designs.
■ Low Power CMOS Technology
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
■ 4-Port Ethernet Controller Optimized for
Switching Hub, Multiport Bridge/Router,
Server Applications
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
■ Meets ANSI/IEEE 802.3 and ISO 8802-3 Standards
for Thicknet (10Base-5), Thin Net (10Base-2)
and Twisted Pair (10Base-T)
■ Standard 10MBit/sec Serial Ethernet
-
Transmit No Preamble Mode
Transmit Packet Autopadding Mode
Receive CRC Mode
Disable Self-Receive on Transmits Mode
Disable Further Transmissions when Both
Transmit Status Registers are Full
- Disable Loading the Transmit Status for
Successfully Transmitted Packets
- Disable the Receive Interrupts Independent
of the Receive Command Register Setting
■ Selectable Little Endian/Big Endian Transmit Byte
Ordering for FIFO Interface for Intel/Motorola
Compatibility
■ Open Bus Interface
■ Programmability of Double Word Threshold
Count for Space Available/Data Available Ready
Condition for Transmit/Receive FIFO’s
■ Auto Retransmit Upon Collision Sense
■ Preamble Generation and Removal
■ Transmit Status on a Per Packet Basis Reports the
Following
- Occurrence of a Transmit FIFO Underflow
- Transmit Collision Occurrence
- 16 Collision Occurrence
- Carrier Sense Error During Transmission
- 10 Mbit/sec Transmit Clock Detect
- Late Collision Occurrence
- Transmission Successful
- Transmission Deferred
■ Automatic 32-Bit FCS (CRC) Generation and
Checking
■ Collision Handling, Transmission Deferral and
Retransmission with Automatic Jam and
Backoff Functions
■ Error Interrupt and Status Generation
■ Single 5 V± 5% Power Supply
■ Standard CPU and Peripheral Interface
Control Signals
■ Each Port Includes the Following Counters or
Status Bits for Network Management Statistics
- 16 Bit Short Receive Frame Counter
- 16 Bit Alignment Error Counter
- 16 Bit CRC Error Counter
- 8 Bit Oversize Receive Frame Counter
- 16 Bit Transmit Collision Counter
- 16 Bit Total Collision Counter
- Transmit Status Bits for “Carrier” and
“SQE” During Transmits
■ Independent 128 Byte Transmit/Receive FIFOs
on each Port
- 1 G Bits/sec (133 M Bytes/sec) Peak Data Rate
in 32 Bit Mode.
■ Loopback Capability for Diagnostics
■ 32 Bit FIFO Data Path
■ Inputs and Outputs TTL Compatible
■ The Following Additional Features can be
Programmed for the 84C30A
- 64 bit Multicast Filter
- Reports Status of “SQE” During Transmits
- Transmit No CRC Mode
■ Full Duplex Operation
- Provides 20 Mbps Bandwidth for Switched
Networks
- Supports AutoDUPLEX Mode for Automatic
Full Duplex Operation
■ 208 Pin PQFP package
4-1
1
MD400151/C
4-Port 84C30A
Table of Contents
1.0 Pin Description
4.0 DC Characteristics
2.0 Introduction
5.0 AC Characteristics
5.01 Command/Status Interface Read Timing
5.02 Command/Status Interface Write Timing
3.0 Functional Description
3.1 Frame Format
6.0 Ethernet Transmit and Receive
Interface Timing
3.2 Packet Transmission per Port
3.2.1 Controlling Transmit Packet
Encapsulation
3.2.2 Transmission Initiation/Deferral
3.2.3 Collision on Transmit
3.2.4 Transmit Termination Conditions
3.2.5 Conditions That Will Cause a Port
TXRET Pin to go HIGH
3.2.6 Detecting and Clearing of a
Transmit Retry Condition
6.01 Ethernet Transmit Interface Timing
6.02 Ethernet Receive Interface Timing
7.0 Transmit Data Interface Timing
7.01 Transmit Data Interface Write Timing 1
7.02 Transmit Data Interface Write Timing 2
8.0 Receive Data Interface Timing
3.3. Packet Reception Per Port
3.3.1 Preamble Processing
3.3.2 Address Matching
3.3.3 Terminating Reception
3.3.4 Using the Rxabort Pins to Terminate
Reception of a Packet
3.3.5 Receive Discard Conditions
8.01 Receive Data Interface Read Timing 1
8.02 Receive Data Interface Read Timing 2
9.0 Transmit Data Interface Timing on
Exception Conditions
10.0 Receive Data Interface Timing on
Exception Conditions
3.4 System Interface
3.5 FIFO Interface
3.5.1 Little and Big Endian Format
3.5.2 Transmit FIFO Interface
3.5.3 Receive FIFO Interface
3.5.4 Special Conditions on
RXRD_TXWR Clock Input
Illustrations
Figure 1. Functional Block Diagram of the 84C30A
3.6 Register Interface
3.6.1 Internal Channel Register Addressing
Table
3.6.2 Station Address Register
3.6.3 Transmit Command Register
3.6.4 Transmit Status Register
3.6.5 Receive Command Register
3.6.6 Receive Status Register
3.6.7 Configuration Registers
3.6.8 FIFO Threshold Register
3.6.8.1 FIFO Threshold Register
Address Settings Table
3.6.9 Defer Register Calculations for the
84C30A
3.6.10 Transmit Control/Product I.D.
Register
Figure 2. 84C30A Pin Configuration
Figure 3. Typical Application Example
3.7 Counters
2
4-2
MD400151/C
4-Port 84C30A
1.0 Pin Description
Pin
Pin Name
I/O
Description
Chip Registers’ Interface
22
ENREGIO
I
This active low input enables the chip for register operations. This input must be
low before any port’s registers can be written or read.
4
W R
I
For a selected port within the chip, this input acts as a write strobe for one of the port’s
registers. The port is selected through the REGPS[1:0] inputs and the register is
addressed through the A[2:0] address inputs. The data being written appears on the
CDST[7:0] data lines and must be set up relative to the rising edge of the write strobe.
This input is active low.
5
RD
I
For a selected port within the chip, this input acts as a read strobe for one of the port’s
registers. The port is selected through the REGPS[1:0] inputs and the register is
addressed through the A[2:0] address inputs. When the read strobe is active low,
the output drivers for CDST[7:0] data bus are enabled. Valid register data appears
on the data bus a specified time before the rising edge of the read strobe.
21, 20
REGPS[1:0]
I
These inputs are used to select which port’s registers are read or written by asserting
the RD or WR read or write strobe inputs. Binary values of 00 through 11 select
channels 1 through 4 respectively with REGPS1 being the MSB of the binary value.
153,
6, 7, 8
A[3:0]
I
These inputs are the address lines used to select which register within a port is being
read or written. A3 has an internal pull down.
CDST[7:0]
I/O
These bidirectional lines carry register data to or from the internal registers of each
port in the chip. These lines are nominally high impedance until their output drivers
are enabled by the RD and ENREGIO input pins being driven low.
7
INT_1
O
This output is driven high by a variety of port #1 transmit and receive interrupt
conditions. It remains high until the port #1 status register containing the reason for
the interrupt is read.
61
INT_2
O
This output is driven high by a variety of port #2 transmit and receive interrupt
conditions. It remains high until the port #2 status register containing the reason for
the interrupt is read.
68
INT_3
O
This output is driven high by a variety of port #3 transmit and receive interrupt
conditions. It remains high until the port #3 status register containing the reason for
the interrupt is read.
77
INT_4
O
This output is driven high by a variety of port #4 transmit and receive interrupt
conditions. It remains high until the port #4 status register containing the reason for
the interrupt is read.
49
RESET
I
This input is an active low chip reset. During reset all registers are reset to zero, all
FIFO’s are cleared, all counters are reset to zero, and all the inputs to the output
drivers for the RXDC and TXRET outputs are driven high.
5-8
9-12
Receive and Transmit FIFO Interface
31
RXINTEN
I
This is an active low input that acts as a chip enable to enable the receiver interface.
Driving this pin active enables the output drivers for the RXDC_1, RXDC_2,
RXDC_3, RXDC_4, RXRDY_1, RXRDY_2, RXRDY_3, and RXRDY_4 pins. Also,
this pin must be driven active before receive FIFO reads can be performed.
32
TXINTEN
I
This is an active low input that acts as a chip enable to enable the transmitter
interface. Driving this pin active enables the output drivers for the TXRET_1,
TXRET_2, TXRET_3, TXRET_4, TXRDY_1, TXRDY_2, TXRDY_3, and TXRDY_4
pins. Also, this pin must be driven active before transmit FIFO writes can be
performed.
4-3
3
MD400151/C
4-Port 84C30A
Pin Description (cont.)
Pin
Pin Name
I/O
Description
36
RXRDEN
I
This is an active low input that, when driven active with the RXINTEN pin, enables
read operations from one of the four receive FIFOs within the chip.
37
TXWREN
I
This is an active low input that, when driven active with the TXINTEN pin, enables
write operations to one of the four transmit FIFOs within the chip.
35
RXRD_TXWR
I
This is the system clock acting as the chip’s read/write strobe to any of the
chips eight receive/transmit FIFO’s. With the TXINTEN and TXWREN inputs active
low, this input becomes the write strobe for writing transmit data to one of the chip’s
transmit FIFOs. Similarly, with the RXINTEN and RXRDEN inputs active low, this
input becomes the read strobe for reading receive data from one of the chips receive
FIFOs. This input must be connected to a continuous clock whose maximum
frequency can be 33 MHz.
30, 29
RXTXPS[1:0]
I
These inputs are used to select a port’s receiver or transmitter for one of the following
operations:
1. Receive FIFO Reads
2. Transmit FIFO Writes
3. Clearing a TXRET Condition
4. Clearing a RXDC Condition
5. Aborting a Receive Packet
23, 24
25, 26
RXTXBE[3:0]
I
These are active low inputs that determine which bytes of the double word for a
receive FIFO read are driven with valid data or which bytes of a double word being
written to a transmit FIFO contain valid data.
44, 57
64, 73
TXRDY_ [1:4]
O
These are active high three state outputs. When enabled, these outputs function as
a flag that indicates whether the associated port’s transmit FIFO has enough space
available to meet the threshold value programmed in the FIFO threshold register.
When enabled, a high value on any of these outputs indicates that the associated
port’s transmit FIFO has greater than or equal to the threshold number of double word
spaces available in the FIFO and a low value indicates it does not. The tristate drivers
for all these outputs are enabled by a low value on the TXINTEN input pin.
42, 56
63, 72
RXRDY_ [1:4]
O
These are active high three state outputs. When enabled, these outputs function as
a flag that indicates whether the associated port’s receive FIFO has enough data
available to meet the threshold value programmed in the FIFO threshold register.
When enabled, a high value on any of these outputs indicates that the associated
port’s receive FIFO has greater than or equal to the threshold number of double
words available in the FIFO or has a completed receive packet in the FIFO as
indicated by the packets status double word being in the FIFO. The tristate drivers
for all these outputs are enabled by a low value on the RXINTEN input pin.
39
SPDTAVL
O
This is an active high output that can be used for validating reads from the receive
FIFO during a read operation and preventing over writes to the transmit FIFO during
a write operation. For further details, please refer to the Transmit Data Write timing
and the Receive Data Read timing diagrams.
40
RXTXEOF
I/O
This is a bidirectional pin that is used to signal the last double word of a transmit or
receive packet. During receive FIFO reads, this pin is enabled as an output and
when detected high indicates that the last double word of a receive packet has been
read from the receive FIFO. During transmit FIFO writes, this pin is an input and when
asserted high during a write it indicates that this is the final double word of a transmit
packet. In the transmit FIFO write case, the value of this signal is stored as the 33rd
bit in the FIFO. In the receive FIFO read case, the value of this signal is read out as
the 33rd bit of the receive FIFO.
4
4-4
MD400151/C
4-Port 84C30A
Pin Description (cont.)
Pin
Pin Name
I/O
41
TXNOCRC
I
This active high input is used to control appending of a CRC to a transmit packet.
A transmit packet can be made to exclude appending a CRC value if this input is held
high during the first double word write of transmit data to the transmit FIFO.
Transmission of all packets without CRC can be done by setting bit #4 of configuration register #1. It should be noted that TXNOCRC pin can be used to control CRC
encapsulation only on a per packet basis.
I/O
This is the bidirectional 32 bit data bus for reads or writes to the chips receive or
transmit FIFO's. For receive FIFO reads it is enabled as an output with the assertion
of the RXINTEN, RXRDEN, and a low value on the RXRD_TXWR input strobe.
Otherwise it is used as an input.
80-84
86-89
91-94
96-101
107-112
115-121
R
X
T
X
D
A
T
A
[
3
1
:
0
]
Description
Transmit and Receive Exception Indicators
48, 62
71, 79
TXRET_ [1:4]
O
These are active high tristate outputs. All four of these output pins are driven by
tristate drivers enabled by an active low being driven onto the TXINTEN input pin.
Once enabled, a high value on any of these inputs indicates that the associated port
could not complete transmission of a packet due to one of the following conditions
and that a retransmission of the packet is requested:
1. A late collision occurred during transmission.
2. Carrier sense never went high or dropped out
during transmission.
3. During a transmission attempt a transmit FIFO underflow error occurred.
4. 16 attempts to transmit the packet all resulting in transmit collisions.
Internally, the TXRET signal will remain high until it is cleared by the CLRTXERR pin,
(See the text on clearing error conditions). As long as the internal TXRET signal for
a port remains high, that port’s transmit FIFO will remain cleared and no new
transmissions can occur.
45, 58
65, 74
RXDC_ [1:4]
O
These are active high tristate outputs. All four of these outputs pins are driven
by tristate drivers enabled by a low value being driven onto the RXINTEN input pin.
Once enabled, a high value on any of these inputs indicates that the associated port’s
discarded reception of a packet due to one of the possible receive discard conditions.
Internally, a port’s RXDC signal will remain high until it is cleared by the CLRRXERR
pin, (See the text on "Receive Discard Conditions"). As long as the internal RXDC
signal for a port remains high, that port’s receive FIFO will remain cleared and no new
packets will be received.
Special Purpose Pins
38
CLRTXERR
I
This active high input is used to clear transmit retry flags within the chip. See the
"Receive Discard Conditions" section for how this input is used.
50
CLRRXERR
I
This active high input is used to clear Receive Discard flags within the chip. See the
"Receive Discard Conditions" section for how this input is used.
46
RXABORT_1
I
This input when pulsed high causes port #1 to abort reception of a receive frame and
clear the Receive FIFO. It can be asserted at any time during the reception of a
frame.
59
RXABORT_2
I
This input when pulsed high causes port #2 to abort reception of a receive frame and
clear the Receive FIFO. It can be asserted at any time during the reception of a
frame.
4-5
5
MD400151/C
4-Port 84C30A
Pin Description (cont.)
Pin
Pin Name
I/O
Description
67
RXABORT_3
I
This input when pulsed high causes port #3 to abort reception of a receive frame and
clear the Receive FIFO. It can be asserted at any time during the reception of a
frame.
75
RXABORT_4
I
This input when pulsed high causes port #4 to abort reception of a receive frame and
clear the Receive FIFO. It can be asserted at any time during the reception of a
frame.
127
ADUPLX_1
I
This active low input is used to set port #1 into Full Duplex Mode. In this mode the
transmitter will not defer to an active carrier sense signal.
125
ADUPLX_2
I
This active low input is used to set port #2 into Full Duplex Mode. In this mode the
transmitter will not defer to an active carrier sense signal.
124
ADUPLX_3
I
This active low input is used to set port #3 into Full Duplex Mode. In this mode the
transmitter will not defer to an active carrier sense signal.
123
ADUPLX_4
I
This active low input is used to set port #4 into Full Duplex Mode. In this mode the
transmitter will not defer to an active carrier sense signal.
Encoder_Decoder Interface
138
TXC_1
I
This is the transmit clock input for port #1. This is a 10 Mhz, 50% duty cycle transmit
clock used to synchronize the transmit data from port #1 to the encoder. Transmit
data appears serially on the TXD0_1 output and all transitions of transmit data and
the TXEN_1 output occur from the falling edge of the clock.
161
TXC_2
I
This is the transmit clock input for port #2. This is a 10 Mhz, 50% duty cycle transmit
clock used to synchronize the transmit data from port #2 to the encoder. Transmit
data appears serially on the TXD0_2 output and all transitions of transmit
data and the TXEN_2 output occur from the falling edge of the clock.
177
TXC_3
I
This is the transmit clock input for port #3. This is a 10 Mhz, 50% duty cycle transmit
clock used to synchronize the transmit data from port #3 to the encoder. Transmit
data appears serially on the TXD0_3 output and all transitions of transmit data and
the TXEN_3 output occur from the falling edge of the clock.
197
TXC_4
I
This is the transmit clock input for port #4. This is a 10 Mhz, 50% duty cycle transmit
clock used to synchronize the transmit data from port #1 to the encoder. Transmit
data appears serially on the TXD0_4 output and all transitions of transmit data and
the TXEN_4 output occur from the falling edge of the clock.
142
TXD_1
O
This input is the serial transmit data output from port #1 to the encoder.
166
TXD_2
O
This input is the serial transmit data output from port #2 to the encoder.
185
TXD _3
O
This input is the serial transmit data output from port #3 to the encoder.
202
TXD_4
O
This input is the serial transmit data output from port #4 to the encoder.
143
TXEN_1
O
This output from port #1 is used to activate the encoder. It becomes active when the
first bit of the Preamble is transmitted and inactive when the last bit of the frame is
transmitted.
6
4-6
MD400151/C
4-Port 84C30A
Pin Description (cont.)
Pin
Pin Name
I/O
167
TXEN_2
O
This output from port #2 is used to activate the encoder. It becomes active when the
first bit of the Preamble is transmitted and inactive when the last bit of the frame is
transmitted.
Description
186
TXEN_3
O
This output from port #3 is used to activate the encoder. It becomes active when the
first bit of the Preamble is transmitted and inactive when the last bit of the frame is
transmitted.
203
TXEN_4
O
This output from port #4 is used to activate the encoder. It becomes active when the
first bit of the Preamble is transmitted and inactive when the last bit of the frame is
transmitted.
128
RXC_1
I
This input is a 10Mhz, 50% duty cycle nominal receive clock which is used to
synchronize incoming data from the decoder to port #1. CSN and RXD0_1 are
assumed to transition from the leading edge of this clock.
146
RXC_2
I
This input is a 10Mhz, 50% duty cycle nominal receive clock which is used to
synchronize incoming data from the decoder to port #2. CSN and RXD0_2 are
assumed to transition from the leading edge of this clock.
169
RXC_3
I
This input is a 10Mhz, 50% duty cycle nominal receive clock which is used to
synchronize incoming data from the decoder to port #3. CSN and RXD0_3 are
assumed to transition from the leading edge of this clock.
188
RXC_4
I
This input is a 10Mhz, 50% duty cycle nominal receive clock which is used to
synchronize incoming data from the decoder to port #4. CSN and RXD0_4 are
assumed to transition from the leading edge of this clock.
137
RXD_1
I
This input is the serial input data to port #1 from the decoder.
160
RXD_2
I
This input is the serial input data to port #2 from the decoder.
175
RXD_3
I
This input is the serial input data to port #3 from the decoder.
196
RXD_4
I
This input is the serial input data to port #4 from the decoder.
130
CSN_1
I
This is port #1's carrier sense input which indicates there is traffic on the transmission
medium connected to port #1. Carrier sense becomes active with the first bit of the
Preamble received, and inactive one bit time after the last bit of the frame is received.
This is an active high input.
148
CSN_2
I
This is port #2's carrier sense input which indicates there is traffic on the transmission
medium connected to port #2. Carrier sense becomes active with the first bit of the
Preamble received, and inactive one bit time after the last bit of the frame is received.
This is an active high input.
171
CSN_3
I
This is port #3's carrier sense input which indicates there is traffic on the transmission
medium connected to port #3. Carrier sense becomes active with the first bit of the
Preamble received, and inactive one bit time after the last bit of the frame is received.
This is an active high input.
191
CSN_4
I
This is port #4's carrier sense input which indicates there is traffic on the transmission
medium connected to port #4. Carrier sense becomes active with the first bit of the
Preamble received, and inactive one bit time after the last bit of the frame is received.
This is an active high input.
4-7
7
MD400151/C
4-Port 84C30A
Pin Description (cont.)
Pin
Pin Name
I/O
Description
145
COLL_1
I
This input indicates that a transmission contention has occurred on the transmission
medium connected to port #1. The collision input is latched internally. Sampled
during transmission, Collision is set by an active high pulse on the COLL input and
automatically reset at the end of transmission of the JAM sequence.
168
COLL_2
I
This input indicates that a transmission contention has occurred on the transmission
medium connected to port #2. The collision input is latched internally. Sampled
during transmission, Collision is set by an active high pulse on the COLL input and
automatically reset at the end of transmission of the JAM sequence.
187
COLL_3
I
This input indicates that a transmission contention has occurred on the transmission
medium connected to port #3. The collision input is latched internally. Sampled
during transmission, Collision is set by an active high pulse on the COLL input and
automatically reset at the end of transmission of the JAM sequence.
204
COLL_4
I
This input indicates that a transmission contention has occurred on the transmission
medium connected to port #4. The collision input is latched internally. Sampled
during transmission, Collision is set by an active high pulse on the COLL input and
automatically reset at the end of transmission of the JAM sequence.
205
DAISY_OUT
O
This output is used for parametric test of the I/O’s only. It should not be externally
connected.
8
4-8
MD400151/C
4-Port 84C30A
Pin Description (cont.)
Pin
Pin Name
I/O
Description
2, 14, 28, 33,
52, 53, 70,
78, 102, 104,
114, 126, 132,
135, 154, 157,
158, 178, 183,
189, 193
VDD
—
Power Supply 5V +/– 5%
1, 3, 13
19, 27, 34,
43, 51, 54,
55, 60, 66,
69, 76, 85,
90, 95, 103,
105, 106, 113,
122, 129, 131,
133, 134, 136
144, 147, 149
150, 151, 155,
156, 159,
165, 170, 172,
173, 174, 176,
179, 184, 190,
192, 194, 195,
200, 207, 208
GND
—
Ground 0 Volts
139, 140, 141
152, 153
162, 163, 164
180, 181, 182
198, 199, 201
206
Do Not
Connect
—
DO NOT CONNECT or run traces under these pins.
Note: All inputs with the exception of the “Do Not Connect” pins, must never be left floating even if they are not in use. Each
pin must be driven either HIGH or LOW.
4-9
9
MD400151/C
MD400151/C
PARALLEL
/SERIAL
CRC/DATA SELECT
RXNOCRC
CONTROL
REGISTER
FILE
CRC
GENERATOR
INTERRUPT
AND
CONTROL
REGISTER
INTERFACE
& TRI-STATE
LOGIC
M
U
X
TXDO
INTn
CDST [7:0]
WR
RD
REGPS [1:0]
A [3:0]
4-Port 84C30A
10
4-10
#208
DO NOT CONNECT
TXEN_4
TXD_4
DO NOT CONNECT
DAISY_OUT
COLL_4
GND
DO NOT CONNECT
#200-
-#1
V DD
GND
DO NOT CONNECT
GND
GND
GND
4-Port 84C30A
WR
RD
A2
A1
A0
CDST7
CDST6
-#10
CDST5
CDST4
GND
VD
GND
REGPS0
RXTXBE3
84C30A
84C30
(208
PQFP)
(208 PQFP)
RXTXBE2
RXTXBE0
GND
VD
TXINTEN
ADUPLX_2
ADUPLX_3
GND
ADUPLX_4
RXRDEN
TXWREN
VD
TXRET_1
GND
Figure 2. 84C30A Pin Configuration
4-11
11
MD400151/C
4-Port 84C30A
2.0 Introduction
The 84C30A is a 4-Port Ethernet Media Access Controller
(MAC) with a rich set of operating modes and features. It
will directly connect with SEEQ’s 84C24 (4-Port 10Base-T
PHY) or four SEEQ 80C25’s (single-channel 10Base-T
PHY). It is manufactured as a single-chip VLSI device to
simplify and enhance the development of multi-port
Ethernet embedded systems such as bridges, switches,
and routers.
(FCS). Each field has a specific format which is described
in detail below. An Ethernet frame has a minimum length
of 64 bytes and a maximum length of 1518 bytes exclusive
of the preamble. The Ethernet frame format is shown in the
figure above.
FIRST BYTE
Each port of the 84C30A is feature compatible with
SEEQ’s 80C03 Ethernet Media Access Controller. These
features include: 64 bit Multicast filter, Transmit no CRC,
Transmit no Preamble, Transmit Packet Autopadding,
Receive CRC, Receive Own Transmit Disable, Receive
Group Address Mode, Fast Receive Discard Mode, and
Full Duplex Mode. Additionally, each port supports: programmable defer time between transmit packets, appending value of FCS on a packet-by-packet basis, and pincontrollable per-port receive packet abort.
A high-bandwidth universal system interface is provided
which is compatible with many microprocessor or system
busses, easing the integration of the 84C30A into many
system architectures. Its 32-bit data path width is provided
to provide the bandwidth necessary to maintain full duplex
wire speed communications simultaneously through all
four ports. Each port is provided with dual 128 byte FIFOs
to ease bus multiplexing and interfacing to different clock
domains.
......
......
A15 . . . . . .
......
A23 . . . . . .
......
A31
......
A39 . . . . . .
......
A47 . . . . . .
......
B7 . . . . . .
......
B15 . . . . . .
......
B23
A7
A0
A8
A16
A24
DESTINATION
ADDRESS
(6 BYTES)
A32
A40
B0
B8
B16
B31
B24
B39
B32
B47
B40
T7
T0
T15
T8
D7
D0
SOURCE
ADDRESS
(6 BYTES)
BYTE COUNT
(2 BYTES)
DATA
(46 – 1500
BYTES)
LAST BYTE
Typical Frame Buffer Format for
Byte-Organized Memory
3.0 Functional Description
3.1 FRAME FORMAT
Preamble: The preamble is a 64-bit field consisting of 62
alternating “1”s and “0”s followed by a “11” End-of-Preamble indicator.
ETHERNET FRAME
PREAMBLE
(8)
DESTINATION
ADDRESS
(6)
SOURCE
ADDRESS
BYTE
(6)
COUNT
(2)
DATA
(46-1500)
Destination Address: The Destination Address is a 6byte field containing either a specific Station Address, a
Broadcast Address, or a Multicast Address to which this
frame is directed.
FCS
(4)
NOTE:
Field length bytes, in parentheses.
Source Address: The Source Address is a 6-byte field
containing the specific Station Address from which this
frame originated.
On an Ethernet communication network, information is
transmitted and received in packets or frames. An Ethernet frame consists of a preamble, two address fields, a
byte-count field, a data field and a frame check sequence
Byte-Count Field: The Byte-Count Field consists of two
bytes providing the number of valid data bytes in the Data
Field, 46 to 1500. This field is uninterpreted at the Data
Link Layer, and is passed through the EDLC chip to be
handled at the Client Layer.
12
4-12
MD400151/C
4-Port 84C30A
Data Field: The Data Field consists of 46 to 1500 bytes of
information which are fully transparent in the sense that
any arbitrary sequence of bytes may occur.
3.2.2 Transmission Initiation/Deferral
A transmission is initiated any time a double word of data
is written to the transmit FIFO. “Transmit buffer to FIFO”
transfers are coordinated via the Transmit FIFO Interface.
When the chip is not in Full Duplex mode, actual transmission of the data onto the network will only occur if the FIFO
has at least one double word of data to transmit, the
network has not been busy for the minimum defer time,
and any Backoff time requirements have been satisfied.
Following the IEEE 802.3 specifications, the minimum
defer time is measured from carrier sense going LOW to
TXEN going HIGH. The default defer time for 10Mbit/sec
serial mode is 9.6 µs as measured from TXEN going LOW
to TXEN going HIGH assuming that the delay from TXEN
going LOW to CSN going LOW is within 5 TXC clock
periods. When the chip is in full duplex mode, transmission
of data onto the network occurs independent of whether
carrier sense indicates a busy network condition or not. To
adjust the defer time to some other value, the programmable defer register can be set using the formulas given in
the section describing the defer register. When transmission begins, the chip activates the transmit enable (TXEN)
line concurrently with the transmission of the first bit, of the
Preamble and keeps it active for the duration of the
transmission.
Frame Check Sequence: The Frame Check Sequence
(FCS) field is a 32-bit cyclic redundancy check (CRC)
value computed as a function of the Destination Address
Field, Source Address Field, Type Field and Data Field.
The FCS is appended to each transmitted frame, and used
at reception to determine if the received frame is valid.
3.2 PACKET TRANSMISSION PER PORT
The transmit data stream consists of the Preamble, four
information fields, and the FCS which is computed in real
time by the port and automatically appended to the frame
at the end of the data. The Preamble is also generated by
the port and transmitted immediately prior to the Destination Address. Destination Address, Source Address, Type
Field and Data Field are prepared in the buffer memory
prior to initiating transmission. The port encapsulates
these fields into an Ethernet frame by inserting a preamble
prior to these information fields and appending a CRC after
the information fields. A port can be programmed to
exclude inclusion of the preamble and/or the FCS from the
transmit data stream. In this case it is assumed that the
preamble and FCS are provided as part of the data written
to the port.
3.2.3 Collision on Transmit
On the occurrence of a transmit collision condition that
does not represent the 16th transmission attempt for the
packet or does not occur after 64 byte times into the
transmission, the controller will automatically attempt to
retransmit the packet. First, the controller will halt the
transmission of data from the FIFO and begin transmitting
a Jam pattern consisting of 55555555 hex. The controller
will also reset the Transmit FIFO read address pointer
back to the beginning of the transmit packet within the
FIFO. At the end of transmitting the Jam pattern the
controller will then begin the Backoff wait period. Once the
backoff period is finished the controller will automatically
retransmit the packet. If a packet reaches 16 retransmission attempts without success due to collisions, or if a
collision occurs later than 64 Byte times after the beginning
of a transmission, this is considered to represent a serious
network error. Upon any one of these two error conditions
occurring, the selected port’s Transmit FIFO will be
cleared and the corresponding TXRET output will be
driven HIGH. If the TXRET signal was driven HIGH due to
16 transmission attempts, the T16COLL signal will also be
driven HIGH. When either of the two above error conditions occurs, retransmission of any packets that were in
the transmit FIFO requires first clearing the TXRET error
condition and then reloading the packet or packets in the
Transmit FIFO.
3.2.1 Controlling Transmit Packet Encapsulation
As was mentioned in the previous paragraph, a port can be
programmed for exclusion of the FCS and/or the preamble
when transmitting a packet. To program a port for transmitting a packet without creating a preamble, bit #2 of the
port’s Configuration Register #1 can be written high. Once
this bit is set, all packets transmitted by the port will not
include a preamble pattern unless it is part of the data
written to the port’s transmit FIFO by the system. Similarly,
a port can be prevented from appending an FCS value to
a packet by setting bit #4 HIGH in the Configuration
Register #1. As long as this bit is high, any packet
transmitted by the port will not include an FCS value unless
it is written as part of the transmit data written to the port's
transmit FIFO. Appending of a FCS value can be controlled on a packet per packet basis by using the
TXNOCRC pin as long as the TXNOCRC Tx-Rx Configuration register bit has not been set high. If the TXNOCRC
pin is held high when the first byte of data is written to a
port's transmit FIFO, this will prevent the port from appending a FCS value to the packet. Only those packets for
which the TXNOCRC pin is held high during the first data
write will not have an FCS value appended by the port
during transmission.
4-13
13
MD400151/C
4-Port 84C30A
Scheduling of retransmission is determined by a controlled randomization process called Truncated Binary
Exponential Backoff. The chip waits a random interval
between 0 and 2 K slot times (51.2 µ s per slot time) before
attempting retransmission, where “K” is the current transmission attempt number (not to exceed 10).
Register. Dependent upon the bits enabled in the Transmit Command Register, an interrupt will be generated for
the just completed transmission.
3.2.5 Conditions That Will Cause a Port’s TXRET Pin
to go High
Detection of a HIGH value on one of the chips 4 TXRET
pins indicates that the associated port could not complete
transmission of a packet due to one or more of the
following conditions:
3.2.4 Transmit Termination Conditions
A port will terminate transmission under the following
conditions.
1. A transmit FIFO underflow occurred while
transmitting the packet.
Normal: The frame has been transmitted successfully
without contention. Loading of the last data byte into a
port’s Transmit FIFO is signaled to the port by activation of
its RxTxEOF signal concurrently with the last double word
of data loaded into the Transmit FIFO. This line acts as a
thirty-third bit in the Transmit FIFO. When the last valid
byte of the last double word has been transmitted, if the
port is not in Transmit No CRC mode, then the CRC is
appended and transmitted concluding frame transmission. The Transmission Successful bit of the Transmit
Status Register will be set by a normal termination.
2. A late collision occurred while transmitting
the packet.
3. Carrier sense never went active during
transmission or went from an active to inactive
state during transmission.
4. 16 attempts to transmit the packet all resulted in
transmit collisions.
Any of the above conditions will cause the port to flush the
transmit FIFO and initiate a transmit retry request. With
initiation of a transmit Retry Request the port’s TXRDY
output will go low and stay low until the TXRET flag is
cleared. Similar to a port's receive discard signal, a
transmit retry signal going to the external TXRET pin is
latched upon a transmit retry condition and held high until
cleared. Until a port's transmit retry signal is cleared, no
new transmit packets can be written to the transmit FIFO.
Collision: Transmission attempted by two or more Ethernet nodes. The Jam sequence is transmitted, the Collision status bit is set, transmit Collision Counter is updated,
the Backoff interval begun, and the Transmit FIFO address
is set to point to the beginning of the packet for retransmission.
Underflow: Transmit data is not ready when needed for
transmission. Once transmission has begun, a port on
average requires one transmit double word every 3200 ns
in order to avoid Transmit FIFO underflow (starvation). If
this condition occurs, the port terminates the transmission,
issues a TXRET signal, and sets the Transmit-Underflow
status bit.
3.2.6 Detecting and Clearing a Transmit Retry
Condition
To enable the output drivers for the four TXRET pins, the
the TXINTEN input is driven low. Once a Tx retry condition
is detected, that port's internal Tx retry signal can be
cleared by first setting the RXTXPS[1:0] inputs to point to
that port. Then by driving the TXINTEN input low and then
pulsing the CLRTXERR input high for a minimum of one
RXRD_TXWR clock cycle, this will clear that port's TXRET
signal. The RXTXPS [1:0] and TXINTEN inputs must not
change during the high time of the CLRTXERR input.
16 Transmission Attempts: If a Collision occurs for the
sixteenth consecutive time, the 16-Transmission-Attempts status bit is set, the Collision status bit is set, the
TXRET signal is generated, and the Backoff interval begun. The counter that keeps track of the number of
collisions is modulo 16 and therefore rolls over on the 17th
collision. Bits 15 to 11 of a port’s transmit collision counter
allow a user to determine how many transmission attempts
were necessary to successfully transmit the packet.
3.3 Packet Reception Per Port
Each port within the chip continuously monitors the network. When activity is recognized via the Carrier Sense
(CSN) signal, the port will then synchronize itself to the
incoming data stream through recognition of the Start
Frame Delimiter (SFD) at the end of Preamble. The
destination address field of the frame is then examined.
Depending on the Address Match Mode specified, the port
will either recognize the frame as being addressed to itself
in a general or specific fashion or abort the frame reception. The port can also be programmed to count all collisions on the network it's connected to.
Late Collision: If a Collision occurs greater than 64 byte
times after the transmission begins this is considered a
late collision error. Upon this condition the transmission is
terminated, the TXRET output is driven HIGH, and the late
collision status bit is set.
At the completion of every transmission or retransmission,
new status information is loaded into the Transmit Status
14
4-14
MD400151/C
4-Port 84C30A
TRANSMIT
RECEIVE
DATA
BUFFER
DMA/
BUFFER
CONTROL
BUS
TRANSCEIVER
84C30A
4 CHANNEL
QUAD
CPU
84C24
4 CHANNEL
10BASE-T
SYSTEM
MEMORY
Figure 3. Typical Application Example
3.3.2 Address Matching
Ethernet addresses consist of two 6-byte fields. The first
bit of the address signifies whether it is a Station Address
or a Multicast/Broadcast Address.
3.3.1 Preamble Processing
A port recognizes activity on the Ethernet via its Carrier
Sense line. The end of preamble is detected by a double
1 serial receive data pattern preceded by 6 bits of alternating 1’s and 0’s.
First Bit
Detection of a double 0 pattern 16 bit times after CSN goes
high and before a proper Start Frame Delimiter pattern is
received, will prevent reception of the packet by the
receiver.
0
1
Address
Station Address (Physical)
Multicast/Broadcast Address
(logical)
Address matching occurs as follows:
Station Address: All destination address bytes must
match the corresponding bytes found in the Station Address Register. If Group Address mode is enabled, the last
4 bits of the station address are masked out during address
matching.
4-15
15
MD400151/C
4-Port 84C30A
After computing the FCS on the first six bytes of the
address field (Destination address), a port uses bits 0 thru
5 as an address to its Multi-cast address filter register. Bit
0 of the FCS is assumed to be where receive data enters
the FCS generation circuitry. If the corresponding bit
addressed in the Multicast address filter register is a ‘1’ the
port will receive the frame, otherwise it will discard the
frame. Addressing of the Multicast address filter register
occurs using bits 0 thru 2 to determine which byte is
selected and bits 3 thru 5 to determine which bit according
to the following tables:
FCS Bits
0 1 2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Byte Selected
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
FCS Bits
3 4 5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3.3.3 Terminating Reception
Reception is terminated when either of the following conditions occur:
Carrier Sense or Receive Data Valid Inactive: Indicates
that traffic is no longer present on the Ethernet cable.
Overflow: The host node for some reason is not able to
empty a port Receive FIFO as rapidly as it is filled, and an
error occurs as frame data is lost. On average a port’s
Receive FIFO must be serviced every 3200 ns to avoid this
condition.
Bit Selected
3.3.4 Using the RXABORT Pins to Terminate
Reception of a Packet
By pulsing the corresponding RXABORT pin high for a
minimum of 1.5 RXC cycles, reception of a packet by a port
can be terminated. When reception of a packet is terminated this way, the Receive FIFO will be cleared and will
stay cleared until carrier sense transitions from high to low
or from low to high indicating either the end of the packet
being aborted or the beginning of a new receive packet. It
is important to note that RXABORT will cause the RXDC
pin to go high based on the conditions described under
“Conditions that cause the RXDC pin to go high”.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Multicast Address: If the first bit of the incoming address
is a 1 and the port is programmed to accept Multicast
Addresses without using Hash filtering, the frame is received. A port also can be programmed to use the hash
filter for determining acceptance of multicast addresses.
The assertion of RXDC is done so that an external processor will always have an indication of a packet abortion
irrespective of whether it’s aborted by the user or by an
external PHY. However, the assertion of the RXDC signal
can be avoided by setting bit 4 of configuration register #2.
This will enable the reception of any packet irrespective of
errors and also reduce the number of signals (RXDC1_4
and CLRRXERR) that need to be processed when the
corresponding RXABORT goes high.
Broadcast Address: The six incoming destination address bytes must all be FF hex. If a port is programmed to
accept Broadcast or Multicast Addresses the frame will be
received.
3.3.5 Receive Discard Conditions
Receive packets can be discarded for not meeting the
minimum IEEE 802.3 requirements for a good packet, for
address mismatches when the chip is not in promiscuous
mode, and by user intervention. In the case of discards
due to oversized packets, address mismatches, or the
assertion of the RXABORT pin during packet reception,
further writing of receive packet data to the receive FIFO
is halted once the mismatch, receive abort or oversized
packet condition is determined.
If the incoming frame is addressed to a port in the chip
specifically (Destination Address matches the contents of
the Station Address Register), or is of general or group
interest (Broadcast or Multicast Address), the port will
pass the frame exclusive of Preamble and FCS to the CPU
buffer and indicate any error conditions at the end of the
frame. If, however, the address does not match, as soon
as the mismatch is recognized, the port will terminate
reception and issue an RxDC.
A port may be programmed via the Match Mode bits of the
Receive Command Register to ignore all frames (Disable
Receiver), accept all frames (Promiscuous mode), accept
frames with the proper Station Address or the Broadcast
Address (Station/Broadcast), or accept all frames with the
proper Station Address, the Broadcast Address, or all
Multicast Addresses (Station/Broadcast/Multicast).
Except for discards due to address mismatches and oversized packets, all packet discards occur after carrier sense
deasserts. The discarding of receive packets for error
conditions can be controlled through bits 0 through 3 of the
receive command register, and through bit 4 of configura-
16
4-16
MD400151/C
4-Port 84C30A
3.6.1 Internal Port Register Addressing Table
Transmit
Command
Register Register
Bits
Address
Register Description
6
5
A3
A2 A1
A0
Read
0
0
0
0
0
0
Station Address 0
Station Address 0
0
0
0
0
0
1
Station Address 1
Station Address 1
0
0
0
0
1
0
Station Address 2
Station Address 2
0
0
0
0
1
1
Station Address 3
Station Address 3
0
0
0
1
0
0
Station Address 4
Station Address 4
0
0
0
1
0
1
Station Address 5
Station Address 5
X
X
0
1
1
0
Rx Status Register
Rx Command Register
X
X
0
1
1
1
Tx Status Register
Tx Command Register
0
1
0
0
0
0
Hash Register 0
Hash Register 0
0
1
0
0
0
1
Hash Register 1
Hash Register 1
0
1
0
0
1
0
Hash Register 2
Hash Register 2
0
1
0
0
1
1
Hash Register 3
Hash Register 3
0
1
0
1
0
0
Hash Register 4
Hash Register 4
0
1
0
1
0
1
Hash Register 5
Hash Register 5
1
0
0
0
0
0
Hash Register 6
Hash Register 6
1
0
0
0
0
1
Hash Register 7
Hash Register 7
1
0
0
0
1
0
FIFO Threshold Register
FIFO Threshold Register
1
0
0
0
1
1
Configuration Register #2
Configuration Register #2
1
0
0
1
0
0
Configuration Register #1
Configuration Register #1
1
0
0
1
0
1
Defer Count Register
Defer Count Register
1
1
0
0
0
0
CRC Error Counter
—
1
1
0
0
0
1
Short Frame Counter
—
1
1
0
0
1
0
Oversize Frame Counter
—
1
1
0
0
1
1
Alignment Error Counter
—
1
1
0
1
0
0
Transmit Collision Counter
—
1
1
0
1
0
1
Receive Collision Counter
—
X
X
1
0
0
0
Transmit Control/Product
Transmit Control/Product*
I.D. Register
I.D. Register
*The upper four bits are read only.
4-17
17
MD400151/C
Write
4-Port 84C30A
tion register #2. Listed below are the required conditions
for a receive discard to be produced:
2. If there are no status double words in the receive
FIFO and if RXRDY goes HIGH just before a discard
condition occurs, RXRDY may go LOW again before
any FIFO reads have occurred. This is due to the
receive discard clearing the FIFO of any receive
bytes already written to the FIFO. In this case,
RXRDY is guaranteed to remain HIGH for at least
one RXRD_TXWR clock cycle.
1. Bit 0 of the Rx command register is LOW and a
receive FIFO overflow occurred during reception.
2. Bit 1 of the Rx command register is LOW and a
packet with a CRC error was received.
3. Bit 4 of Configuration register 2 is LOW and the
RXABORT pin is driven high while CSN is high.
Detecting and Clearing a Receive Discard Condition
To enable the output driver for the RXDC pins, the
RXINTEN input must be driven low. Once a discard
condition is detected, the receive discard can be cleared
by driving the RXINTEN input low and then pulsing the
CLRRXERR input high for a minimum of one
RXRD_TXWR clock cycle. The RXINTEN input must not
change state for the duration of the time that the
CLRRXERR input is high.
4. Bit 3 of the Rx command register is LOW and a packet
with less than 64 bytes of data was received.
5. Bit 4 of the Rx command register is LOW and a
packet of size greater than 1518 was received.
6. The Receiver is not in promiscuous mode and a
address mismatch occurs.
Discarding of a receive packet by a port will cause any
packet data that was written to that receive FIFO to be
flushed from the FIFO. If no completely received packets
are in the receive FIFO at the time a receive discard
occurs, the receive FIFO will be completely flushed of
data. If however, a completely received packet, as indicated by the packet’s status double word having been
written to the FIFO, is in the receive FIFO at the time of a
receive discard, the FIFO will be flushed only up to the last
completely received packet. To prevent a receive packet
from being discarded due to an error condition, you can
selectively enable the reception of errored packets as
described in the section describing bit settings on configuration register #2.
Clearing Interrupts
Within one port, both receive and transmit interrupts are
combined into a single interrupt signal which then goes to
the INT output pin. The interrupt signal in the chip is
actually the result of the receive/transmit status register
outputs and the receive/transmit command register interrupt enable bits that are set. To clear an interrupt, the
status that caused the interrupt needs to be cleared. This
can be accomplished by reading the transmit status register and/or the receive status register.
3.4 SYSTEM INTERFACE
The chip system interface consists of one receive/transmit
32-bit bidirectional data bus, one 8-bit bidirectional command/status data bus, and each busses respective control
signals. Receive FIFO data is read and Transmit FIFO
data is written over the RXTXDATA[31:0] bus, and Command/Status data is written or read over the bidirectional
CDST[7:0] data bus.
Conditions that Cause the RXDC Pin to go HIGH
As packets are discarded due to the receive packet error
conditions given in the section “Description of How Receive Packets are Discarded”, the corresponding port’s
RXDC pin may or may not assert. If a receive packet’s
status has been written to the receive FIFO and the
packet’s status has not yet been read from the FIFO,
discards caused by following packets with errors are
handled within the chip and the RXDC pin will not go HIGH.
If all status double words for all packets written to the FIFO
have been read out, then the RXDC pin will go HIGH under
the following condition:
1. Enough of a receive packet has been written to the
FIFO to cause RXRDY to go HIGH before the packet
is discarded due to an error condition.
18
4-18
MD400151/C
4-Port 84C30A
3.5 FIFO INTERFACE
3.5.1 Little Endian and Big Endian Format
The FIFO interface control includes the BUSMODE bit 6 in
configuration register #2, which sets the 84C30A FIFO
interface to Big Endian or Little Endian byte transmit/
receive data order. In Big Endian mode, data written to the
transmit FIFO is transmitted most significant byte of the
RXTXDATA bus first and least significant byte of the
RXTXDATA bus last. In Little Endian mode, the least
significant byte of each double word is transmitted first and
the most significant byte of each double word is transmitted last. On the receive side, if Big Endian mode is in effect
then the first data bytes received are assumed to be the
most significant bytes of the double word and appear on
the most significant portion of the RXTXDATA bus for
receive FIFO reads. The receiver reverses this order if the
chip is in Little Endian mode. The value of the BUSMODE
bit has no effect on the operation of the 84C30A’s register
interface.
RXTXDATA0
Once one of the TXRDY outputs is determined to be high,
that port’s Transmit FIFO can be written. To write to a
port’s Transmit FIFO, the TXWREN and TXINTEN inputs
must be asserted low and at least one of the RXTXBE byte
enables must be low for each write cycle. The value of the
RXTXPS inputs determines which port is being written. All
of the above inputs are clocked into the chip on the high
going edge of the RXRD_TXWR clock input which also
acts as the FIFO write strobe. Because of this pipe lining
RXTXDATA24
..
.
..
.
RXTXDATA7
PREAMBLE
3.5.2 Transmit FIFO Interface
To determine if the transmit FIFO for any of the chip’s ports
has reached its threshold number of double words of
space available, all four TXRDY outputs can be enabled by
driving the TXINTEN input low. The TXRDY output for a
port will be high if there is enough space available in the
port's transmit FIFO to meet or exceed the programmed
threshold value.
RXTXDATA31
1ST BYTE
2ND BYTE
A0 . . . A7
A8 . . . A15
3RD BYTE
A16 . . . A23
RXTXDATA0
..
.
RXTXDATA7
4TH BYTE
5TH BYTE
6TH BYTE
A24 . . . A31
A32 . . . A39
A40 . . . A47
SOURCE ADDRESS . . .
DESTINATION ADDRESS
BITS WITHIN A DOUBLE WORD TRANSMITTED/RECEIVED BIT NO.“0” FIRST THROUGH BIT NO. “31” LAST.
Bit Serialization/Deserialization for Little Endian Format
RXTXDATA24
RXTXDATA0
..
.
..
.
RXTXDATA31
PREAMBLE
1ST BYTE
2ND BYTE
A0 . . . A7
A8 . . . A15
RXTXDATA7
3RD BYTE
A16 . . . A23
4TH BYTE
A24 . . . A31
RXTXDATA24
..
.
RXTXDATA31
5TH BYTE
6TH BYTE
A32 . . . A39
A40 . . . A47
DESTINATION ADDRESS
Bit Serialization/Deserialization for Big Endian Format
4-19
19
MD400151/C
SOURCE ADDRESS . . .
4-Port 84C30A
the actual FIFO write will occur one RXRD_TXWR cycle
after the assertion of the Transmit FIFO interface control
signals. Valid combinations of the RXTXBE inputs for
transmit FIFO writes are given below:
2. The number of bytes taken out of the transmit FIFO
for transmission subtracted from the number of bytes
written to the FIFO leaves the FIFO with enough double
word space available to meet the threshold setting.
It is important to note that until the packet is completely
transmitted or until enough of the packet is transmitted to
get past the normal collision window, the TXRDY output
will only reflect how many writes have occurred and will not
reflect how much of the FIFO data has been read out for
transmission. Because of this, it is important to insure
enough packet data has been written to prevent FIFO
underflows if there exists a large latency between the
TXRDY output being determined HIGH and the writing of
more data to the FIFO.
RXTXBE3 RXTXBE2 RXTXBE1 RXTXBE0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
1
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
3.5.3 Receive FIFO Interface
To determine if the receive FIFO has reached its threshold
number of double words of data, the RXRDY output can be
enabled by driving the RXINTEN input low. The RXRDY
output for the chip will be high under one of the following
conditions:
The TXRDY output for the port being read will remain high
until the port's transmit FIFO no longer has enough double
word space to meet the programmed threshold value.
1. There are enough double words of data in the
channel's receive FIFO to meet or exceed the
programmed threshold value.
While transmit FIFO writes are occurring the SPDTAVL
output will remain high until the highgoing edge of the write
to the second to the last remaining double word space in
the FIFO. Because transmit FIFO writes are pipelined,
there will always be one more write after TXWREN is
deasserted.
2. The status double word for a receive packet with
an end of frame value of HIGH is in the receive FIFO.
Once the RXRDY output is determined to be high, the
receive FIFO can be read. To read from the Receive FIFO,
the RXRDEN and RXINTEN inputs must be asserted low
and the RXTXBE byte enables must be low for each read
cycle. Similar to the Transmit FIFO interface, all of the
above Receive FIFO interface control signals are clocked
into the chip on the high going edge of the RXRD_TXWR
clock input which also acts as the FIFO read strobe.
Because of this pipe lining the actual FIFO read will occur
one RXRD_TXWR cycle after the assertion of the Receive
FIFO interface control signals.
Using the 84C30A in 8 bit or 16 bit mode.
The transmit and the receive FIFO are 128 bytes deep
organized as double word (32 bits) rows. During writes to
the transmit FIFO, the FIFO pointer gets incremented on
every write to the FIFO, irrespective of whether all the four
byte enables are asserted or not. Hence, during non
double word writes to the FIFO, one entire row of the FIFO
gets filled irrespective of whether all the bytes are valid or
not. The 84C30A automatically ignores the invalid bytes
when the data gets transmitted from the FIFO.
Using the 84C30A in 8 Bit or 16 Bit Mode
Effect of Auto Retransmission Upon TXRDY Behavior
As a packet is read out of a port’s Transmit FIFO by the
transmitter for transmission onto the network, the corresponding TXRDY signal will not reflect any reads that have
occurred to the FIFO until enough bytes of data have been
transmitted to get past the normal collision window of less
than 64 byte times. This means that if a port’s TXRDY
goes low during the writing of a packet to the Transmit
FIFO, it will not go HIGH again until both of the following
conditions are true:
On the receive side, two different modes are possible.
On burst reads (Rxrden being asserted for multiple clock
cycles), if the first read is not a double word read, the
second read will always increment the FIFO pointer irrespective of whether all the byte enables are enabled or not.
In this mode, 16 bit reads are possible by muxing the LSB
and the MSB of the data bus. 8 bit reads are not possible.
On single reads (Rxrden being asserted for only one clock
cycle), the FIFO pointer will get incremented only on a
double word read. In this mode, the different bytes of the
1. The packet has been completely transmitted or to a
point 64 byte times from the beginning of the transmission has been reached.
20
4-20
MD400151/C
4-Port 84C30A
data bus can be muxed to perform multiple 8 bit or 16 bit
reads. But, all the reads of the bytes belonging to one row
should be terminated with a double word read to increment
the FIFO pointer.
The ENREGIO signal is used as a general register interface enable and must be active low before any register
operations can occur. The REGPS signals are used to
select which port’s registers are to be accessed. The
A[2:0] are used to address which register within a port is
being accessed. Initiation of a register read is controlled by
the RD signal and initiation of a register write is controlled
by the WR signal. A port’s registers may be accessed at
any time. However, it is recommended that writing to the
command register, be done only during interframe gaps.
When the chip is being read, the RXRDY output will remain
high until the high going edge of the read that results in one
of the following conditions:
1. The FIFO no longer has enough data to meet the
threshold setting.
2. A packet’s status double word with its associated
HIGH end of frame value is read out.
With the exception of the two Match Mode bits in the
Receive Command Register, all bits in both command
registers are interrupt enable bits. Changing the interrupt
enable bits during frame transmission does not affect the
frame integrity. Asynchronous error events, however,
e.g., overflow, underflow, etc., may cause chip operation
to vary, if their corresponding enable bits are being altered
at the same time.
In the case of RXRDY being driven LOW upon condition
two given above, it will remain LOW for 8 RXRD_TXWR
clock cycles and then goes back HIGH if one of the
conditions for RXRDY being HIGH is met.
During reads from the FIFO, the SPDTAVL output will
remain high until the high going edge of the read that
causes one of the following conditions to occur:
Reading the status registers may also occur at any time
during transmission or reception.
1. The read that empties the FIFO completely.
Status Registers and all management counters are read
only registers. The Rx and Tx Command Registers are
write only and all other registers are writable and readable.
Access to these registers is via the CPU interface: Control
signals ENREGIO, RD, WR , REGPS [1:0], and the
Command/Status Data Bus CdSt [7:0].
2. The read that reads a packets status double word
from the FIFO.
In the case of SPDTAVL being driven low upon the high
going edge of the read that meets one of the above
conditions, the SPDTAVL output will remain low for a
period of 8 RXRD_TXWR clock cycles. For the time that
SPDTAVL remains low, further reads are blocked within
the chip even if external reads continue. This allows
overreading the receive FIFO by a few cycles without,
internal to the chip, reading an empty FIFO or reading new
packet data before the present packet is processed. It is up
to the processor doing the FIFO reads to determine on
which read cycle the SPDTAVL went low and thereby
which read cycles are over reads containing invalid data.
3.6.2 Station Address Register
The Station Address Register is 6 bytes in length. The
contents may be written in any order, with bit “0” of byte “0”
corresponding to the first bit received in the data stream,
and indicating whether the address is physical or logical.
Bit 7 of station address byte 5 is compared to the last bit of
the received destination address. The Station Address
should be programmed prior to enabling a port’s receiver.
3.6.3 Transmit Command Register
The transmit command register is an 8 bit writable register.
Bits 0 through 3 of the Transmit Command Register
function as interrupt mask bits, which provide for control of
the conditions allowed to generate transmit interrupts.
Each of the four bits may be individually set or cleared.
When set, the occurrence of the associated condition will
cause an interrupt to be generated. The four specific
conditions for which interrupts may be generated are:
3.5.4 Special Conditions on the RXRD_TXWR input
This input is required to be tied to a continuous clock signal
whose maximum clock frequency can be 33Mhz. The
number of read or write cycles occurring to the chip is
controlled through the TXWREN and RXRDEN inputs. All
transitions of the TXRDY, RXRDY, RXTXEOF, SPDTAVL,
RXDC, RXTXDATA[31:0], and TXRET outputs are synchronized internally to the RXRD_TXWR clock and are
clocked to the output drivers on the highgoing edge of the
clock.
1. A Transmit FIFO underflow occurred while
transmitting the packet.
3.6 Register Interface
Writing of Command, Configuration, and Station Address
registers and reading of status registers is controlled by
the ENREGIO, RD, WR, REGPS[1:0], and A[2:0] signals.
2. A collision occurred while transmitting the packet.
4-21
21
MD400151/C
4-Port 84C30A
3. A transmit error condition occurred i.e,
(Carrier sense never went active during
transmission or went from an active to inactive state
during transmission or 16 collisions occurred for a
transmit packet or a late collision occured).
A delay time after the highgoing edge of the read operation
that reads new transmit status, one of the internal transmit
status registers will be cleared and made available for new
transmit status. Following are the types of transmit status
given through status register:
4. The packet was transmitted successfully.
Bit 0 - Transmit FIFO Underflow Occurred
Bit 1 - Collision during transmission occurred.
Interrupts are cleared by following the procedure given in
the section entitled "Clearing Interrupts".
Bit 2 - 16 collisions occurred while attempting to
transmit a packet.
Bit 4 is used for testing purposes and should not be
written high under normal circumstances.
Bit 3 - Packet transmitted successfully.
Bit 4 - Carrier Sense error during transmission
attempt.
Bits 5 and 6 are used in conjunction with the A[2:0] address
pins to access registers other than the Receive and
Transmit Command and Status Registers within a port.
(See the Internal Port Register Addressing table).
Bit 5 - Transmit Deferred Due to Carrier Sense.
Bit 6 - Late Collision
Bit 7 - Old/New Status.
Bit 7 is used for testing purposes and should not be
written high under normal circumstances.
Bit 5 of the Transmit status register (transmit OK but defer)
is an indication that the transmit state machine was ready
to initiate a transmission but it has to defer due to carrier
sense being HIGH. Bit 6 of the Transmit status register
(Late Collision) is an indication that the transmitter encounter a collision contention 64 byte times after TXEN
when HIGH.
Transmit Command Register Format
Values After Reset
7 6 5
4 3 2
1 0
BIT
0 0 0 0 0 0 0 0
A port can be programmed so that if both transmit registers
are full, no new transmissions will occur until at least one
of the register is cleared by reading it. To program this
feature, bit #1 of configuration register #2 needs to be
written to a 1 value.
Interrupt on Transmit Underflow
Interrupt on Transmit Collision
Tx Error Condition
Interrupt on Transmission
Successful
Also a port can be programmed so that no new transmit
status is loaded if the transmission is successful.
Test Mode
Register Code Bit 0
Transmit Status Register Format
Register Code Bit 1
7 6
Test Mode
3.6.4 Transmit Status Register
Within each port's transmit section are 2 transmit status
registers. These registers give the appearance of a single
register to an external CPU. With each transmission attempt, whether successful or not, one of the status registers is written with the transmit status for that packet and
bit 7 of that register is set to a 0 until both registers are full.
When both registers are full, no new transmit status can be
written until one of the registers is read. To an external
CPU, both transmit status registers appear as a single
register. If the CPU reads a LOW value for bit 7 of the
transmit status register, this indicates that either one or
both of the internal transmit registers contains new status.
BIT
Transmit Underflow
Transmit Collision
16 Transmission Attempts
Transmission Successful
Carrier Sense Error During
Transmission
Transmit OK But Defer
Late Collision
Old/New Status
22
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MD400151/C
5 4 3 2 1 0
4-Port 84C30A
3.6.5 Receive Command Register
A port’s Receive Command Register has two primary
functions, it specifies the Address Match Mode, and it
specifies which types of receive frames will be received
and if an associated interrupt will be produced. To set
interrupt conditions the Receive Command Register uses
bits 5 through 0 in conjunction with bit #7 of configuration
register #1.
Receive Command Register Format
7 6
5 4 3 2 1 0
BIT
Interrupt on Overflow Error
Interrupt on CRC Error
Interrupt on Oversize Frame
Interrupt on Short Frame
Bit 7 of configuration register #1 is a general receive
interrupt disable. Setting this bit HIGH disables all receive
interrupt conditions even if one of the bits 0 through 5 in the
receive command register is set HIGH. This allows enabling reception of receive packets with errors without an
interrupt being produced. With the general receive interrupt bit LOW, a receive interrupt can be produced on one
or more of the following conditions by setting its associated
interrupt enable bit in the receive command register:
Interrupt on 12 Bytes Received
Interrupt on Good Frames
Match Mode 0
Match Mode 1
Bits 0-5 specify Interrupt and Frame-of-Interest when set.
Match
Mode
1
Match
Mode
0
0
0
0
Receiver Disable
(Rx Command Bit 3)
1
2
0
1
1
0
4. Interrupt on reception of
oversize frame.
(Rx Command Bit 2)
3
1
1
Receive All Frames
Receive Station or Broadcast
Frames
Receive Station,
Broadcast/Multicast Frames
5. Interrupt on reception of
a frame with a CRC error.
(Rx Command Bit 1)
6. Interrupt on a receive FIFO
overflow error.
(Rx Command Bit 0)
1. Interrupt on good frames
(Rx Command Bit 5)
2. Interrupt on receiving the
12 bytes of data for a
packet.
(Rx Command Bit 4)
3. Interrupt on reception of
a short frame.
Match Mode Definition
Changing the receive Match Mode bits during frame reception may change chip operation and give unpredictable
results.
For conditions 3, 4, 5 and 6 above, the associated interrupt
enable bit also acts as a receive enable bit. This means for
example that if bit 1 of the receive command register is
written high, packets with CRC errors will be received and
no receive discard will be asserted. By using a combination of the general receive interrupt disable bit 7 in configuration register #1 and bits 0 through 3 of the receive
command register, a port can be programmed to accept
packets with error conditions without the generation of an
interrupt.
Interrupt Enable and Frames-of-Interest
Bits 0-5 when set specify interrupt generation on occurrence of the corresponding frame reception condition.
3.6.6 Receive Status Register
Within each port’s receive section, there is a receive status
register that is written with the status of each receive
packet whether it is discarded or not. Once the receive
status register is written, bit 7 of the register is set to a 0 and
the register is write protected from being overwritten with
new status until it is read. Reading the receive status
Bits 6 and 7 of the Receive Command Register are the
receive match mode bits.
4-23
23
MD400151/C
Function
4-Port 84C30A
register clears the register and enables it to be written with
new status. The following packet status is reported in the
receive status register:
status set HIGH should be considered to have bad data.
This condition should never occur in a properly designed
application. If status is ever read with Bit 8 being HIGH, the
receive section will automatically reset itself to provide a
clean starting point for further packet reception.
Bit 7 - Old/New status
Bit 6 - 12 bytes of a frame received.
Bit 5 - Received good frame.
Bit 4 - Oversized frame received.
Bit 3 - Short frame error.
Bit 2 - Frame with dribble bits or nibbles.
Bit 1 - Frame with CRC error.
Bit 0 - Receive FIFO overflow error.
Format of the Status Double Word
31
16
8
0
Reserved
Byte Count
Receive packet status is also included as part of the final
double word of receive data for a packet that is not
discarded. The final double word of a packet as read from
the receive FIFO contains the status and the byte count for
that packet with the status appearing as the least significant word of the double word and the byte count appearing
in the two most significant bytes of the double word. The
status read through the FIFO has the same bit values as
the receive status register except for the following:
Status Register Word
Note: This status double word gets appended to the
packet in same format for both Little and Big Endian
modes.
Status Register Word
8
7
6
5 4 3 2 1 0
BIT
Word 0 of the Double Word
Bit 7: RXABORT During Reception
Bit 8: Read Error Condition
Received Frame with Overflow Error
Received Frame with CRC Error
Bit 7 is an indication that the RXABORT pin was pulsed
HIGH while CSN was HIGH for the packet. Bit 8 Indicates
that some type of error has occurred in the receive FIFO
control circuitry with a result that the number of double
words written to the FIFO as indicated by the byte count
portion of the status double word does not equal the
number of double words read from the FIFO for the packet.
This type of error can only be caused by some type of noise
glitch or other unusual occurrence within the receive
section. Any packet read from the FIFO with Bit 8 of the
Received Frame with Dribble Error
Received Short Frame
Received Oversize Frame
Received Good Frame
Received 12 Bytes of a Frame
RXABORT During Reception
Read Error Condition
24
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MD400151/C
4-Port 84C30A
Clearing Interrupts
Both receive and transmit interrupts for a port are combined into a single interrupt signal which then goes to that
port's INT output pin. The interrupt signal within a port in
the chip is actually the result of the receive/transmit status
register outputs and the receive/transmit command register interrupt enable bits that are set. To clear an interrupt
the status that caused the interrupt needs to be cleared.
This can be accomplished by reading the transmit status
register and/or the receive status register.
Don’t Load Tx Status Upon Successful Transmit Mode
If bit #0 of configuration register #2 is set, then a packet that
has been transmitted successfully will not have it’s status
loaded into either of the two internal transmit status registers.
Disable Further Transmission Upon Full Tx Status
Register Mode
If bit #1 of configuration register #2 is set, whenever both
Tx Status Registers have been filled, no new transmissions will occur until one of the Tx Status Registers is
cleared, even if the transmit FIFO has transmit data.
3.6.7 Configuration Register #2
Allows for control of a port’s transmission of one packet at
a time, Busmode, Multi-cast hash filter, reception of runt
frames, and halting new transmissions until one of the
port’s transmit status registers is cleared.
7
6 5 4
Successful Packet Transmission Complete Feature
This feature is programmable by setting bit 7 of configuration register #2 to a ‘1’ value. If this bit is set, then,
independent of the FIFO threshold setting, the corresponding port’s TXRDY pin will go LOW once the final
double word of data for a transmit packet is written to the
transmit FIFO. Once a port’s TXRDY has been driven
LOW due to this condition, it will remain LOW until the
packet has completed transmission without error or until a
transmission exception condition causing the TXRET pin
to go HIGH is cleared. This allows the user to determine
when a packet has completed successful transmission by
detecting when the corresponding port’s TXRDY goes
HIGH after the final double word of the packet has been
written. After TXRDY goes LOW due to a double word
write with the RXTXEOF pin HIGH, further writes to the
transmit FIFO are allowed as long as the SPDTAVL pin
indicates that there is still space available within the
transmit FIFO.
3 2 1 0
Bit 0 = ‘1’ Disable
Loads to Transmit
Status Reg. Upon
Transmission
Successful
Bit 1 = ‘1’ Disables
New Transmissions
Upon Full TX
Status Registers
Bit 2 = ‘1’ Sets a High
Value of EOF as the 33rd
Bit on Both the Last
Double Word of Data and
the Status Double Word
Big Endian Mode
Writing this bit HIGH programs the port to Big Endian
mode.
Bit 3 = ‘1’ Enables
Hash Filter for Multicast
Pack Only Two Valid Bytes in First Receive Double
Word, Bit 5
This is a read/write bit. When read, it indicates SQE status,
the SQE function is always on, when reading this register
it causes it to reset. If this bit is set then the first double
word of data written to the receive FIFO for a receive
packet will have only two valid bytes. When this first
double word is read out of the receive FIFO , which two
bytes are valid depends upon whether the port has been
programmed for Big Endian or Little Endian mode. For the
first double word read, only RXTXDATA[15:0] are valid if
bit #6 is HIGH, otherwise only RXTXDATA[31:16] are
valid. All subsequent double words of data read from the
receive FIFO will contain 4 valid bytes except for the last
double word which may not have all 4 bytes valid.
Bit 4 = ‘1’ Enables Packet
Reception Without
Discard Even if the
RXABORT Goes High
During Reception
Bit 5 =
Write = ‘1’ Packs Only 2
Bytes into the First
Double Word Written to
the Receive FIFO
Read = ‘1’ SQE Status
Bit 6 = ‘1’ If this bit is set,
whenever the EOF is written
to the Transmit FIFO for a
transmit packet, the TXRDY is
driven low until the packet has
completed transmission.
Bit 7 = ‘1’ Sets Port’s
FIFO Interfaces to Big
Endian Mode.
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MD400151/C
4-Port 84C30A
EOF on Data Bit 2
This function puts a HIGH EOF value on both the last
double word of data and the status double word.
Group Address Mode
In this mode the last 4 bits of the serial receive data stream
for the destination address are masked out in address
comparison. This means that when the destination address is compared against the value programmed in the
station address register that the packet will not be rejected
due to incorrect address even its last 4 bits did not match.
Multicast Mode
Each port has a 64 bit multicast address filter register
which can be accessed as shown in the Internal Port
Register Addressing Table (page 18). When a port is
programmed to receive multicast frames (match mode 3),
after computing the CRC on the address field of the
receiving frame (first 6 bytes), it will index to the multicast
address filter register depending on bits 0 to 5 of the CRC.
If the corresponding bit is a ‘1’ it will receive the frame,
otherwise it will discard the frame.
Transmit Packet Autopad Mode
This feature automatically pads packets to be transmitted
with less than 60 bytes of data out to a minimum IEEE
802.3 standard packet length of 60 bytes excluding FCS.
Padding is done with bytes of 00 hex.
Transmit No Preamble Mode
This mode prevents the transmitter from adding a preamble pattern at the beginning of data to be transmitted.
Configuration Register #1
Allows for control of a port’s various transmit and receive
features. Set to all 0’s after reset.
7 6
Disable Loopback Mode
Description on the Loopback mode (Bit #3 of Config 1)
5 4 3 2 1 0
The following description assumes that a transceiver is
connected to the MAC.
Bit 0 = ‘1’ Enables Group
Address Mode
Configuration Register #1
Bit 3
Bit 1 = ‘1’ Enables Transmit
Packet Autopad Mode
Bit 5
Mode
1
0
(
D
e
f
a
u
l
t
)
Half
Duplex
In this mode, the transmit
data looped back from the
transceiver is ignored by
the controller. The data
does not get written into
the receive FIFO and the
Rxrdy does not reflect the
incoming data.
0
(
D
e
f
a
u
l
t
)
1
Full
Duplex
In this mode, the
transceiver (In Full Duplex
mode), will not loopback
the transmitted data.
However, since data
reception is possible during
transmission, bit 3 should
be written with ‘0’ so that
the data gets written to the
Receive FIFO.
Bit 2 = ‘1’ Enables Transmit No
Preamble Mode
Bit 3 = ‘1’ Receive Own Transmit
Disable Mode
Bit 4 = ‘1’ Enables Transmit No
CRC Mode
Bit 5 = ‘1’ Enables Full Duplex
Mode
[Bit 3 Should be ‘0’]
Bit 6 = ‘1’ Enables Receive CRC
Mode
Bit 7 = ‘1’ Disables Receive Interrupt’s
Half Duplex Mode
Bit 3 = ‘1’, Bit 5 = ‘0’
In this mode, the transmit data looped back from the
transceiver (connected to a port of the 84C300) is ignored
by the controller. The data does not get written into the
receive FIFO and the Rxrdy does not reflect the incoming
data.
26
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MD400151/C
Functional Description
4-Port 84C30A
Algorithm for Defer Time Calculations for 10 Mbit
Serial Mode
Full Duplex Mode
Bit 3 = ‘0’, (default), Bit 5 = ‘1’
In this mode, the transceiver (in Full Duplex mode), will not
loopback the transmitted data. However, since data
reception is possible during transmission, bit 3 should be
written with a value of ‘0’ so that the data gets written to the
receive FIFO.
Defer Time = Int {{Int (Delay/100)+17+DefRegSet}/8}+2
Defer Time = The transmit defer time in byte times
Delay = Delay from the down going edge of TXEN to the
down going edge of CSN. (Half Duplex)
= 0 (Full Duplex)
Transmit No CRC Mode
This mode prevents a port’s transmitter from appending
transmit data with an FCS.
DefRegSet = The transmit defer register setting
Int = Using the Whole Number Portion
Example Calculations
Full Duplex Mode
In this mode a ports transmitter will ignore carrier sense
and will not defer to it if it is ready to transmit a packet.
To find out the value that needs to be programmed
into the defer register for a defer time of 9600 ns, the
following steps need to be taken
The software bit setting and the hardware setting (pin
#108) have an OR relationship. This means that either the
hardware or software setting will enable Full Duplex.
Assume Delay = 3400 ns
Desired Defer Time = 9600 ns = 12 byte times
The desired byte times should be a multiple of 800
Receive CRC Mode
In this mode a ports receiver loads the 4 bytes of FCS into
the receive FIFO along with the data allowing the FCS
value to be read out.
Step 1: Calculation of the Actual Defer Time
Let’s assume a Defer Register Setting Value of 21
Defer Time = Int { { Int (Delay / 100) + 17 + DefRegSet}
/8} + 2
Disable Receive Interrupts
With this bit set, a port’s receiver is disabled from producing receive interrupts.
= Int { { Int (34) + 17 + 21}/8} + 2
= Int {9} + 2
= 9 + 2 = 11 byte times
3.6.8 FIFO Threshold Register
This register allows programming of the threshold of
Space Available and/or Data Available double word
counts that cause assertion of the TxRDY and/or RxRDY
signals respectively. Bits 4 through 7, when written with a
binary value, indicates the minimum number of double
words necessary in the receive FIFO before RxRDY is
asserted. Similarly, bits 0 through 3, when written with a
binary value, indicate the minimum number of double word
wide spaces necessary in the transmit FIFO for TxRDY to
be asserted. On page 28 is a table showing how many
double words of space/data are required to cause the
TXRDY/RXRDY signals to go high for each threshold
setting.
Step 2: Calculation of the Actual Defer Register
Setting
Since we know that the value derived from the
previous step is 1 byte time lower than what is
desired we will increment the assumed defer
register setting by 8 and do the calculations again.
Let’s assume a Defer Register Setting Value of 29
Defer Time = Int {{Int (Delay / 100)+17+DefRegSet}
/8} + 2
= Int { { Int (34) + 17 + 29 } /8} + 2
= Int { 10 } + 2
3.6.9 Defer Register Calculations for the 84C30A
= 10 + 2 = 12 byte times
Defer Time Definitions
In the standard Half Duplex Mode, Defer time is defined as
the time from the falling edge of carrier sense to the rising
edge of TXEN. In full duplex mode, the defer time is
measured as the time from the falling edge of TXEN to the
next rising edge of TXEN. The binary value programmed
into the defer count register is used to determine how many
byte times the defer time will be set to. The algorithms
below illustrates how the defer time is calculated.
Please note that you might have to do this process
several times before you can get the actual defer
register setting for a desired defer time based on your
delays.
3.6.10 Transmit Control/Product I.D. Register
The lower four bits can be used to set a threshold value on
the transmit FIFO that can be used to control the packet
transmission and the upper four bits of this register con-
4-27
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MD400151/C
4-Port 84C30A
tains the product I.D. When the lower four bits are written
with a decimal value ranging from 1 to 15, packet transmission from the FIFO will begin only when the count of the
double words of data written into the transmit FIFO equals
or exceeds twice the register value. For example, when
the lower four bits are written with a decimal value of 15,
data transmission will begin only after the FIFO is written
with 30 or more double words of data. This threshold value
is valid only at the beginning of frame transmission and it
will take effect again when the user starts to load the
beginning of the next frame. The default decimal value of
the lower four bits is ‘0’ and packet transmission will begin
automatically when the FIFO is loaded with a minimum of
one double word of data. The upper four bits are read only
and contain a value of ‘A’.
before it is read. Normally, once the low byte has been read
the counter is reset to zero. Should the 84C30A attempt
to increment the counter while it is frozen, then reading the
low byte of the counter causes it to be loaded with 0001 hex
thereby preventing the counter from missing a count.
Runt Frame Counter
This is a 16 bit read only counter that counts the number
of frames received or discarded less than the minimum
valid frame time (64 bytes). Upon reaching its maximum
count value of FFFF hex, this counter will stop counting. To
read this counter, two consecutive reads must be performed to the same address location. The first read, reads
out the high byte and the second read, reads out the low
byte. Upon reading the high byte, the count value of the
low byte is frozen to prevent the low byte count value from
rolling over before it is read. Normally, once the low byte
has been read the counter is reset to zero. Should the
84C30A attempt to increment the counter while it is frozen,
then reading the low byte of the counter causes it to be
loaded with 0001 hex thereby preventing the counter from
missing a count.
3.7 COUNTERS
CRC Error Counter
This is a 16 bit read only counter that counts the number
of frames received or discarded with CRC errors but no
framing errors. Upon reaching its maximum count value of
FFFF hex, this counter will stop counting. To read this
counter, two consecutive reads must be performed to the
same address location. The first read, reads out the high
byte and the second read, reads out the low byte. Upon
reading the high byte, the count value of the low byte is
frozen to prevent the low byte count value from rolling over
Receive Oversize Frame Counter
This is a 8-bit counter that counts the number of receive
frames with greater than the 1518 byte maximum frame
size of data. Upon reaching its maximum count value of FF
3.6.6.1 FIFO Threshold Register Settings Table
Fifo Threshold Register Bits
Minimum # of
Double Words of
Data for RXRDY High
Minimum # of
Double Word Spaces
for TXRDY High
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
2
2
0
0
1
0
0
0
1
0
3
3
0
0
1
1
0
0
1
1
4
4
0
1
0
0
0
1
0
0
5
5
0
1
0
1
0
1
0
1
6
6
0
1
1
0
0
1
1
0
7
7
0
1
1
1
0
1
1
1
8
8
1
0
0
0
1
0
0
0
9
9
1
0
0
1
1
0
0
1
10
10
1
0
1
0
1
0
1
0
11
11
1
0
1
1
1
0
1
1
12
12
1
1
0
0
1
1
0
0
13
13
1
1
0
1
1
1
0
1
14
14
1
1
1
0
1
1
1
0
15
15
1
1
1
1
1
1
1
1
16
16
28
4-28
MD400151/C
4-Port 84C30A
hex, this counter will stop counting. During reading of this
counter the count value will be frozen to prevent incrementing while being read. Should the 84C30A attempt to
increment the counter while it is frozen, then the counter
will be loaded with 01 hex upon completion of the read.
Otherwise, completing the read will reset the counter to 00
hex.
value of FFFF hex, this counter will stop counting. To read
this counter, two consecutive reads must be performed to
the same address location. The first read, reads out the
high byte and the second read, reads out the low byte.
Upon reading the high byte, the count value of the low byte
is frozen to prevent the low byte count value from rolling
over before it is read. Normally, once the low byte has been
read the counter is reset to zero. Should the 84C30A
attempt to increment the counter while it is frozen, then
reading the low byte of the counter causes it to be loaded
with 0001 hex thereby preventing the counter from missing
a count.
Alignment Error Counter
This is a 16 bit read only counter that counts the number
of frames received or discarded with a framing error and a
CRC error both. Upon reaching its maximum count value
of FFFF hex, this counter will stop counting. To read this
counter, two consecutive reads must be performed to the
same address location. The first read, reads out the high
byte and the second read, reads out the low byte. Upon
reading the high byte, the count value of the low byte is
frozen to prevent the low byte count value from rolling over
before it is read. Normally, once the low byte has been read
the counter is reset to zero. Should the 84C30A attempt
to increment the counter while it is frozen, then reading the
low byte of the counter causes it to be loaded with 0001 hex
thereby preventing the counter from missing a count.
Receive Collision Counter
This is a 16 bit read only counter that counts the number
of collisions other than transmit collisions that occur.
Collisions due to the SQET test are not counted. Upon
reaching its maximum count value of FFFF hex, this
counter will stop counting. To read this counter, two
consecutive reads must be performed to the same address location. The first read, reads out the high byte and
the second read, reads out the low byte. Upon reading the
high byte, the count value of the low byte is frozen to
prevent the low byte count value from rolling over before it
is read. Normally, once the low byte has been read the
counter is reset to zero. Should the 84C30A attempt to
increment the counter while it is frozen, then reading the
low byte of the counter causes it to be loaded with 0001 hex
thereby preventing the counter from missing a count.
Transmit Collision Counter
This is a 16 bit read only counter. Bits 15 through 11 of this
counter count the number of retransmission attempts a
packet required before being transmitted successfully.
Bits 10 through 0 count the number of transmit collisions a
port has experienced. Upon reaching its maximum count
4-29
29
MD400151/C
4-Port 84C30A
Absolute Maximum Ratings
Operating Conditions
Ambient Temperature
Under Bias ........................................... –10°C to + 80°C
Storage Temperature .......................... –65°C to +150°C
All Input or Output Voltages
with Respect to Ground ........................... +6V to –0.3V
Package Maximum Power Dissipation ............ 1.5 Watts
Ambient Temperature Range ...................... 0° C to 70°C
VCC Power Supply ................................ 4.75 V to 5.25 V
4.0 DC Characteristics
TA = 0° C to 70°C, VCC = 5 V to 5%
Limits[1]
Symbol
Parameter
IIN
Min.
Typ.
Max.
Units
Input Leakage Current
10
µA
VIN = 0.45 V to 5.25 V
IO
Output Leakage Current
10
µA
VOUT = 0.45 V to 5.25 V
ICC
VCC Current
300
mA
VCH
Clock Input High Voltage
6
V
VCL
Clock Input Low Voltage
0.8
V
VIL
Input Low Voltage
0.8
V
VIH 1
Input High Voltage
6
V
VOL
Output Low Voltage
RXTXDATA [31:0], RXTXEOF,
SPDTAVL, TXRDY_[1:4],
RXRDY_[1:4], TXRET_[1:4],
RXDC_[1:4]
0.4
V
IOL = 8 mA
VOH
Output High Voltage
RXTXDATA [31:0], RXTXEOF,
SPDTAVL, TXRDY_[1:4],
RXRDY_[1:4], TXRET_[1:4],
RXDC_[1:4]
V
IOH = 8 mA
VOL
Output Low Voltage
TXD [0:3]_[1:4],
TXEN_[1:4]
V
IOL = 4 mA
VOH
Output High Voltage
TXD [0:3]_[1:4],
TXEN_[1:4]
V
IOH = 4 mA
VOL
Output Low Voltage
All Other Outputs
V
IOL = 2 mA
VOH
Output High Voltage
All Other Outputs
V
IOH = 2 mA
250
4.0
2.0
2.4
0.4
2.4
0.4
2.4
NOTE:
1. Typical values are for TA = 25°C and nominal supply voltages.
30
4-30
MD400151/C
Condition
4-Port 84C30A
AC Test Conditions
Capacitance
Output Load: 1 Schottky TTL Gate + CL = 100 pF
except where specifically given otherwise in the condition
column.
Input Pulse Level:0.4 V to 2.4 V
Timing Reference Level:1.5 V
5.0 AC Characteristics
TA = 25°C, FC = 1 MHz
Symbol Parameter
Maximum
Condition
CIN
Input Capacitance
15 pF
VIN = 0 V
CI/O
I/O Capacitance
15 pF
VI/O = 0 V
TA = 0° C to 70°C, VCC = 5 V ± 5%
Limits
[1]
Max.
(ns)
0.5 RXC/TXC
Cycles + 10 ns
1.5 RXC/TXC
Cycles + 50 ns
ns
All Other Registers
10
50
ns
TDBR
CDST [7:0]
Bus Release Delay
1.5
5.5
ns
TDBS
CDST [7:0]
Bus Siezure Delay
6
32
ns
THA
A[3:0] Hold
10
ns
THDA
CdSt Bus Hold
0
ns
TSA
A[3:0] Setup
15
ns
TSCS
CdSt Bus Setup
10
ns
Symbol
Parameter
Min.
Typ.
Units
Condition
COMMAND/STATUS INTERFACE READ AND WRITE TIMING
TDBD
Receive/Transmit
Command Status, and
Management Counters
RXC, TXC = 10 MHz
THCS
CdSt Bus Hold
0
ns
TRWH
RD/ High Width
1 TXC/RXC
Cycle
ns
RXC, TXC = 10 MHz
TRWL
RD/ Low Width
1.5 TXC/RXC
Cycles + 70 ns
ns
RXC, TXC = 10 MHz
TWWH
WR High Width
30
ns
TWWL
WR Low Width
30
ns
NOTES:
1. Italics indicate input requirement, non-italics indicate output timing.
4-31
31
MD400151/C
4-Port 84C30A
5.01 Command/Status Interface Read Timing
TRWL
RD
TRWH
TSEN
THEN
ENREGIO
THPS
TSPS
REGPS[1:0]
THA
TSA
A0-A3
TDBS
TDBR
CDST[7:0]
TDBD
DATA VALID
5.02 Command/Status Interface Write Timing
TW
WR
TWWH
TSEN
ENREGIO
TSPS
THPS
REGPS[1:0]
TSA
A0-A3
THA
TSCS
CDST[7:0]
THCS
32
4-32
MD400151/C
4-Port 84C30A
6.0 Ethernet Transmit and Receive Interface Timing
AC Characteristics
TA = 0° C to 70° C, VCC = 5 V ± 5%
ETHERNET TRANSMIT INTERFACE TIMING
Limits
Symbol
Parameter
Min.
TDTD
TXD/TXEN Delay
5 ns
TWHTC
TXC High Width
45
TWLTC
TXC Low Width
45
Typ.
20 ns
ETHERNET RECEIVE INTERFACE TIMING
THRD
RxD Hold
5 ns
TSRD
RxD Setup
5 ns
TWHRC
RxC High Width
45
TWLRC
RxC Low Width
45
6.01 ETHERNET TRANSMIT INTERFACE TIMING
TWHTC
TWLTC
TPCK
TxC
TDTD
TxD
TDTD
TxEN
TDTD
6.02 ETHERNET RECEIVE INTERFACE TIMING
TWHRC
TWLRC
RxC
TSRD
RxD
THRD
CSN
4-33
33
MD400151/C
Max.
Condition
4-Port 84C30A
7.0 Transmit Data Interface Timing
Symbol
Parameter
Min.
t1
Transmit Interface Enable
to Clock Setup Time
5ns
t2
Transmit Write Enable
to Clock Setup Time
5 ns
t3
Transmit Interface Enable
to Transmit Write Enable
Timing Skew
0 ns
t4
Port Select Inputs
to Clock Setup Time
5 ns
t5
TXRDY Output Enabled
to Output Valid Delay
5 ns
25 ns
t6
SPDTAVL Output Enable
to Output Valid Delay
4 ns
24 ns
t7
Transmit Data, Byte
Enables, TXEOF, TXNOCRC
to Clock Setup Time
5 ns
t8
Transmit Data, Byte
Enables, TXEOF, TXNOCRC
Hold Time
1.5 ns
t9
TXRDY Deassert Due to
Threshold Being Met
5 ns
25 ns
t10
SPDTAVL Output Disabled
to Hi-Z Delay
3 ns
14 ns
t11
TXRDY Output Disabled
to Hi-Z Delay
3 ns
13 ns
t12
Port Select Inputs
Hold Time
0 ns
t13
Transmit Write Enable
Hold Time
0 ns
t14
Transmit Interface
Enable Hold Time
0 ns
t15
SPDTAVL Deassert Due to
Transmit FIFO Reading an almost
Empty Condition
4 ns
34
4-34
MD400151/C
Typ.
Max.
24 ns
4-Port 84C30A
7.01 Transmit Data Interface Write Timing 1
1
2
3
4
5
6
7
9
RXRD_TXWR
t1
t3
TXINTEN
t9
t5
TXRDY
t4
t 12
RXTXPS[1:0]
t2
t 13
TXWREN
t7
RXTXDATA[31:0]
1
t8
2
3
4
5
6
7
t7
8
t8
RXTXBE[3:0]
t 15 [1]
t6
SPDTAVL
t7
t8
TXNOCRC
Notes: 1. SPDTAVL gets deasserted because of the 7th double word write to the transmit FIFO indicating that the 8th
double word write will fill the FIFO completely. It is important to note that the data gets pipelined internally, hence
the 7th external double word write (The 7th Clock Edge that latches in the active low TXWREN) actually happens
on the 8th clock cycle internally.
4-35
35
MD400151/C
4-Port 84C30A
7.02 Transmit Data Interface Write Timing 2
n-3
n-2
n-1
n
RXRD_TXWR
t14
TXINTEN
t2
TXWREN
RXTXBE[3:0]
RXTXDATA[31:0]
n-3
n-2
n-1
n
t9
t 11
TXRDY
t 10
SPDTAVL
t7
RXTXEOF
t8
t7
t8
TXNOCRC
36
4-36
MD400151/C
4-Port 84C30A
8.0 Receive Data Interface Timing
Symbol
Parameter
Min.
t1
Receive Interface Enable
to Clock Setup Time
5ns
t2
Receive Read Enable
to Clock Setup Time
5 ns
t3
Receive Interface Enable
to Receive Read Enable
Timing Skew
0 ns
t4
SPDTAVL Output Enabled to
Output Valid Delay
4 ns
t5
Receive Byte Enables
to Clock Setup Time
5 ns
t6
Port Select Inputs
to Clock Setup Time
5 ns
t7
RXRDY Output Enabled
to Output Valid Delay
4 ns
26 ns
t8
RXTXDATA [31:0], RXTXEOF
Outputs Enabled to Outputs
Valid Delay
5 ns
22 ns
t9
FIFO Read Strobe High to
RXTXEOF, RXTXDATA[31:0]
FIFO Data Out Delay
5 ns
24 ns
t10
Clock to SPDTAVL Low Delay
SPDTAVL Deassert to Assert
Minimum Low Time
Typ.
Max.
24 ns
22 ns
8 RXRD_TXWR
Cycles
t12
SPDTAVL Output Disabled
to Hi-Z Delay
3 ns
14 ns
t13
RXRDY Output Disabled to
Hi-Z Delay
3 ns
12 ns
t14
Receive Data and RXTXEOF
Outputs Disabled to Hi-Z Delay
3 ns
13 ns
t15
RXRD_TXWR Clock Pulse
Width High
12 ns
t16
RXRD_TXWR Clock Pulse
Width Low
12 ns
t17
RXRD_TXWR Clock Period
30 ns
t18
Port Select Inputs
Hold Time
0 ns
t19
Byte Enables Hold Time
0 ns
t20
Receive Read Enable
Hold Time
0 ns
t21
Receive Interface Enable
Hold Time
0 ns
4-37
37
MD400151/C
180 ns
Condition
4-Port 84C30A
Receive Data Interface Timing (cont’d)
Symbol
Parameter
Min.
Typ.
Max.
Condition
t22
RXRDY Deassert Due to Emptying
RX FIFO Below Threshold
4 ns
26 ns
t23
RXRDY Assert from CSN Going
Low Due to Status Write
9 RXC Cycles
+ 2.5 RXRD_TXWR
Cycles + 4 ns
17 RXC Cycles
+ 3.5 RXRD_TXWR
Cycles + 22 ns
8.01 Receive Data Interface Read Timing 1
t 15
1
2
3
4
5
6
7
8
RXRD_TXWR
t 17
t 16
t1
t3
RXINTEN
t7
t 23
RXRDY
t6
t 18
RXTXPS[1:0]
t2
t 20
RXRDEN
t9
t 26
t8
1
RXTXDATA[31:0]
2
3
4
5
6
7
Invalid
t5
RXTXBE[3:0]
1
2
3
4
5
6
7
t19
t 10 [1]
t4
t12
SPDTAVL
t8
t 26
RXTXEOF
Notes: 1. SPDTAVL gets deasserted because of the 7th double word read from the receive FIFO indicating that there is
no more data available in the receive FIFO and further reads will cause invalid reads. Here, it is important to note
that the 7th read is referred to the 7th clock edge that latches in the active low RXRDEN and the resultant data
can be latched out on the 8th clock edge because of the pipelining effect.
38
4-38
MD400151/C
4-Port 84C30A
8.02 Receive Data Interface Read Timing 2
n-3
n-1
n-2
n
Stat
RXRD_TXWR
t 21
RXINTEN
t 13
t 22
RXRDY
t7
t 18
RXTXPS[1:0]
RXRDEN
t 14
t8
RXTXDATA[31:0]
n-3
n-2
n-1
n
Stat
RXTXBE[3:0]
t8
RXTXEOF
CSN
t 23
t 12
t4
SPDTAVL
4-39
39
MD400151/C
4-Port 84C30A
9.0 Transmit Data Interface Timing on Exception Conditions
Symbol
Parameter
Min.
Typ.
Max.
t1
TXINTEN Setup Time
5ns
t2
RXRD_TXWR to TXRET Delay
t3
TXRET Deassert from CLRTXERR
t4
TXWREN Setup Time
5 ns
t5
TXWREN Hold Time
0 ns
t6
CLRTXERR Setup Time
12 ns
t7
CLRTXERR Hold Time
0 ns
t8
TXRDY Output Enabled to Output
Valid Delay
5 ns
25 ns
t9
TXRDY Deassert Due to TXRET
Going HIGH Because of
an Exception Condition
5 ns
1 RXRD_TXWR Cycle
+ 25 ns
t10
RXTXDATA Setup Time
t12
TXEN Assert from First Data
Write to the Transmit FIFO
(Assuming Defer Time Has Been
Met)
t13
9.5 ns
38 ns
1 TXC Cycle
+ 1 RXRD_TXWR Cycle
+ 7 ns
2 TXC Cycles
+ 2 RXRD_TXWR Cycles
+ 28 ns
5 ns
0.75 RXRD_TXWR Cycles
+ 18.5 TXC Cycles + 5 ns
(10 Mbit/sec Serial Mode)
0.75 RXRD_TXWR Cycles
+ 26.5 TXC Cycles + 20 ns
(10 Mbit/sec Serial Mode)
TXRET Set Delay Due to
Late Collision or 16 Collisions
25 TXC Cycles
+ 1 RXRD_TXWR Cycle
+ 9.5 ns
34 TXC Cycles
+2 RXRD_TXWR Cycles
+ 38 ns
TXRET Set Due to Underflow
8 TXC Cycles
+ 1 RXRD_TXWR Cycle
+ 9.5 ns
8 TXC Cycles
+ 2 RXRD_TXWR Cycles
+ 38 ns
5 ns
25 ns
9.5 ns
38 ns
3 ns
12 ns
t15
TXRDY Going HIGH Due to TXRET
Going Low
t16
TXRET Output Enabled
to Output Valid Delay
t17
TXRET Output Disabled to Hi-Z
Delay
t18
INT High to TXEN Low Delay
Due to Underflow
1 TXC Cycle
+ 15 ns
1 TXC Cycle
+ 40 ns
TXEN Low to INT HIGH Delay
Due to Carrier Sense Dropout
2 TXC Cycles
+ 15 ns
2 TXC Cycles
+ 40 ns
10 ns
20 ns
20 TXC Cycles + 15 ns
27 TXC Cycles + 40 ns
1.5 TXC Cycles
+ 15 ns
2.5 TXC Cylces
+ 40 ns
TXEN Low to INT High
Delay Due to Successful
Transmission
t19
COLL High to INT High Delay
t20
INT Clear Delay
40
4-40
MD400151/C
4-Port 84C30A
9.0 Transmit Data Timing On Exception Conditions
RXRD_TXWR
t1
TXINTEN
t8
t9
t 15
TXRDY
t3
t2
t 16
t 17
TXRET
t4
TXWREN
t5
t 10
RXTXDATA[31:0]
SPDTAVL
t 12
TXEN
t 13
LATE
COLL
t6
INT
t 20
4-41
41
MD400151/C
4-Port 84C30A
10.0 Receive Data Interface Timing on Exception Conditions
Symbol
t1
Parameter
Min.
Typ.
Max.
Receive INT Delay Due to
Shortframe, CRC, Good Frame,
or Oversized Packet
2 RXC Cycles
+ 15 ns
2 RXC Cycles
+ 40 ns
Receive INT Delay Due to
Overflowed Packet
2 RXC Cycles
+ 15 ns
18 RXC Cycles
+ 40 ns
1.5 RXC Cycles
+ 15 ns
2.5 RXC Cycles
+ 40 ns
t2
INT Clear Delay
t3
CLRRXERR Setup Time
to RXRD_TXWR
6 ns
t4
CLRRXERR to
RXRD_TXWR Hold Time
0 ns
t5
CLRRXERR High to
RXDC Low Delay
t6
1 RXC Cycle
+ 3 RXRD_TXWR
Cycles + 6 ns
2 RXC Cycles
+ 4 RXRD_TXWR
Cycles + 27 ns
RXRDY Deassert Due to
Discard to RXDC High Delay
5 ns
1 RXRD_TXWR
Cycle + 11 ns
t7
RXRD_TXWR to RXDC
Delay
9 ns
37 ns
t8
SPDTAVL Deassert Due to
Discard to RXDC High Delay
5 ns
1 RXRD_TXWR
Cycle + 13 ns
t9
RXRD_TXWR to RXDC Hi-Z
3 ns
11 ns
t10
CSN Deassert to RXDC High
Due to Shortframe Error,
CRC Error, or Receive Abort
2 RXC Cycles
+ 3 RXRD_TXWR
Cycles + 9 ns
2 RXC Cycles
+ 4 RXRD_TXWR
Cycles + 37 ns
CSN Deassert to RXDC High
Due to Receive Overflow
Condition
2 RXC Cycles
+ 3 RXRD_TXWR
Cycles + 9 ns
18 RXC Cycles
+ 4 RXRD_TXWR
Cycles + 37 ns
t10a
RXDC High From Point of
Detection of Receive Packet
with Greater than 1518 Bytes
2 RXC Cycles
+ 3 RXRD_TXWR
Cycles + 9 ns
2 RXC Cycles
+ 4 RXRD_TXWR
Cycles + 37 ns
t11
RXABORT Pulse Width
1.5 RXC
RXABORT is
Asynchronously
Asserted with
Respect to RXC
RXABORT to RXC
Setup Time
5 ns
RXABORT is
Synchronously
Asserted with
Respect to RXC
RXC to RXABORT
Hold Time
5 ns
42
4-42
MD400151/C
Condition
4-Port 84C30A
10.0 Receive Data Timing On Exception Conditions
RXRD_TXWR
RXINTEN
t6
RXRDY
t7
t9
RXDC
t 10
RXRDEN
Invalid Invalid Invalid Invalid
RXTXDATA[31:0]
t8
SPDTAVL
t 11
RXABORT
t4
t3
CLRRXERR
t1
INT
t2
RD_B
4-43
43
MD400151/C
4-Port 84C30A
Ordering Information
Q
Q
84C30A
PACKAGE
TYPE
TEMPERATURE
RANGE
PART TYPE
PLASTIC QUAD FLATPACK
208 Pin PQFP
Q – 0°C to +70°C
EDLC
Full Duplex Designation
Full Duplex
Symbol indentifies product as
Full Duplex device.
Revision History
4/19/96
Page 20, Section 3.5.2:
- Using the 84C30A in 8 Bit or 16 Bit Mode, sub section has been added tothis section.
Page 20, Section 3.5.3:
- The end of the second paragraph in this section has been replaced with the new sub section
Using the 84C30A in 8 Bit or 16 Bit Mode.
Page 26: Receive Own Transmit Disable Mode has been deleted and replaced with new sub section Disable
Loopback Mode and new table Configuration Register #1.
Page 27: Section 3.6.9 has been entirely replaced with new copy.
9/25/96
Page 31, AC Characteristics:
- TDBD (min) has been changed from 100 to 0.5 RXC/TXC Cycles + 10 ns.
- TDBD (max) has been changed from 200 to 1.5 RXC/TXC Cycles + 50 ns.
- TDBD, All Other Registers (min) is now 10.
- TDBR (min) has been changed from 7 to 1.5.
- TDBR (max) has been changed from 20 to 5.5.
- TDBS (min) has been changed from 10 to 6.
- TDBS (max) has been changed from 20 to 32.
- Symbol THAR has been changed to THA.
- THA Parameter has been changed from A 0-2/Reg PS[1:0] Hold to A[3:0] Hold.
44
4-44
MD400151/C
4-Port 84C30A
Revision History
Page 31, AC Characteristics:
- Symbol TSAR has been changed to TSA.
- TSA Parameter has been changed from A0-2/Setup to A[3:0] Setup.
- THCS row is new.
- Symbol TWCH has been changed to TRWH.
- TRWH Parameter has been changed from RD/WR High Width, to RD High Width.
- TRWH (min) has been changed from 200 to 1 TXC/RXC Cycle.
- Symbol TWCL has been changed to TRWL.
- TRWL Parameter has been changed from RD/WR Low Width to RD Low Width.
- TRWL (min) has been changed from 200 to 1.5 TXC/RXC Cycles + 70 ns.
- TWWH row is new.
- TWWL row is new.
10/23/96
Page 4, Pin Description:
- Pin 35 Description now reads; This is the system clock acting as the chip’s ...
- Pin 39 Description now reads; This is an active high output that can be used for validating reads from the receive
FIFO during a read operation and preventing over writes to the transmit FIFO
during a write operation. For further details, please refer to the Transmit Data
Write timing and the Receive Data Read timing diagrams.
Page 12 - Section 2.0 Introduction has been deleted and replaced with new Section 2.0 Introduction.
Page 16 - Section 3.3.5 Second paragraph, now reads; Except for discards due to address mismatches and
oversized packets, all packet ...
Page 24 - Format of the Status Double Word, illustration has been added.
Page 26 - Configuration Register #1 Illustration has been changed; now reads, Bit 5 = ‘1’ Enables Full Duplex Mode
[Bit 3 should be ‘0’].
Page 28-29 - In Sections: CRC Error Counter, Runt Frame Counter, Alignment Error Counter, Transmit Collision Counter,
Receive Collision Counter; copy has changed ... To read this counter, two consecutive reads must be
performed to the same address location. The first read, reads out the high byte and the second
read, reads out the low byte. Upon reading ...
Page 30, DC Characteristics:
- Clock Input High Voltage (Limits Min.), has been changed from 3.5 to 4.0.
Pages 32 to 39, has been deleted and replaced with new Tables and Timing Diagrams, also the pagination has changed.
- Page 32, New Timing Diagrams, 5.01 Command/Status Interface Read Timing, and 5.02 Command/Status
Interface Write Timing.
- Page 33, New Timing Diagrams, 6.01 Ethernet Transmit Interface Timing, and 6.02 Ethernet Receive Interface
Timing.
- Page 33, New Table 6.0 Ethernet Transmit and Receive Interface Timing.
- Page 34, New Table, 7.0 Transmit Data Interface Timing.
- Page 35, New Timing Diagram, 7.01 Transmit Data Interface Write Timing 1.
- Page 36, New Timing Diagram, 7.02 Transmit Data Interface Write Timing 2.
- Page 37, New Table, 8.0 Receive Data Interface Timing.
- Page 38, New Timing Diagram, 8.01 Receive Data Interface Read Timing 1.
- Page 39, New Timing Diagram, 8.02 Receive Data Interface Read Timing 2.
- Page 40, New Table, 9.0 Transmit Data Interface Timing on Exception Conditions.
- Page 41, New Timing Diagram, 9.0 Transmit Data Timing on Exception Conditions.
- Page 42, New Table, 10.0 Receive Data Interface Timing on Exception Conditions.
- Page 43, New Timing Diagram, 10.0 Receive Data Timing on Exception Conditions.
12/5/96
Page 17; Internal Port Register Addressing Table
- Register Description Read, Dribble Error Counter has been changed to Alignment Error Counter.
Page 46; 208 Pin PQFP Dimension Diagram, illustration has changed.
4-45
45
MD400151/C
4-Port 84C30A
208 Pin PQFP
30.60 ± 0.25
0.18 ±0.05
28.0 ± 0.10
30.60 ± 0.25
28.0 ± 0.10
0.076
See Detail A
#1
0.19 ± 0.06
0.33 nom., 0.25 min.
1.25 Ref.
Typ (8 plc)
4.07 max.
0.50
3.37 +0.30
–0.20
0 - 7°
Detail A
1. All dimensions are in millimeters.
46
4-46
MD400151/C
0.50 ± 0.10