Am29F017B 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ Optimized for memory card applications — Backwards-compatible with the Am29F016C ■ 5.0 V ± 10%, single power supply operation — Minimizes system level power requirements ■ Manufactured on 0.32 µm process technology ■ High performance — Access times as fast as 70 ns ■ Low power consumption ■ Minimum 1,000,000 program/erase cycles per sector guaranteed ■ 20-year data retention at 125°C — Reliable operation for the life of the system ■ Package options — 40-pin TSOP — 48-pin TSOP ■ Compatible with JEDEC standards — 25 mA typical active read current — Pinout and software compatible with single-power-supply Flash standard — 30 mA typical program/erase current — Superior inadvertent write protection — 1 µA typical standby current (standard access time to active mode) ■ Flexible sector architecture — 32 uniform sectors of 64 Kbytes each — Any combination of sectors can be erased. — Supports full chip erase — Group sector protection: A hardware method of locking sector groups to prevent any program or erase operations within that sector group Temporary Sector Group Unprotect allows code changes in previously locked sectors ■ Embedded Algorithms ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase cycle completion ■ Ready/Busy# output (RY/BY#) — Provides a hardware method for detecting program or erase cycle completion ■ Erase Suspend/Erase Resume — Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation ■ Hardware reset pin (RESET#) — Resets internal state machine to the read mode — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies bytes at specified addresses This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21195 Rev: D Amendment/0 Issue Date: November 16, 1999 GENERAL DESCRIPTION The Am29F017B is a 16 Mbit, 5.0 volt-only Flash memory organized as 2,097,152 bytes. The 8 bits of data appear on DQ0–DQ7. The Am29F017B is offered in a 48-pin TSOP package. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMD’s 0.32 µ m process technology, and offers all the features and benefits of the Am29F016C, which was manufactured using 0.5 µm process technology. The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) 2 before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Am29F017B PRODUCT SELECTOR GUIDE Family Part Number Am29F017B (VCC = 5.0 V ± 5%) Speed Options -75 (VCC = 5.0 V ± 10%) -90 -120 -150 Max Access Time (ns) 70 90 120 150 CE# Access (ns) 70 90 120 150 OE# Access (ns) 40 40 50 75 Note: See the AC Characteristics section for more information. BLOCK DIAGRAM DQ0–DQ7 Sector Switches VCC VSS Erase Voltage Generator RY/BY# RESET# WE# Input/Output Buffers State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector Address Latch STB Timer A0–A20 STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix 21195D-1 Am29F017B 3 CONNECTION DIAGRAMS NC NC A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-Pin Standard TSOP 48 NC 47 NC 46 A20 45 NC 44 WE# 43 OE# 42 RY/BY# 41 DQ7 40 DQ6 39 DQ5 38 DQ4 37 VCC 36 VSS 35 VSS 34 DQ3 33 DQ2 32 DQ1 31 DQ0 30 A0 29 A1 28 A2 27 A3 26 NC 25 NC 21195D-2 NC NC A20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-Pin Reverse TSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 NC NC 21195D-3 4 Am29F017B CONNECTION DIAGRAMS A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40-Pin Standard TSOP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 21195D-4 A20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40-Pin Reverse TSOP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 21195D-5 Am29F017B 5 PIN CONFIGURATION A0–A20 = LOGIC SYMBOL 21 Addresses 21 DQ0–DQ7 = 8 Data Inputs/Outputs CE# = Chip Enable WE# = Write Enable OE# = Output Enable RESET# = Hardware Reset Pin, Active Low RY/BY# = Ready/Busy Output OE# VCC = +5.0 V single power supply see Product Selector Guide for device speed ratings and voltage supply tolerances) WE# VSS = Device Ground NC = Pin Not Connected Internally 6 A0–A20 8 DQ0–DQ7 CE# RESET# RY/BY# 21195D-6 Am29F017B ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29F017B -75 E I OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In (Contact an AMD representative for more information) TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) E4 = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040) F4 = 40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am29F017B 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory 5.0 V Read, Program, and Erase Valid Combinations Valid Combinations AM29F017B-75 (VCC = 5.0 V ± 5%) EC, EI, FC, FI, E4C, E4I, F4C, F4I AM29F017B-90 EC, EI, EE, FC, FI, FE, E4C, E4I, E4E, F4C, F4I, F4E AM29F017B-120 AM29F017B-150 Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29F017B 7 DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. Operation register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Am29F017B Device Bus Operations CE# OE# WE# RESET# A0–A20 DQ0–DQ7 Read L L H H AIN DOUT Write L H L H AIN DIN VCC ± 0.5 V X X VCC ± 0.5 V X High-Z TTL Standby H X X H X High-Z Output Disable L H H H X High-Z Hardware Reset X X X L X High-Z Temporary Sector Unprotect (See Note) X X X VID AIN DIN CMOS Standby Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Writing Commands/Command Sequences During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation To write a command or command sequence (which includes programming data to the device and erasing 8 Program and Erase Operation Status Am29F017B Status” for more information, and to each AC Characteristics section for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when CE# and RESET# pins are both held at VCC ± 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# and RESET# pins are both held at VIH. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. In the DC Characteristics tables, ICC3 represents the standby current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VIL, the device enters the TTL standby mode; if RESET# is held at VSS ± 0.5 V, the device enters the CMOS standby mode. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Am29F017B 9 Table 2. Sector Address Table Sector A20 A19 A18 A17 A16 Address Range SA0 0 0 0 0 0 000000h–00FFFFh SA1 0 0 0 0 1 010000h–01FFFFh SA2 0 0 0 1 0 020000h–02FFFFh SA3 0 0 0 1 1 030000h–03FFFFh SA4 0 0 1 0 0 040000h–04FFFFh SA5 0 0 1 0 1 050000h–05FFFFh SA6 0 0 1 1 0 060000h–06FFFFh SA7 0 0 1 1 1 070000h–07FFFFh SA8 0 1 0 0 0 080000h–08FFFFh SA9 0 1 0 0 1 090000h–09FFFFh SA10 0 1 0 1 0 0A0000h–0AFFFFh SA11 0 1 0 1 1 0B0000h–0BFFFFh SA12 0 1 1 0 0 0C0000h–0CFFFFh SA13 0 1 1 0 1 0D0000h–0DFFFFh SA14 0 1 1 1 0 0E0000h–0EFFFFh SA15 0 1 1 1 1 0F0000h–0FFFFFh SA16 1 0 0 0 0 100000h–10FFFFh SA17 1 0 0 0 1 110000h–11FFFFh SA18 1 0 0 1 0 120000h–12FFFFh SA19 1 0 0 1 1 130000h–13FFFFh SA20 1 0 1 0 0 140000h–14FFFFh SA21 1 0 1 0 1 150000h–15FFFFh SA22 1 0 1 1 0 160000h–16FFFFh SA23 1 0 1 1 1 170000h–17FFFFh SA24 1 1 0 0 0 180000h–18FFFFh SA25 1 1 0 0 1 190000h–19FFFFh SA26 1 1 0 1 0 1A0000h–1AFFFFh SA27 1 1 0 1 1 1B0000h–1BFFFFh SA28 1 1 1 0 0 1C0000h–1CFFFFh SA29 1 1 1 0 1 1D0000h–1DFFFFh SA30 1 1 1 1 0 1E0000h–1EFFFFh SA31 1 1 1 1 1 1F0000h–1FFFFFh Note: All sectors are 64 Kbytes in size. 10 Am29F017B Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad- Table 3. Description dress must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See “Command Definitions” for details on using the autoselect mode. Am29F017B Autoselect Codes (High Voltage Method) CE# OE# WE# A20-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0 DQ7-DQ0 Manufacturer ID: AMD L L H X X VID X VIL X VIL VIL 01h Device ID: Am29F017B L L H X X VID X VIL X VIL VIH 3Dh Sector Group Protection Verification L L H Sector Group Address X VID X VIL X VIH VIL 01h (protected) 00h (unprotected) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Sector Group Protection/Unprotection Table 4. Sector Group Addresses The hardware sector group protection feature disables both program and erase operations in any sector. Each sector group consists of four adjacent sectors. Table 4 shows how the sectors are goruped, and the address range that each sector group contains. The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sectors. Sector Group SGA3 0 1 1 SA12–SA15 SGA4 1 0 0 SA16–SA19 Sector group protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Details on this method are provided in a supplement, publication number 21544. Contact an AMD representative to obtain a copy of the appropriate document. SGA5 1 0 1 SA20–SA23 SGA6 1 1 0 SA24–SA27 SGA7 1 1 1 SA28–SA31 The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector group is protected or unprotected. See “Autoselect Mode” for details. A20 A19 A18 Sectors SGA0 0 0 0 SA0–SA3 SGA1 0 0 1 SA4–SA7 SGA2 0 1 0 SA8–SA11 Temporary Sector Group Unprotect This feature allows temporary unprotection of previously protected sectors groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once V ID is removed from the RESET# pin, all the p r ev i ou s ly p ro t ec te d se ct o r gr o u p s a r e protected again. Figure 1 shows the algorithm, and the Temporary Sector/Sector Group Unprotect diagram shows the timing waveforms, for this feature. Am29F017B 11 against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. START RESET# = VID (Note 1) Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Perform Erase or Program Operations RESET# = VIH Temporary Sector Group Unprotect Completed (Note 2) Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. 21195D-7 Notes: 1. All protected sector groups unprotected. Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. 2. All previously protected sector groups are protected once again. Figure 1. Logical Inhibit Temporary Sector Group Unprotect Operation Hardware Data Protection Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. The command sequence requirement of unlock cycles for programming or erasing provides data protection COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/ Erase Resume Commands” for more information on this mode. Reading Array Data The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram. 12 Am29F017B Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Byte Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Am29F017B 13 The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. START Write Program Command Sequence Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms. Data Poll from System Embedded Program algorithm in progress Verify Data? Sector Erase Command Sequence No Yes Increment Address No The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Last Address? Yes Programming Completed 21195D-7 Note: See the appropriate Command Definitions table for program command sequence. Figure 2. Program Operation Chip Erase Command Sequence Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. 14 Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should Am29F017B be reinitiated once the device has returned to reading array data, to ensure data integrity. status bits, just as in the standard program operation. See “Write Operation Status” for more information. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Operation Status” for information on these status bits. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information. Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command. The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. START Write Erase Command Sequence When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 Data Poll from System No Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed 21195D-8 Notes: 1. See the appropriate Command Definitions table for erase command sequence. 2. See “DQ3: Sector Erase Timer” for more information. Am29F017B Figure 3. Erase Operation 15 Table 5. Am29F017B Command Definitions Cycles Bus Cycles (Notes 2–4) Addr Read (Note 5) 1 RA RD Reset (Note 6) 1 XXX F0 4 XXX AA XXX 55 XXX 90 X00 01 4 XXX AA XXX 55 XXX 90 X01 3D SGA X02 XX00 90 XX01 Command Sequence (Note 1) Manufacturer ID Autoselect Device ID (Note 7) Sector Group Protect Verify (Note 8) First Second Data XXX 4 Third Addr Data Addr XXX AA XXX Fourth Data Addr XXX 55 XXX XXX Data Fifth Sixth Addr Data Addr Data Program 4 XXX AA XXX 55 XXX A0 PA PD Chip Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 XXX 10 Sector Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 SA 30 Erase Suspend (Note 9) 1 XXX B0 Erase Resume (Note 10) 1 XXX 30 Legend: 4. Address bits A20–A11 are don’t cares for unlock and command cycles, unless SA or PA required. X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20–A16 select a unique sector. SGA = Address of the sector group to be verified. Address bits A20–A18 select a unique sector group. Notes: 1. See Table 1 for description of bus operations. 5. No unlock or command cycles required when reading array data. 6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 7. The fourth cycle of the autoselect command sequence is a read cycle. 8. The data is 00h for an unprotected sector group and 01h for a protected sector group.See “Autoselect Command Sequence” for more information. 9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 10. The Erase Resume command is valid only during the Erase Suspend mode. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 16 Am29F017B WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Table 6 shows the outputs for Data# Polling on DQ7. Figure 4 shows the Data# Polling algorithm. START DQ7: Data# Polling Read DQ7–DQ0 Addr = VA The Data# Polling bit, DQ7, indicates to the host sys tem whether an Embedded Algor ithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 2 µs, then the device returns to reading array data. DQ7 = Data? No No When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7– DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. The Data# Polling Timings (During Embedded Algorithms) figure in the “AC Characteristics” section illustrates this. DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to “1”; prior to this, the device outputs the “complement,” or “0.” The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. Yes DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Am29F017B 21195D-9 Figure 4. Data# Polling Algorithm 17 RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/BY#. The timing diagrams for read, reset, program, and erase shows the relationship of RY/BY# to other signals. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 2 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. 18 The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the “AC Characteristics” section for the timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6. Figure 5 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 5 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and Am29F017B the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 5). erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 6 shows the outputs for DQ3. START Read DQ7–DQ0 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Read DQ7–DQ0 (Note 1) Toggle Bit = Toggle? No Yes Under both these conditions, the system must issue the reset command to return the device to reading array data. No DQ5 = 1? Yes DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 µs. See also the “Sector Erase Command Sequence” section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector Read DQ7–DQ0 Twice Toggle Bit = Toggle? (Notes 1, 2) No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. Am29F017B 21195D-10 Figure 5. Toggle Bit Algorithm 19 Table 6. Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Write Operation Status DQ7 (Note 1) DQ6 DQ5 (Note 2) DQ3 DQ2 (Note 1) RY/BY# DQ7# Toggle 0 N/A No toggle 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Reading within Erase Suspended Sector 1 No toggle 0 N/A Toggle 1 Reading within Non-Erase Suspended Sector Data Data Data Data Data 1 Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0 Notes: 1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information. 20 Am29F017B ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C Commercial (C) Devices Ambient Temperature with Power Applied. . . . . . . . . . . . . . –55°C to +125°C Industrial (I) Devices Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . –2.0 V to 7.0 V A9, OE#, RESET# (Note 2) . . . . . –2.0 V to 12.5 V All other pins (Note 1) . . . . . . . . . . –2.0 V to 7.0 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC voltage on output and I/O pins is VCC + 0.5 V. During voltage transitions, outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 7. Ambient Temperature (TC) . . . . . . . . . . .0°C to +70°C Ambient Temperature (TC) . . . . . . . . .–40°C to +85°C Extended (E) Devices Ambient Temperature (TA) . . . . . . . .–55°C to +125°C VCC Supply Voltages VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V VCC for ± 10% all devices . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. 2. Minimum DC input voltage on A9, OE#, RESET# pins is –0.5V. During voltage transitions, A9, OE#, RESET# pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC input voltage on A9, OE#, and RESET# is 12.5 V which may overshoot to 13.5 V for periods up to 20 ns. 3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. Stresses greater than those listed in this section may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns 20 ns VCC +2.0 V VCC +0.5 V 20 ns +0.8 V –0.5 V –2.0 V 2.0 V 20 ns 20 ns 20 ns 21195D-11 21195D-12 Figure 6. Maximum Negative Overshoot Waveform Figure 7. Am29F017B Maximum Positive Overshoot Waveform 21 DC CHARACTERISTICS TTL/NMOS Compatible Parameter Symbol Parameter Description Test Description Min Typ ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ICC1 VCC Read Current (Note 1) CE# = VIL, OE# = VIH ICC2 VCC Write Current (Notes 3, 4) CE# = VIL, OE# = VIH ICC3 VCC Standby Current (Note 2) CE# = VIH, RESET# = VIH ICC4 VCC Standby Current (Note 2) RESET# = VIL 0.4 VIL Input Low Level VIH Max Unit ±1.0 µA 50 µA ±1.0 µA 40 mA 40 60 mA 0.4 1.0 mA 1.0 mA –0.5 0.8 V Input High Level 2.0 VCC + 0.5 V VID Voltage for Autoselect and Sector VCC = 5.0 V Protect 11.5 12.5 V 0.45 V VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min VOH Output High Level IOH = –2.5 mA, VCC = VCC Min VLKO Low VCC Lock-out Voltage 25 2.4 V 3.2 4.2 V Max Unit ±1.0 µA 50 µA Cmos Compatible Parameter Symbol Parameter Description Test Description ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V Typ ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA ICC1 VCC Read Current (Note 1) CE# = VIL, OE# = VIH 25 40 mA ICC2 VCC Write Current (Notes 3, 4) CE# = VIL, OE# = VIH 30 40 mA ICC3 VCC Standby Current (Notes 2, 5) CE# = VCC ± 0.5 V, RESET# = VCC ± 0.5 V 1 5 µA ICC4 VCC Standby Current (Notes 2, 5) RESET# = VSS ± 0.5 V 1 5 µA VIL Input Low Level –0.5 0.8 V VIH Input High Level 0.7x VCC VCC + 0.3 V VID Voltage for Autoselect and Sector Protect 11.5 12.5 V VOL Output Low Voltage 0.45 V VOH1 VOH2 VLKO Output High Voltage VCC = 5.0 V IOL = 12 mA, VCC = VCC Min IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V IOH = –100 µA, VCC = VCC Min VCC – 0.4 V Low VCC Lock-out Voltage 3.2 Notes for DC Characteristics (both tables): 1. The ICC current is typically less than 1 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Program or Embedded Erase algorithm is in progress. 4. Not 100% tested. 5. For CMOS mode only ICC3, ICC4 = 20 µA at extended temperature (>+85°C). 22 Min Am29F017B 4.2 V TEST CONDITIONS Table 7. 5.0 V All speed options Test Condition 2.7 kΩ Device Under Test Test Specifications Output Load CL 6.2 kΩ 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 100 pF Input Rise and Fall Times 20 ns 0.45–2.4 V Input timing measurement reference levels 0.8 V Output timing measurement reference levels 2.0 V Input Pulse Levels Note: Diodes are IN3064 or equivalent 21195D-13 Figure 8. Unit Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) KS000010-PAL Am29F017B 23 AC CHARACTERISTICS Read-only Operations Parameter Symbol JEDEC Std tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tGLQV tOE Output Enable to Output Delay tOEH Output Enable Hold Time (Note 1) Speed Options Test Setup Parameter Description -75 -90 -120 -150 Unit Min 70 90 120 150 ns CE# = VIL OE# = VIL Max 70 90 120 150 ns OE# = VIL Max 70 90 120 150 ns Max 40 40 50 55 ns Read Min 0 0 0 0 ns Toggle and Data# Polling Min 10 10 10 10 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 20 20 30 35 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 20 20 30 35 ns tAXQX tOH Output Hold Time From Addresses CE# or OE# Whichever Occurs First Min 0 0 0 0 ns RESET# Pin Low to Read Mode (Note 1) Max 20 20 20 20 µs tReady Notes: 1. Not 100% tested. 2. See Figure 8 and Table 7for test specifications. tRC Addresses Stable Addresses tACC CE# tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V 21195D-14 Figure 9. 24 Read Operation Timings Am29F017B AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description Test Setup All Speed Options Unit tREADY RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 µs tREADY RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH RESET# High Time Before Read (See Note) Min 50 ns tRB RY/BY# Recovery Time Min 0 ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP 21195D-15 Figure 10. RESET# Timings Am29F017B 25 AC CHARACTERISTICS Erase/Program Operations Parameter Speed Options JEDEC Std Parameter Description -75 -90 -120 -150 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 150 ns tAVWL tAS Address Setup Time Min tWLAX tAH Address Hold Time Min 40 45 50 50 ns tDVWH tDS Data Setup Time Min 40 45 50 50 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns Read Recover Time Before Write (OE# high to WE# low) Min 0 ns 0 ns tGHWL tGHWL tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min tWHWL tWPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs Typ 1 sec tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Max 8 sec 50 µs tVCS VCC Set Up Time (Note 1) Min tBUSY WE# to RY/BY# Valid Min Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 26 Am29F017B 40 40 45 40 50 50 50 60 ns ns AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses 555h Read Status Data (last two cycles) PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH A0h Data PD Status tBUSY DOUT tRB RY/BY# tVCS VCC Note: PA = program address, PD = program data, DOUT is the true data at the program address. 21195D-16 Figure 11. Program Operation Timings Am29F017B 27 AC CHARACTERISTICS Erase Command Sequence (last two cycles) tAS tWC Addresses Read Status Data 2AAh VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Note: SA = Sector Address. VA = Valid Address for reading status data. 21195D-17 Figure 12. 28 Chip/Sector Erase Operation Timings Am29F017B AC CHARACTERISTICS tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ0–DQ6 Status Data Status Data Valid Data True High Z Valid Data True tBUSY RY/BY# Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 21195D-18 Figure 13. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ6/DQ2 tBUSY Valid Status Valid Status (first read) (second read) Valid Status Valid Data (stops toggling) RY/BY# Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 21195D-19 Figure 14. Toggle Bit Timings (During Embedded Algorithms) Am29F017B 29 AC CHARACTERISTICS Enter Embedded Erasing Erase Suspend Erase Resume Erase Suspend Program Erase Suspend Read Erase WE# Enter Erase Suspend Program Erase Suspend Read Erase Complete Erase DQ6 DQ2 Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended sector. 21195D-20 Figure 15. DQ2 vs. DQ6 Temporary Sector Unprotect Parameter JEDEC Std Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotect All Speed Options Unit Min 500 ns Min 4 µs Note: Not 100% tested. 12 V RESET# 0 or 5 V 0 or 5 V tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRSP RY/BY# 21195D-21 Figure 16. 30 Temporary Sector Group Unprotect Timing Diagram Am29F017B AC CHARACTERISTICS Erase and Program Operations Alternate CE# Controlled Writes Parameter Symbol Speed Options JEDEC Std Parameter Description -75 -90 -120 -150 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 150 ns tAVEL tAS Address Setup Time Min tELAX tAH Address Hold Time Min 40 45 50 50 ns tDVEH tDS Data Setup Time Min 40 45 50 50 ns tEHDX tDH Address Hold Time Min 0 ns tGHEL tGHEL Read Recover Time Before Write Min 0 ns tWLEL tWS CE# Setup Time Min 0 ns tEHWH tWH CE# Hold Time Min 0 ns tELEH tCP Write Pulse Width Min tEHEL tCPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs Typ 1 sec tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Max 8 sec 0 40 45 ns 50 50 ns Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Am29F017B 31 AC CHARACTERISTICS XXX for program XXX for erase PA for program SA for sector erase XXX for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tCP CE# tWS tWHWH1 or 2 tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence. 21195D-22 Figure 17. 32 Alternate CE# Controlled Write Operation Timings Am29F017B ERASE AND PROGRAMMING PERFORMANCE Parameter Typ (Note 1) Max (Note 2) Unit Sector Erase Time 1 8 sec Chip Erase Time 32 256 sec Byte Programming Time 7 300 µs 14.4 43.2 sec Chip Programming Time (Note 3) Comments Excludes 00h programming prior to erasure (Note 4) Excludes system-level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 4.5 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set DQ5 = 1. See the section on DQ5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 6 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Input Voltage with respect to VSS on I/O pins VCC Current Min Max –1.0 V VCC + 1.0 V –100 mA +100 mA Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time. TSOP PIN CAPACITANCE Parameter Symbol Parameter Description Test Conditions Min Max Unit 6 7.5 pF Input Capacitance VIN = 0 COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF CIN Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time Am29F017B 33 PHYSICAL DIMENSIONS TS 040—40-Pin Standard Thin Small Outline Package (measured in millimeters) Dwg rev AA; 10/99 34 Am29F017B PHYSICAL DIMENSIONS TSR040—40-Pin Reverse Thin Small Outline Package (measured in millimeters) Dwg rev AA; 10/99 Am29F017B 35 PHYSICAL DIMENSIONS TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters) Dwg rev AA; 10/99 36 Am29F017B PHYSICAL DIMENSIONS TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters) Dwg rev AA; 10/99 Am29F017B 37 REVISION SUMMARY Revision B (January 1998) Revision B+3 (August 1998) Global Global Made formatting and layout consistent with other data sheets. Used updated common tables and diagrams. The Am29F017B is now available in 40-pin standard and reverse TSOP packages. The online version has slightly modified formatting. DC Characteristics Revision B+1 (January 1998) Moved the VCCmax test condition for ICC specifications to notes. Reset Command Deleted paragraph referring to RESET# waveforms. Revision C (January 1999) Global AC Characteristics—Read-only Operations Deleted note referring to output driver disable time. Updated for CS39S process technology. Distinctive Characteristics Figure 16—Temporary Sector Group Unprotect Timings Added: ■ 20-year data retention at 125°C Corrected title to indicate “sector group.” — Reliable operation for the life of the system Revision B+2 (April 1998) Ordering Information Global Added -70 speed option, deleted -75 speed option. Valid Combinations: Eliminated the extended temperature range option for Am29F017B-70. Distinctive Characteristics DC Characteristics—CMOS Compatible Changed minimum 100K write/erase cycles guaranteed to 1,000,000. ICC3, ICC4: Added Note 5, “For CMOS mode only ICC3, ICC4 = 20 µA at extended temperature (>+85°C)”. Ordering Information Revision C+1 (March 23, 1999) Added extended temperature availability. Operating Ranges Operating Ranges The temperature ranges are now specified as ambient. Added extended temperature range. Revision C+2 (May 17, 1999) DC Characteristics, CMOS Compatible Corrected the CE# and RESET# test conditions for ICC3 and ICC4 to VCC ±0.5 V. AC Characteristics Erase/Program Operations; Erase and Program Operations Alternate CE# Controlled Writes: Corrected the notes reference for tWHWH1 and tWHWH2. These parameters are 100% tested. Corrected the note reference for tVCS. This parameter is not 100% tested. Temporary Sector Unprotect Table Added note reference for tVIDR. This parameter is not 100% tested. Erase and Programming Performance Changed minimum 100K program and erase cycles guaranteed to 1,000,000. Product Seletor Guide Corrected the tOE specification for the 150 ns speed option to 55 ns. Operating Ranges VCC Supply Voltages: Added VCC for ± 5% devices. Changed “VCC for± all devices” to “VCC for ± 10% all devices.” Revision D (November 16, 1999) Distinctive Characteristics Package Options: Added 40-pin TSOP. AC Characteristics—Figure 11. Program Operations Timing and Figure 12. Chip/Sector Erase Operations Deleted tGHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations. 38 Am29F017B Trademarks Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Am29F017B 39