Am7943 Subscriber Line Interface Circuit DISTINCTIVE CHARACTERISTICS Programmable constant-current feed Current gain = 200 Programmable loop-detect threshold Low power Standby state Performs polarity reversal Ground-key detector Tip Open state for ground-start lines –19 V to –58 V battery operation Two-wire impedance set by single external impedance On-hook transmission On-chip ring relay driver and relay snubber circuit On-chip Thermal Management (TMG) feature Ideal for DLC and PABX applications BLOCK DIAGRAM TMG Ring Relay Driver RINGOUT C1 A(TIP) C2 Input Decoder and Control Ground-Key Detector HPA HPB C3 E0 E1 Two-Wire Interface DET RSN Signal Transmission VTX Off-Hook Detector RD B(RING) DA DB VBAT Power-Feed Controller RDC CAS Ring-Trip Detector BGND VCC VEE AGND/DGND Publication# 080136 Rev: D Issue Date: October 1999 Amendment: /0 ORDERING INFORMATION Standard Products Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am7943 –1 J C TEMPERATURE RANGE C = Commercial (0°C to 70°C)* PACKAGE TYPE J = 32-pin Plastic Leaded Chip Carrier (PL 032) PERFORMANCE GRADE –1 = Performance Grading –2 = Performance Grading DEVICE NUMBER/DESCRIPTION Am7943 Subscriber Line Interface Circuit Valid Combinations Valid Combinations Am7943 –1 –2 JC Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on Legerity’s standard military– grade products. Note: * Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is guaranteed by characterization and periodic sampling of production units. 2 Am7943 Data Sheet CONNECTION DIAGRAM Top View VCC NC BGND B(RING) A(TIP) 4 3 2 1 32 31 30 DB NC 32-Pin PLCC RINGOUT 6 28 DA NC 7 27 RD TMG 8 26 HPB VBAT 9 25 NC C3 10 24 HPA E1 11 23 VTX C2 12 22 VEE DET 13 21 RSN 19 20 AGND/DGND 16 17 18 NC 15 CAS 14 RDC TP E0 29 NC 5 C1 TP Notes: 1. Pin 1 is marked for orientation. 2. TP is a thermal conduction pin tied to substrate. 3. NC = No Connect SLIC Products 3 PIN DESCRIPTIONS Pin Names 4 Type Description AGND/DGND Gnd Analog and Digital ground A(TIP) Output Output of A(TIP) power amplifier BGND Gnd Battery (power) ground B(RING) Output Output of B(RING) power amplifier C3–C1 Input Decoder. TTL compatible. C3 is MSB and C1 is LSB. CAS Capacitor Anti-saturation pin for capacitor to filter reference voltage when operating in antisaturation region. DA Input Ring-trip negative. Negative input to ring-trip comparator. DB Input Ring-trip positive. Positive input to ring-trip comparator. DET Output Switchhook detector. When enabled, a logic Low indicates the selected detector is tripped. The detector is selected by the logic inputs (C3–C1, E1–E0). The output is opencollector with a built-in 15 kΩ pull-up resistor. E0 Input DET Enable. A logic High enables DET. A logic Low disables DET. (DET = Logic High). (PLCC only) E1 Input Ground-Key Enable. E1 = Low connects the ground-key or ring-trip detector to DET. E1 = High connects the off-hook or ring-trip detector to DET. (PLCC only) HPA Capacitor High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor. HPB Capacitor High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor. RD Resistor Detector resistor. Threshold modification and filter point for the off-hook detector. RDC Resistor DC feed resistor. Connection point for the DC feed current programming network. The other end of the network connects to the receiver summing node (RSN). The sign of VRDC is negative for normal polarity and positive for reverse polarity. RINGOUT Output Ring Relay Driver. Open-collector driver with emitter internally connected to BGND. RSN Input Receive Summing Node. The metallic current (AC and DC) between A(TIP) and B(RING) is equal to 200 times the current into this pin. The networks that program receive gain, two-wire impedance, and feed current all connect to this node. TMG — Thermal management. A resistor connected from this pin to VBAT reduces the on-chip power dissipation in the normal polarity, Active state only. Refer to Table 2. TP Thermal Thermal pin. Connection for heat dissipation. Internally connected to substrate (VBAT). Leave as open circuit or connected to VBAT. In both cases, the TP pins can connect to an area of copper on the board to enhance heat dissipation. VBAT Battery Battery supply VCC Power +5 V power supply VEE Power –5 V power supply VTX Output Transmit Audio. This output is a unity gain version of the A(TIP) and B(RING) metallic voltage. VTX also sources the two-wire input impedance programming network. Am7943 Data Sheet ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage temperature . . . . . . . . . . . . –55°C to +150°C Commercial (C) Devices VCC with respect to AGND/DGND . . .–0.4 V to +7.0 V Ambient temperature . . . . . . . . . . . . . . 0°C to +70°C* VEE with respect to AGND/DGND . . .+0.4 V to –7.0 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V VBAT with respect to AGND/DGND: Continuous . . . . . . . . . . . . . . . . . . +0.4 V to –70 V 10 ms . . . . . . . . . . . . . . . . . . . . . . +0.4 V to –75 V VEE . . . . . . . . . . . . . . . . . . . . . . . . –4.75 V to –5.25 V BGND with respect to AGND/DGND . . . .+3 V to –3 V A(TIP) or B(RING) to BGND: Continuous . . . . . . . . . . . . . . . . . . . .–70 V to +1 V 10 ms (f = 0.1 Hz) . . . . . . . . . . . . . . . –70 V to +5 V 1 ms (f = 0.1 Hz) . . . . . . . . . . . . . . . . –80 V to +8 V 10 µs (f = 0.1 Hz) . . . . . . . . . . . . . . –90 V to +12 V Current from A(TIP) or B(RING) . . . . . . . . . . . .±150 mA Current from TMG . . . . . . . . . . . . . . . . . . . . . 100 mA Voltage on RINGOUT: During transient . . . . . . . . . . . . . . BGND to +10 V During steady state . . . . . . . . . . . . . BGND to +7 V VBAT . . . . . . . . . . . . . . . . . . . . . . . . . –19 V to –56.5 V AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V BGND with respect to AGND/DGND . . . . . . . . . . . . –100 mV to +100 mV Load resistance on VTX to ground . . . . . . . 10 kΩ min Operating Ranges define those limits between which device functionality is guaranteed. * Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is guaranteed by characterization and periodic sampling of production units. Current through relay drivers . . . . . . . . . . . . . . 60 mA DA and DB inputs Voltage on ring-trip inputs . . . . . . . . . . .VBAT to 0 V Current into ring-trip inputs . . . . . . . . . . . . . .±10 mA C3–C1, E0, E1 to AGND/DGND . . . . . . . . . . –0.4 V to VCC +0.4 V Maximum power dissipation, TA = 85°C No heat sink (see note): In 32-pin PLCC package. . . . . . . . . . . . . . . . 1.4 W Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .θJA In 32-pin PLCC package. . . . . . . . . . . .43°C/W typ Note: Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165°C. The device should never be exposed to this temperature. Operation above 145°C junction temperature may degrade device reliability. See the SLIC Packaging Considerations for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. SLIC Products 5 ELECTRICAL CHARACTERISTICS Description Test Conditions (See Note 1) Min Analog (VTX) output impedance –35 –40 –40°C to +85°C 300 Hz to 3.4 kHz 1 Unit Note Ω +35 +40 Longitudinal impedance at A or B Overload level Max 3 Analog (VTX) output offset Analog (RSN) input impedance Typ mV 20 — 4 4 35 Ω +2.5 Vpk 2a 4-wire and 2-wire Active state –2.5 On-hook, RLAC = 900 Ω, Active or OHT state 0.95 Vrms 2b 26 dB 4, 8 Transmission Performance 2-wire return loss (See Test Circuit D) 200 to 3400 Hz Longitudinal Balance (2-Wire and 4-Wire, See Test Circuit C); RL = 740 Ω at VBAT = 48 V Longitudinal to metallic L-T, L-4 0°C to +70°C –40°C to +85°C –1* –2 –2 –2 52 63 58 58 1 kHz to 3.4 kHz normal polarity 0°C to +70°C normal polarity –40°C to +85°C reverse polarity –1* –2 –2 –2 52 58 54 54 200 Hz to 1 kHz normal polarity normal polarity reverse polarity Longitudinal signal generation 4-L 300 Hz to 800 Hz normal polarity 42 Longitudinal current per pin Active state and OHT state 27 — — 4 — dB 35 — — 4 — mArms Insertion Loss (2- to 4-Wire and 4- to 2-Wire, See Test Circuits A and B) BAT = –48 V, RL = 900 Ω Gain accuracy Gain accuracy, OHT state Variation with frequency Gain tracking 0 dBm, 1 kHz 0°C to +70°C –40°C to +85°C –0.15 –0.20 +0.15 +0.20 –10 dBm, on-hook, RLAC = 900 Ω –0.5 +0.5 300 to 3400 Hz relative to 1 kHz — — 4 4 dB 0°C to +70°C –40°C to +85°C +7 dBm to –55 dBm Reference: 0 dBm — — 4 –0.10 –0.15 +0.10 +0.15 –0.1 +0.1 –0.15 –0.20 +0.15 +0.20 — 3 4 –0.1 –0.15 +0.1 +0.15 — 3 4 4 — Balance Return Signal (4- to 4-Wire, See Test Circuit B) BAT = –48 V, RL = 900 Ω Gain accuracy Variation with frequency Gain tracking Group delay 0 dBm, 1 kHz 0°C to +70°C –40°C to +85°C 300 to 3400 Hz relative to 1 kHz 0°C to +70°C –40°C to +85°C +3 dBm to –55 dBm Reference: 0 dBm 0°C to +70°C –40°C to +85°C f = 1 kHz Am7943 Data Sheet — — 3, 4 4 +0.1 +0.15 4 Note: * P.G. = Performance Grade 6 –0.1 –0.15 dB µs 4, 8 ELECTRICAL CHARACTERISTICS (continued) Description Test Conditions (See Note 1) Min Typ Max Unit –64 –55 –50 –40 dB Note Total Harmonic Distortion (2- to 4-Wire or 4- to 2-Wire) (See Test Circuits A and B) BAT = –48 V, RL = 900 Ω Harmonic distortion 300 Hz to 3400 Hz 2-wire level = 0 dBm 2-wire level = +7 dBm Idle Channel Noise (2-wire and 4-wire) C-message weighted noise 0°C to +85°C –40°C to 0°C +7 +7 +10 +12 dBrnC — 4 Psophometric weighted noise 0°C to +85°C –40°C to 0°C –83 –80 –78 dBmp — 4 29.0 Line Characteristics, Active State (See Figure 1) Short loops, Active state BAT = –43 V, RLDC = 600 Ω BAT = –48 V, RLDC = 600 Ω 25.0 27.0 Long loops, Active state BAT = –43 V, RLDC = 1.4 kΩ BAT = –48 V, RLDC = 1.9 kΩ 20.0 18.0 23.8 20.4 OHT state BAT = –48 V, RLDC = 600 Ω 16.0 18.0 20.0 Standby state V BAT – 3 V I L = -----------------------------R L + 1800 0.7IL IL 1.3IL 15.0 17.4 TA = 25°C RL = 600 Ω, BAT = –48 V TA = 70oC Loop current Tip Open, RL = 0 Disconnect, RL = 0 Tip Open, Bwire to GND Tip Open, Bwire = VBAT + 6 V ILLIM (Itip + Iring) Tip and ring shorted to GND Ground-start signaling (tip voltage) Active state RTIP to –48 V = 7.0 kΩ RRING to GND = 100 Ω –7.5 Active and OHT BAT = –48 V 40.5 Open circuit voltage mA — — 30 30 100 100 — — µA µA mA mA 100 130 mA –5.0 V 4 — — 42.0 Power Dissipation, Normal Loop Polarity, BAT = –48 V On hook, Open Circuit state On hook, OHT state On hook, Active state RTMG = Open RTMG = 1700 Ω On hook, Standby state 25 70 120 210 160 195 260 280 35 85 Off hook, OHT state RL = 300 Ω, RTMG = ∞ BAT = –48 V 735 1050 Off hook, Active state RL = 300 Ω, RTMG = ∞ BAT = –48 V 1.25 1.45 RL = 300 Ω, RTMG = ∞ 0.57 0.85 RL = 600 Ω, TA = 25°C 0.68 1.0 Off hook, Standby state SLIC Products mW W 7 ELECTRICAL CHARACTERISTICS (continued) Description Test Conditions (See Note 1) Min Typ Max VCC on-hook supply current Open Circuit state OHT state Standby state Active state 1.7 4.9 2.2 6.3 2.5 7.5 3.0 8.5 VEE on-hook supply current Open Circuit state OHT state Standby state Active state 0.7 2.0 0.77 2.1 2.0 3.5 2.0 5.0 VBAT on-hook supply current Open Circuit state OHT state Standby state Active state 0.18 1.9 0.45 4.2 1.0 4.7 1.5 5.7 Unit Note Supply Currents, BAT = –48 V mA Power Supply Rejection Ratio (VRIPPLE = 50 mVrms), Active Normal State VCC 50 Hz to 3400 Hz 33 40 VEE 50 Hz to 3400 Hz 29 35 VBAT 50 Hz to 3400 Hz 30 50 Effective internal resistance CAS pin to GND 85 170 RFI rejection 100 kHz to 30 MHz (See Figure E) dB 5 255 kΩ 4 1.0 mVrms 4 +10 % Off-Hook Detector Current threshold 375I DET = -------RD –10 Ground-Key Detector Thresholds, Active State, BAT = –48 V Ground-key resistance threshold B(RING) to GND Ground-key current threshold B(RING) to GND 2.0 5.0 10.0 kΩ 9 mA –0.5 –0.05 µA –50 0 Ring-Trip Detector Input Bias current Offset voltage Source resistance = 2 MΩ +50 mV Logic Inputs (C3–C1, E0, E1) Input High voltage 2.0 Input Low voltage Input High current 0.8 All inputs except C3 and E1 Input C3 Input E1 Input Low current –75 –75 –75 40 200 45 –0.4 V µA mA Logic Output (DET) Output Low voltage IOUT = 0.8 mA 0.4 Output High voltage IOUT = –0.1 mA V 2.4 Relay Driver Output (RINGOUT) On voltage 35 mA sink Off leakage VOH = +5 V Zener breakover 100 µA Zener on voltage 30 mA 8 +0.25 6 +0.4 V 100 µA 7.2 V 10 Am7943 Data Sheet 6 RELAY DRIVER SCHEMATIC RINGOUT BGND SWITCHING CHARACTERISTICS (32-pin PLCC only) Symbol tgkde Parameter Test Conditions E1 Low to DET High (E0 = 1) E1 Low to DET Low (E0 = 1) Ground-Key Detect state RL open, RG connected (See Figure G) Temperature Range Min Typ Max 0°C to 70°C –40° to +85°C 3.8 4.0 0°C to 70°C –40° to +85°C 1.1 1.6 0°C to 70°C –40° to +85°C 1.1 1.6 tgkdd E0 High to DET Low (E1 = 0) tgkd0 E0 Low to DET High (E1 = 0) 0°C to 70°C –40° to +85°C 3.8 4.0 tshde E1 High to DET Low (E0 = 1) 0°C to 70°C –40° to +85°C 1.2 1.7 0°C to 70°C –40° to +85°C 3.8 4.0 0°C to 70°C –40° to +85°C 1.1 1.6 0°C to 70°C –40° to +85°C 3.8 4.0 E1 High to DET High (E0 = 1) tshdd E0 High to DET Low (E1 = 1) tshd0 E0 Low to DET High (E1 = 1) Switchhook Detect state RL = 600 Ω, RG open (See Figure F) SLIC Products Unit Note µs 4 9 SWITCHING WAVEFORMS E1 to DET E1 DET tgkde tshde tgkde tshde E0 to DET E1 E0 DET tshdd tgkdd tshd0 Note: All delays measured at 1.4 V level. 10 Am7943 Data Sheet tgkd0 Notes: 1. Unless otherwise noted, test conditions are VCC = +5 V, VEE = –5 V, CHP = 0.33 µF, RDC1 = RDC2 = 9.26 kΩ, CDC = 0.33 µF, Rd = 35.4 kΩ, CCAS = 0.33 µF, no fuse resistors, BAT = –48 V, RL = 900 Ω, and RTMG = 1700 Ω. 2. a. Overload level is defined when THD = 1%. b. Overload level is defined when THD = 1.5%. 3. Balance return signal is the signal generated at VTX by VRX. This specification assumes the two-wire AC load impedance matches the programmed impedance. 4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests. 5. This parameter is tested at 1 kHz with a termination impedance of 900 Ω and an RL of 600 Ω in production. Performance at other frequencies is guaranteed by characterization. 6. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only. 7. Assumes the following ZT networks: (900 Ω): VTX RSN 90 kΩ 90 kΩ 150 pF (600 Ω): VTX RSN 60 kΩ 60 kΩ 150 pF 8. Group delay can be considerably reduced by using a ZT network such as that shown in Note 7 above. The network reduces the group delay to less than 2 µs. The effect of group delay on the linecard performance may be compensated for by using the QSLAC™ or DSLAC™ device. Table 1. SLIC Decoding DET Output State C3 C2 C1 Two-wire Status E1 = 1 E1 = 0 0 0 0 0 Open Circuit Ring trip Ring trip 1 0 0 1 Ringing Ring trip Ring trip 2 0 1 0 Active Loop detector Ground key 3 0 1 1 On-hook TX (OHT) Loop detector Ground key 4 1 0 0 Tip Open Loop detector Ground key 5 1 0 1 Standby Loop detector Ground key 6 1 1 0 Active Polarity Reversal Loop detector Ground key 7 1 1 1 OHT Polarity Reversal Ground key Loop detector Note: E0 High enables the DET pin. SLIC Products 11 Table 2. User-Programmable Components Z T = 200 ( Z 2WIN – 2R F ) ZT is connected between the VTX and RSN pins. The fuse resistors are RF and Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. 200 • Z T ZL Z RX = ----------- • ------------------------------------------------G 42L Z T + 200 ( Z L + 2R F ) ZRX is connected from VRX to RSN. ZT is defined above and G42L is the desired receive gain. 500 R DC1 + R DC2 = ------------I LOOP RDC1, RDC2, and CDC form the network connected to the RDC pin. RDC1 and RDC2 are approximately equal. ILOOP is the desired loop current in the constant-current region. R DC1 + R DC2 C DC = 1.5 ms • -------------------------------R DC1 • R DC2 375 0.5 ms R D = --------- , C D = ----------------IT RD RD and CD form the network connected from RD to –5 V and IT is the threshold current between on hook and off hook. 500 V • 0.66I OHT = ------------------------------R DC1 + R DC2 OHT loop current (constant-current region) 1 C CAS = ----------------------------5 3.4 • 10 π f c CCAS is the regulator filter capacitor and fc is the desired filter cut-off frequency. Thermal Management Equations (Normal Active and Tip Open states) RTMG is connected from TMG to VBAT and is used to limit power dissipation within the SLIC in Normal Active and Tip Open states only. V BAT – 6 V R TMG = ---------------------------I LOOP 2 ( V BAT – 6 V – ( IL • R L ) ) P RTMG = --------------------------------------------------------------R TMG Power dissipated in the thermal management resistor, RTMG, during Active and Tip Open states 2 P SLIC = V BAT • I L – P RTMG – R L ( I L ) + 0.12 W Power dissipated in the SLIC while in Active and Tip Open states Thermal Management Equations (Polarity Reverse State) Note: SLIC die temperature should not exceed 140oC. 2 P SLIC = V BAT • I L – R L ( I L ) + 0.12 W Power dissipated in the SLIC while in the Polarity Reverse state T SLIC = P SLIC • θ JA + T Ambient Total die temperature Theta JA ( θ JA ) PLCC = 43 ° C ⁄ watt Thermal impedance of the 32-pin plastic leaded chip carrier package 12 Am7943 Data Sheet DC FEED CHARACTERISTICS 3 4 VBAT = 51.3 V 3 2 VBAT = 47.3 V 1 Active state RDC1 + RDC2 = RDC = 18.52 kΩ Notes: 1. Constant-current region: Active state, OHT state 500I L = --------R DC 2 500 I L = --- • ---------3 R DC OHT state, 2. Anti-sat (battery tracking) turn-on: V AB = 1.017 V BAT – 10.7 3. Open circuit voltage: V AB = 1.017 V BAT – 6.3 4. Anti-sat (battery tracking) region: R DC V AB = 1.017 V BAT – 6.3 – IL --------120 a. VA–VB (VAB) Voltage vs. Loop Current (Typical) SLIC Products 13 DC FEED CHARACTERISTICS (continued) RDC1 + RDC2 = RDC = 18.52 kΩ VBAT = 47.3 V b. Loop Current vs. Load Resistance (Typical) A a RL RSN IL SLIC RDC1 b RDC2 B RDC Feed current programmed by RDC1 and RDC2 c. Feed Programming Figure 1. 14 DC Feed Characteristics Am7943 Data Sheet CDC TEST CIRCUITS RL 2 RT SLIC RL 2 VTX SLIC AGND VAB VL A(TIP) VTX A(TIP) VAB RT AGND RL RRX B(RING) RRX RSN B(RING) RSN VRX IL4-2 = –20 log (VAB / VRX) IL2-4 = –20 log (VTX / VAB) BRS = 20 log (VTX / VRX) B. Four- to Two-Wire Insertion Loss and Balance Return Signal A. Two- to Four-Wire Insertion Loss ZD 1 -------<< RL ωC S1 A(TIP) A(TIP) VTX RL 2 VTX SLIC R C VL RT VAB VM VS VL SLIC RT1 AGND R RL 2 ZIN S2 RT2 RRX RSN B(RING) VRX B(RING) RSN RRX S2 Open, S1 Closed L-T Long. Bal. = 20 log (VAB / VL) L-4 Long. Bal. = 20 log (VTX / VL) Note: ZD is the desired impedance (e.g., the characteristic impedance of the line). S2 Closed, S1 Open 4-L Long. Sig. Gen. = 20 log (VL / VRX) C. Longitudinal Balance CT1 RL = –20 log (2 VM / VS ) D. Two-Wire Return Loss Test Circuit SLIC Products 15 TEST CIRCUITS (continued) L1 200 Ω RF1 50 Ω C1 A(TIP) CAX 33 nF RF2 50 Ω 200 Ω B(RING) HF GEN L2 50 Ω CBX 33 nF C2 VTX SLIC under test 1.5 Vrms 80% Amplitude Modulated 100 kHz to 30 MHz E. RFI Test Circuit VCC 6.2 kΩ A(TIP) A(TIP) DET 15 pF RL = 600 Ω B(RING) E1 F. Loop-Detector Switching 16 Am7943 Data Sheet B(RING) RG RG: 2 kΩ at VBAT = –48 V G. Ground-Key Switching TEST CIRCUITS (continued) +5 V –5 V VEE VCC DA RD DB RD 2.2 nF VTX VTX A(TIP) A(TIP) HPA RT CHP RSN HPB B(RING) B(RING) 2.2 nF RRX VRX RDC1 RDC2 RDC CDC RINGOUT AGND/ DGND BGND E1 C3 C2 C1 VBAT BAT D6 DET TMG RTMG 1700 Ω CAS BATTERY GROUND CCAS ANALOG GROUND DIGITAL GROUND H. Am7943 Test Circuit SLIC Products 17 PHYSICAL DIMENSION PL032 .447 .453 .485 .495 .009 .015 .585 .595 .042 .056 .125 .140 Pin 1 I.D. .080 .095 .547 .553 SEATING PLANE .400 REF. .490 .530 .013 .021 .050 REF. .026 .032 TOP VIEW SIDE VIEW 16-038FPO-5 PL 032 DA79 6-28-94 ae REVISION SUMMARY Revision A to B • Minor changes were made to the data sheet style and format to conform to Legerity standards. Revision B to Revision C • In Pin Description table, inserted/changed TP pin description to: “Thermal pin. Connection for heat dissipation. Internally connected to substrate (VBAT). Leave as open circuit or connected to VBAT. In both cases, the TP pins can connect to an area of copper on the board to enhance heat dissipation.” • Minor changes were made to the data sheet style and format to conform to Legerity standards. Revision C to Revision D • The physical dimension (PL032) was added to the Physical Dimension section. • Deleted the Ceramic DIP and Plastic DIP packages and references to them. • Updated the Pin Description table to correct inconsistencies. 18 Am7943 Data Sheet The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in Legerity's Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of Legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. Legerity reserves the right to discontinue or make changes to its products at any time without notice. © 1999 Legerity, Inc. All rights reserved. Trademarks Legerity, the Legerity logo and combinations thereof, DSLAC and QSLAC are trademarks of Legerity, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. P.O. Box 18200 Austin, Texas 78760-8200 Telephone: (512) 228-5400 Fax: (512) 228-5510 North America Toll Free: (800) 432-4009 To contact the Legerity Sales Office nearest you, or to download or order product literature, visit our website at www.legerity.com. To order literature in North America, call: (800) 572-4859 or email: [email protected] To order literature in Europe or Asia, call: 44-0-1179-341607 or email: Europe — [email protected] Asia — [email protected]