Am79484 Subscriber Line Interface Circuit DISTINCTIVE CHARACTERISTICS Ideal for long-loop applications Low standby power (45 mW) –40 V to –58 V battery operation On-hook transmission Tip Open state for ground-start lines Two-wire impedance set by single external impedance Programmable constant-current feed Programmable loop-detect threshold Current gain = 200 Polarity reversal option available On-chip Thermal Management (TMG) feature On-chip ring and test relay driver and relay snubber circuits BLOCK DIAGRAM TMG DA DB A(TIP) HPA Ring-Trip Detector Two-Wire Interface HPB Ground-Key Detector Off-hook Detector Relay Driver TESTOUT Ring Relay Driver RINGOUT Input Decoder and Control C1 C2 C3 C4 E1 E0 DET RD B(RING) Signal Transmission Power-Feed Controller VTX RSN RDC CAS VBAT BGND VCC VNEG AGND/DGND Publication# 080180 Rev: C Amendment: /0 Issue Date: May 1999 ORDERING INFORMATION Standard Products Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79484 –1 J C TEMPERATURE RANGE C = Commercial (0°C to 70°C)* PACKAGE TYPE J = 32-pin Plastic Leaded Chip Carrier (PL 032) PERFORMANCE GRADE OPTION –1 = 52 dB Longitudinal Balance, Polarity Reversal –2 = 63 dB Longitudinal Balance, Polarity Reversal –3 = 52 dB Longitudinal Balance, No Polarity Reversal –4 = 63 dB Longitudinal Balance, No Polarity Reversal DEVICE NUMBER/DESCRIPTION Am79484 Subscriber Line Interface Circuit Valid Combinations –1 –2 Am79484 JC –3 –4 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Leger ity sales office to confir m availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on Legerity’s standard military grade products. Note: * Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is guaranteed by characterization and periodic sampling of production units. 2 Am79484 Data Sheet CONNECTION DIAGRAM Top View NC BGND B(RING) 3 2 1 32 31 30 DB VCC 4 A(TIP) NC 32-Pin PLCC 29 NC RINGOUT 6 28 DA TESTOUT 7 27 RD TMG 8 26 HPB VBAT 9 25 RSVD C3 10 24 HPA E1 11 23 VTX C4 12 22 VEE NC 13 21 RSN AGND/DGND RDC 18 19 20 C1 15 16 17 C2 E0 14 CAS 5 DET NC Notes: 1. Pin 1 is marked for orientation. 2. NC = No Connect 3. RSVD = Reserved. Do not connect to this pin. SLIC Products 3 PIN DESCRIPTIONS Pin Names Type Description AGND/DGND Ground Analog and digital ground are connected internally to a single pin. A(TIP) Output Output of A(TIP) power amplifier. BGND Ground Battery (power) ground. B(RING) Output Output of B(RING) power amplifier. C4–C1 Input Decoder. SLIC control pins. TTL compatible. C4 is MSB and C1 is LSB. CAS Capacitor Anti-saturation. Pin for capacitor to filter reference voltage when operating in antisaturation region. DA Input Ring-trip negative. Negative input to ring-trip comparator. DB Input Ring-trip positive. Positive input to ring-trip comparator. DET Output Switchhook detector. Logic Low indicates that the selected detector is tripped. C3–C1 and E0 select the detector. Open-collector with a built-in 15 kΩ pull-up resistor. E0 Input Detect enable. A logic High enables DET. A logic Low disables DET. E1 Input Ground-key enable. E1 Low connects the ground-key or ring-trip detector to DET. E1 High connects the off-hook detector or ring-trip detector to DET. HPA Capacitor High-pass filter. A(TIP) side of high-pass filter capacitor. HPB Capacitor High-pass filter. B(RING) side of high-pass filter capacitor. NC — No connect. Pin not internally connected. RD Resistor Detect resistor. Threshold modification/filter point for the off-hook detector. RDC Resistor DC feed resistor. Connection point for the DC feed current programming network. The other end of the network connects to the receiver summing node (RSN). VRDC is negative for normal polarity and positive for reverse polarity. RINGOUT Output Ring relay driver. Open collector Darlington pull down. RSN Input Receive Summing Node. The metallic current (both AC and DC) between A(TIP) and B(RING) is 200 times the current flowing into this pin. The networks that program receive gain, two-wire impedance, and feed resistance connect to this node. RSVD — This pin is reserved only for test purposes. Leave unconnected. TESTOUT Output Test relay driver. Open collector Darlington pull down. TMG — Thermal management. External resistor connects between this pin and VBAT to off-load power dissipation from SLIC. Functions during Normal Polarity and Reverse Polarity states. VBAT Battery Battery supply. Connected through an external protection diode. VCC Power +5 V power supply. VEE Power –5 V power supply. VTX Output Transmit Audio. This output is a unity gain version of the A(TIP) and B(RING) metallic voltage. VTX also sources the two-wire input impedance programming network. 4 Am79484 Data Sheet ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage temperature . . . . . . . . . . . . –55°C to +150°C Commercial (C) Devices VCC with respect to AGND/DGND . . . . –0.4 V to +7 V Ambient temperature . . . . . . . . . . . . . . 0°C to +70°C* VEE with respect to AGND/DGND . . . . +0.4 V to –7 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V VBAT with respect to AGND/DGND: VEE . . . . . . . . . . . . . . . . . . . . . . . . –4.75 V to –5.25 V Continuous . . . . . . . . . . . . . . . . . . . +0.4 V to –70 V 10 ms . . . . . . . . . . . . . . . . . . . . . . . +0.4 V to –75 V VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . –40 V to –58 V BGND with respect to AGND/DGND . . . .+3 V to –3 V BGND with respect to AGND/DGND . . . . . . . . . . . . –100 mV to +100 mV A(TIP) or B(RING) to BGND: AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V Continuous . . . . . . . . . . . . . . . . . . . .–70 V to +1 V 10 ms (f = 0.1 Hz) . . . . . . . . . . . . . . . –70 V to +5 V 1 µs (f = 0.1 Hz) . . . . . . . . . . . . . . . . .–80 V to +8 V 250 ns (f = 0.1 Hz) . . . . . . . . . . . . . . –90 V to +12 V Load resistance on VTX to ground . . . . . . . 10 kΩ min Current from A(TIP) or B(RING). . . . . . . . . . ±150 mA * Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is guaranteed by characterization and periodic sampling of production units. Steady state operation at TA = 70°C is guaranteed by testing at 90°C and guard banding. RINGOUT/TESTOUT current. . . . . . . . . . . . . . 75 mA RINGOUT/TESTOUT voltage . . . . . . . BGND to +7 V RINGOUT/TESTOUT transient . . . . . BGND to +10 V The operating ranges define those limits between which the functionality of the device is guaranteed. DA and DB inputs Voltage on ring-trip inputs . . . . . . . . . . .VBAT to 0 V Current into ring-trip inputs . . . . . . . . . . . . ±10 mA C4–C1, E0, E1 Input voltage. . . . . . . . . . . . . –0.4 V to VCC + 0.4 V Maximum power dissipation, continuous, TA = 70°C, No heat sink (See note): In 32-pin PLCC package . . . . . . . . . . . . . . . . 1.7 W Thermal Data: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .θJA In 32-pin PLCC package . . . . . . . . . . . .43°C/W typ Note: Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165°C. The device should never see this temperature, and operation above 145°C junction temperature may degrade device reliability. See the SLIC Packaging Considerations for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may effect device reliability. SLIC Products 5 ELECTRICAL CHARACTERISTICS Description Test Conditions (See Note 1) Min Typ Max Unit Note dB 1, 4, 7 20 Ω 4 +40 +50 mV — 4 Transmission Performance 2-wire return loss 200 Hz to 3.4 kHz 26 Analog output (VTX) impedance 3 Analog (VTX) output offset voltage 0°C to +70°C –40°C to +85°C –40 –50 Overload level, 2 wire and 4 wire Active state 2.5 Vpk 2a Overload level On hook, RLAC = 900 Ω 1.18 Vrms 2b THD, Total Harmonic Distortion 0 dBm 0 dBm, RLDC = 2030 Ω, BAT = –42.5 V +7 dBm dB 5 — 5 THD, on hook –64 –45 –55 +1 dBm, RLAC = 900 Ω –50 –40 –36 5 Longitudinal Capability (See Test Circuit C) Longitudinal to metallic L-T, L-4 200 Hz to 1 kHz –1, –3* 52 200 Hz to 1 kHz Normal polarity –2, –4* 63 200 Hz to 1 kHz Reverse polarity –2* 58 200 Hz to 1 kHz –40°C to +85°C –2, –4* 58 1 kHz to 3.4 kHz –1, –3* 52 1 kHz to 3.4 kHz –2, –4* 58 4 1 kHz to 3.4 kHz –40°C to +85°C Longitudinal signal generation 4-L 200 Hz to 800 Hz Longitudinal current per pin Active state Standby state Longitudinal impedance at A or B 0 Hz to 100 Hz 70 54 Normal polarity 4 40 8.5 8.5 dB 27 27 mArms 25 35 Ω/pin Idle Channel Noise C-message weighted noise +25°C to +85°C –40°C to +25°C +7 +10 +12 dBrnC Psophometric weighted noise +25°C to +85°C –40°C to +25°C –83 –80 –78 dBmp — 4 Insertion Loss (2- to 4-Wire and 4- to 2-Wire, See Test Circuits A and B) Gain accuracy 0 dBm, 1 kHz 0 dBm, 1 kHz On hook, OHT state 0°C to +70°C –40°C to +85°C –0.15 –0.20 –0.35 +0.15 +0.20 +0.35 Gain accuracy over frequency relative to 1 kHz 300 Hz to 3.4 kHz 300 Hz to 3.4 kHz 0°C to +70°C –40°C to +85°C –0.10 –0.15 +0.10 +0.15 Gain tracking relative to 0 dBm +3 dBm to –55 dBm 0°C to +70°C +3 dBm to –55 dBm –40°C to +85°C +3 dBm, BAT = –42.5 V, RLDC = 2030 Ω On hook –0.10 –0.15 –0.30 –0.35 +0.10 +0.15 +0.30 +0.35 Note: * Performance Grade 6 Am79484 Data Sheet — 4 4 dB 5 4 — 4 — — ELECTRICAL SPECIFICATIONS (continued) Description Test Conditions (See Note 1) Min Typ Max Unit Note Balance Return Signal (4-Wire to 4-Wire) Gain accuracy Ref: 0 dBm, 1 kHz Ref: 0 dBm, 1 kHz 0°C to +70°C –40°C to +85°C –0.15 –0.20 +0.15 +0.20 Gain accuracy over frequency 300 Hz to 3400 Hz 300 Hz to 3400 Hz 0°C to +70°C –40°C to +85°C –0.10 –0.15 +0.10 +0.15 Gain tracking relative to 0 dBm +3 dBm to –55 dBm +3 dBm to –55 dBm 0°C to +70°C –40°C to +85°C –0.10 –0.15 +0.10 +0.15 Group delay 0 dBm, 1 kHz 4 3 4 dB 3 4 — 4 µs 4, 7 Line Characteristics Voltage on TMG pin Constant-current region IL, short loops, Active or OHT state IL, long loops, Active state RLDC = 2030 Ω, BAT = –42.5 V, TA = 25°C IL, accuracy, Standby state V BAT – 3 V I L = -----------------------------R L + 400 20 22 24 18 18.6 0.8IL IL 1.2IL 16 22 39 0 23 22 100 45 24.5 µA mA mA 100 µA 120 mA mA TA = 25°C Constant-current region IL, loop current, Tip Open state 8 VTMG RL = 0 Ω, VA = 0 Ω to VA = VBAT B to ground VBAT = –56.5 V, R = 2.2 kΩ, B to gnd IL, loop current, Open Circuit state RL = 0 Ω ILLIM Active, A and B to gnd VA, Active, ground-start signaling A to –48 V = 7 kΩ, B to gnd = 100 Ω VAB, Open Circuit voltage BAT = –52 V A lead impedance, Tip Open state VA = 0 V to VA = VBAT 95 –7.5 –5 4 V –42.75 –45.7 150 k 10 M Ω 4 dB 5 Power Supply Rejection Ratio (VRIPPLE = 100 mVrms), Active Normal State VCC 50 Hz to 3400 Hz 500 Hz to 3000 Hz 30 35 40 VEE 50 Hz to 3400 Hz 500 Hz to 3000 Hz 28 30 35 VBAT 50 Hz to 3400 Hz 500 Hz to 3000 Hz 28 45 50 Effective internal resistance CAS pin to gnd 85 170 Control lead feed through 50 Hz to 3400 Hz on C1, C2, or C3 35 50 255 kΩ 4 SLIC Products dB 7 ELECTRICAL SPECIFICATIONS (continued) Description Test Conditions (See Note 1) Min Typ Max On hook, Open Circuit state 25 70 On hook, Standby state 45 85 On hook, OHT state 180 270 180 195 270 300 860 1100 Unit Note Power Dissipation On hook, Active state RTMG = open RTMG = 2500 Ω Off hook, Standby state Off hook, OHT state RL = 300 Ω, RTMG = open 1000 1300 Off hook, Active state RL = 300 Ω, RTMG = 2500 Ω 450 800 ICC, On-hook VCC supply current Open Circuit state OHT state Standby state Active state, BAT = –48 V 1.7 7.0 3.0 6.3 2.5 8.5 3.5 8.5 IEE, On-hook VEE supply current Open Circuit state OHT state Standby state Active state, BAT = –48 V 0.7 2.0 0.77 2.1 2.0 3.5 2.0 5.0 IBAT, On-hook VBAT supply current Open Circuit state OHT state Standby state Active state, BAT = –48 V 0.18 1.9 0.45 4.2 1.0 4.7 1.5 5.7 mW 4 Supply Currents, Battery = –58 V mA RFI Rejection RFI rejection 100 kHz to 30 MHz, (See Figure E) 1.0 mVrms 4 V 4 Receive Summing Node (RSN) RSN DC voltage IRSN = 0 mA 0 Logic Inputs (C4–C1, E0, E1) VIH, input High voltage 2.0 V VIL, input Low voltage 0.8 IIH, input High current IIL, input Low current –75 40 µA C4–C1, E0, E1 –400 Logic Output (DET) VOL, output Low voltage Iout = 0.3 mA, 15 kΩ to VCC VOH, output High voltage Iout = –0.1 mA, 15 kΩ to VCC 0.40 V 2.4 Ring-trip Detector Input (DA, DB) Bias current Offset voltage Source resistance = 2 MΩ –20 –5 –50 0 nA +50 4 6 mV Offset voltage 8 Source resistance mismatch = 3 MΩ Am79484 Data Sheet –50 0 +50 4 ELECTRICAL SPECIFICATIONS (continued) Description Test Conditions (See Note 1) Min Typ Max Unit +0.35 +1.00 V 100 µA Note Relay Driver Output (RINGOUT) On voltage IOL = 41 mA Off leakage VOH = +5 V Zener breakover IZ = 100 µA Zener ON voltage IZ = 30 mA 10 On voltage IOL = 81.5 mA +0.8 Off leakage VOH = +5 V Zener breakover IZ = 100 µA Zener ON voltage IZ = 80 mA 6 7.2 V Test Driver Output (TESTOUT) 6 +1.50 V 100 µA 7.2 V 14 Detector Thresholds IT, loop-detect threshold tolerance RD = 35.4 kΩ, IT, ground-key detect threshold Tip Open, B lead only, E1 = 0 Active Standby 330/RD 375/RD 420/RD 330/RD 375/RD 420/RD 7.5 10 14 A mA RELAY DRIVER SCHEMATICS TESTOUT RINGOUT BGND AGND SLIC Products 9 Notes: 1. Unless otherwise noted, test conditions are BAT = –48 V, VCC = +5 V, VEE = –5 V, RL = 600 Ω, RDC1 = RDC2 = 11.36 kΩ, RD = 35.4 kΩ, RTMG = 2.5 kΩ, no fuse resistors, CHP = 0.2 µF, CDC = 0.1 µF, CCAS = 0.1 µF, two-wire AC input impedance is a 900 Ω resistance synthesized by the programming network shown below. VTX RT1 = 90 kΩ RT2 = 90 kΩ CT1 = 100 pF RSN ~ RRX = 90 kΩ 2. 3. 4. 5. 6. 7. 8. VRX a. Overload level is defined when THD = 1%. b. Overload level is defined when THD = 1.5%. Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire AC load impedance matches the programmed impedance. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1 above. The network reduces the group delay to less than 2 µs and increases 2WRL. The effect of group delay on linecard performance may also be compensated by synthesizing complex impedance with the QSLAC™ or DSLAC™ device. The voltage on the TMG pin (VTMG) is related to the voltage across the line (VAB) when the device is in the constant-current region. The relationship between VAB and VTMG voltage is described by the following equation: VTMG = –0.966|VAB| – 6.23 Table 1. SLIC Decoding DET Output State C3 C2 C1 Two-Wire Status 0 0 0 0 Open Circuit Ring trip Ring trip 1 0 0 1 Ringing Ring trip Ring trip 2 0 1 0 Active Loop detector Ground key 3 0 1 1 On-hook TX (OHT) Loop detector Ground key 4 1 0 0 Tip Open Loop detector Ground key 5 1 0 1 Standby Loop detector Ground key 6 1 1 0 Active Polarity Reversal Loop detector Ground key 7 1 1 1 OHT Polarity Reversal Loop detector Ground key Notes: 1. C4 logic high enables the TESTOUT relay driver. 2. E0 logic high enables the DET pin. 10 Am79484 Data Sheet E1 = 1 E1 = 0 Table 2. User-Programmable Components Z T = 200 ( Z 2WIN – 2R F ) Z RX ZT is connected between the VTX and RSN pins. The fuse resistors are RF, and Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the desired receive gain. 200 • Z T ZL - • ------------------------------------------------= ---------G 42L Z T + 200 ( Z L + 2R F ) R DC1 + R DC2 RDC1, RDC2, and CDC form the network connected to the RDC pin. RDC1 and RDC2 are approximately equal. ILOOP is the desired loop current in the constant-current region. 500 = -------------I LOOP R DC1 + R DC2 C DC = 1.5 ms • ------------------------------R DC1 R DC2 375 R D = --------- , IT RD and CD form the network connected from RD to –5 V, and IT is the threshold current between on hook and off hook. 0.5 ms C D = ---------------RD CCAS is the regulator filter capacitor, and fc is the desired filter cut-off frequency. 1 C CAS = ----------------------------5 3.4 • 10 π f c OHT loop current (constant-current region). 500 I OHT = ------------------------------R DC1 + R DC2 Thermal Management Equations (Normal Active and Tip Open States) RTMG is connected from TMG to VBAT and is used to limit power dissipation within the SLIC in Active and Tip Open states only. V BAT – 6 V R TMG ≥ -----------------------------I LOOP Power is dissipated in the thermal management resistor, RTMG, during Active and Tip Open states. 2 ( V BAT – 6 V – ( I L • R L ) ) P RTMG = -----------------------------------------------------------------R TMG 2 P SLIC = V BAT • I L – P RTMG – R L ( I L ) + 0.12 W Power is dissipated in the SLIC while in Active and Tip Open states. SLIC Products 11 DC FEED CHARACTERISTICS 60 3 2 VAB (V) 1 0 30 IL (mA) RDC = RDC1 + RDC2 = 22.72 kΩ BAT = –48 V 500 1. V AB = I L R L' = ---------- R L ' , where R L' = R L + 2R F R DC R DC 2. V AB = 0.925 • V BAT + 0.9 – I L ---------- 120 R DC 3. V AB = 0.925 • V BAT – 1.83 – I L ---------- 120 a. Load Line (typical) A RSN a RL b SLIC IL RDC2 CDC B RDC1 RDC Feed current programmed by RDC1 and RDC2 b. Feed Programming Figure 1. 12 DC Feed Characteristics Am79484 Data Sheet TEST CIRCUITS A(TIP) RL 2 VTX SLIC VAB VL RL 2 AGND RT RRX RSN B(RING) IL2-4 = 20 log (VTX / VAB) A. Two- to Four-Wire Insertion Loss A(TIP) VTX SLIC VAB RL AGND RT RRX B(RING) RSN IL4-2 = 20 log (VAB / VRX) VRX BRS = 20 log (VTX / VAB) B. Four- to Two-Wire Insertion Loss and Balance Return Signal 1 << RL ωC S1 VTX A(TIP) RL 2 C VL VL SLIC VAB AGND RL 2 RT S2 RRX B(RING) RSN VRX S2 Open, S1 Closed L-T Long. Bal. = –20 log (VAB / VL) S2 Closed, S1 Open 4-L Long. Sig. Gen. = –20 log (VL / VRX) L-4 Long. Bal. = –20 log (VTX / VL) C. Longitudinal Balance SLIC Products 13 TEST CIRCUITS (continued) ZD A(TIP) R VTX SLIC VS VM R RT1 AGND ZIN RT2 CT1 B(RING) RSN RRX ZD: The desired impedance; e.g., the characteristic impedance of the line Return loss = –20 log (2 VM / VS) D. Two-Wire Return Loss Test Circuit L1 RF1 200 Ω C1 50 Ω A RF2 50 Ω 200 Ω HF GEN 1.5 Vrms 80% Amplitude Modulated 100 kHz to 30 MHz 14 CAX 33 nF B 50 Ω L2 C2 CBX 33 nF VTX SLIC under test E. RFI Test Circuit Am79484 Data Sheet TEST CIRCUITS (continued) +5 V DA DB –5 V VCC VEE RD RD VTX VTX 2.2 nF A(TIP) HPA A(TIP) CHP HPB B(RING) B(RING) RT RDC1 2.2 nF RRX VRX RSN RDC2 RDC CDC RINGOUT AGND/ TESTOUT DGND E1 BGND E0 BATTERY GROUND C4 C3 VBAT BAT TMG Schottky C2 ANALOG GROUND C1 D1 RTMG DET CAS CCAS DIGITAL GROUND F. Am79484 Test Circuit SLIC Products 15 PHYSICAL DIMENSIONS PL032 .447 .453 .485 .495 .009 .015 .585 .595 .042 .056 .125 .140 Pin 1 I.D. .080 .095 .547 .553 SEATING PLANE .400 REF. .490 .530 .013 .021 .050 REF. .026 .032 TOP VIEW SIDE VIEW 16-038FPO-5 PL 032 DA79 6-28-94 ae REVISION SUMMARY Revision A to B Within the Electrical Specifications, under the Supply Currents, changed the values for the ICC, On hook VCC Supply Current. Minor changes were made to the data sheet style and format to conform to Legerity standards. Revision B to C 16 The equation in note #8 on page 10 was modified. The physical dimensions were added on page 16. Am79484 Data Sheet Notes: www.legerity.com Legerity provides silicon solutions that enhance the performance, speeds time-to-market, and lowers the system cost of our customers' products. By combining process, design, systems architecture, and a complete set of software and hardware support tools with unparalleled factory and worldwide field applications support, Legerity ensures its customers enjoy a smoother design experience. It is this commitment to our customers that places Legerity in a class by itself. The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in Legerity's Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of Legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. Legerity reserves the right to discontinue or make changes to its products at any time without notice. © 1999 Legerity, Inc. All rights reserved. Trademarks Legerity, the Legerity logo and combinations thereof, DSLAC and QSLAC are trademarks of Legerity, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. P.O. Box 18200 Austin, Texas 78760-8200 Telephone: (512) 228-5400 Fax: (512) 228-5510 North America Toll Free: (800) 432-4009 To contact the Legerity Sales Office nearest you, or to download or order product literature, visit our website at www.legerity.com. To order literature in North America, call: (800) 572-4859 or email: [email protected] To order literature in Europe or Asia, call: 44-0-1179-341607 or email: Europe — [email protected] Asia — [email protected]