ETC AM79574-1JC

Am79574
Subscriber Line Interface Circuit
DISTINCTIVE CHARACTERISTICS
Programmable constant resistance feed
Line-feed characteristics independent of
battery variations
Programmable loop-detect threshold
On-chip switching regulator for low-power
dissipation
Pin for external ground-key noise filter
capacitor available
Ground-key detect option available
Two-wire impedance set by single external
impedance
Polarity reversal feature
Tip Open state for ground-start lines
Test relay driver optional
On-hook transmission
BLOCK DIAGRAM
A(TIP)
Ring Relay Driver
RINGOUT
Test Relay Driver
TESTOUT
Ground-Key
Detector
HPA
Input Decoder
and Control
Two-Wire
Interface
DET
HPB
GKFIL
VTX
RSN
Signal
Transmission
Off-Hook
Detector
B(RING)
Power-Feed
Controller
DA
DB
VREG
L
VBAT
BGND
C1
C2
C3
C4
E1
E0
RD
RDC
Ring-Trip Detector
Switching
Regulator
CHS QBAT CHCLK
VCC
VEE AGND
16855C-001
Notes:
1. Am79574—E0 and E1 inputs; ring and test relay drivers sourced internally to BGND.
2. Output amplifier current gain (K1) = 1000.
Publication# 080153 Rev: E Amendment: /0
Issue Date: October 1999
ORDERING INFORMATION
Standard Products
Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Am79574
J
C
TEMPERATURE RANGE
C = Commercial (0°C to 70°C)*
PACKAGE TYPE
J = 32-Pin Plastic Leaded Chip Carrier (PL 032)
PERFORMANCE GRADE
Blank = Standard Specification
–1 = Performance Grading
–2 = Performance Grading
DEVICE NAME/DESCRIPTION
Am79574
Subscriber Line Interface Circuit
Valid Combinations
Valid Combinations
Am79574
–1
–2
JC
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Legerity sales office to confirm
availability of specific valid combinations, to
check on newly released combinations, and to
obtain additional data on Legerity’s standard
military–grade products.
Note:
* Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is
guaranteed by characterization and periodic sampling of production units.
2
Am79574 Data Sheet
VCC
VREG
BGND
B(RING)
A(TIP)
4
3
2
1
32
31 30
DB
RINGOUT
CONNECTION DIAGRAM
Top View
TP
TESTOUT
6
28
DA
L
7
27
RD
VBAT
8
26
HPB
QBAT
9
25
HPA
CHS
10
24
VTX
CHCLK
11
23
VEE
C4
12
22
RSN
E1
13
21
AGND
18 19 20
DGND
17
RDC
15 16
C2
E0
14
C1
29
C3
5
DET
TP
Notes:
1. Pin 1 is marked for orientation.
2. TP is a thermal conduction pin tied to substrate (QBAT).
SLIC Products
3
PIN DESCRIPTIONS
Pin Names
Type
Description
AGND
Gnd
Analog (quiet) ground
A(TIP)
Output
Output of A(TIP) power amplifier
BGND
Gnd
Battery (power) ground
B(RING)
Output
Output of B(RING) power amplifier
C3–C1
Input
Decoder. TTL compatible. C3 is MSB and C1 is LSB.
C4
Input
Test relay driver command. TTL compatible. Logic Low enables the driver.
CHCLK
Input
Chopper clock. Input to switching regulator (TTL compatible). Freq = 256 kHz (Nominal).
CHS
Input
Chopper stabilization. Connection for external stabilization components.
DA
Input
Ring-trip negative. Negative input to ring-trip comparator.
DB
Input
Ring-trip positive. Positive input to ring-trip comparator.
DET
Output
Detector. Logic Low indicates that the selected detector is tripped. Logic inputs C3–C1, E1, and E0
select the detector. Open-collector with a built-in 15 kΩ pull-up resistor.
DGND
Gnd
Digital ground
E0
Input
A logic High enables DET. A logic Low disables DET.
E1
Input
E1 = High connects the ground-key detector to DET, and E1 = Low connects the off-hook or ring-trip
detector to DET.
HPA
Capacitor High-pass filter capacitor. A(TIP) side of high-pass filter capacitor.
HPB
Capacitor High-pass filter capacitor. B(RING) side of high-pass filter capacitor.
L
Output
Switching Regulator Power Transistor. Connection point for filter inductor and anode of catch diode.
Has up to 60 V of pulse waveform on it and must be isolated from sensitive circuits. Keep the diode
connections short because of the high currents and high di/dt.
QBAT
Battery
Filtered battery supply for the signal processing circuits.
RD
Resistor
Detector resistor. Threshold modification and filter point for the off-hook detector.
RDC
Resistor
DC feed resistor. Connection point for the DC feed current programming network, which also
connects to the Receiver Summing Node (RSN). VRDC is negative for normal polarity and positive
for reverse polarity.
RINGOUT
Output
Ring relay driver. Sourcing from BGND with internal diode to QBAT.
RSN
Input
The metallic current (AC and DC) between A(TIP) and B(RING) = 1000 x the current into this pin. The
networks that program receive gain, two-wire impedance, and feed resistance all connect to this
node. This node is extremely sensitive. Route the 256 kHz chopper clock and switch lines away from
the RSN node.
TESTOUT
Output
Test relay driver. Source from BGND with internal diode to QBAT.
TP
Thermal
Thermal pin. Connection for heat dissipation. Internally connected to substrate (QBAT). Leave as
open circuit or connected to QBAT. In both cases, the TP pins can connect to an area of copper on
the board to enhance heat dissipation.
VBAT
Battery
Battery supply. Connected through an external protection diode.
VCC
Power
+5 V power supply.
VEE
Power
–5 V power supply.
VREG
Input
Regulated voltage. Provides negative power supply for power amplifiers, connection point for
inductor, filter capacitor, and chopper stabilization.
VTX
Output
Transmit Audio. Unity gain version of the A(TIP) and B(RING) metallic voltage. VTX also sources the
two-wire input impedance programming network.
4
Am79574 Data Sheet
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage temperature ......................... –55°C to +150°C
VCC with respect to AGND/DGND...... –0.4 V to +7.0 V
VEE with respect to AGND/DGND ...... +0.4 V to –7.0 V
Commercial (C) Devices
Ambient temperature ............................. 0°C to +70°C*
VCC ..................................................... 4.75 V to 5.25 V
VBAT with respect to AGND/DGND ..... +0.4 V to –70 V
VEE .................................................. –4.75 V to –5.25 V
Note: Rise time of VBAT (dv/dt) must be limited to 27 V/µs or
less when QBAT bypass = 0.33 µF.
BGND with respect to AGND/DGND.. +1.0 V to –3.0 V
A(TIP) or B(RING) to BGND:
Continuous..................................... –70 V to +1.0 V
10 ms (f = 0.1 Hz) .......................... –70 V to +5.0 V
1 µs (f = 0.1 Hz) .............................. –90 V to +10 V
250 ns (f = 0.1 Hz) ........................ –120 V to +15 V
Current from A(TIP) or B(RING) ....................... ±150 mA
Voltage on RINGOUT ........BGND to 70 V above QBAT
Voltage on TESTOUT ........BGND to 70 V above QBAT
VBAT ...................................................... –40 V to –58 V
AGND/DGND.......................................................... 0 V
BGND with respect to
AGND/DGND ........................ –100 mV to +100 mV
Load Resistance on VTX to ground............. 10 kΩ min
Operating Ranges define those limits between which the
functionality of the device is guaranteed.
* Functionality of the device from 0°C to +70°C is guaranteed
by production testing. Performance from –40°C to +85°C is
guaranteed by characterization and periodic sampling of
production units.
Current through relay drivers .............................60 mA
Voltage on ring-trip inputs
(DA and DB) ......................................... VBAT to 0 V
Current into ring-trip inputs.................................. ±10 mA
Peak current into regulator
Switch (L pin) ..............................................150 mA
Switcher transient peak off
Voltage on L pin ............................................+1.0 V
C4–C1, E1, CHCLK to
AGND/DGND ....................... –0.4 V to VCC + 0.4 V
Maximum power dissipation, (see note) ...... TA = 70°C
In 32-pin PLCC package..............................1.74 W
Note: Thermal limiting circuitry on-chip will shut down the
circuit at a junction temperature of about 165°C. The device
should never be exposed to this temperature. Operation
above 145°C junction temperature may degrade device
reliability. See the SLIC Packaging Considerations for more
information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
SLIC Products
5
ELECTRICAL CHARACTERISTICS
Description
Test Conditions (See Note 1)
Min
Analog (VTX ) output impedance
Analog (VTX) output offset
Typ
Max
3
0°C to 70°C
–1*
–35
–30
+35
+30
–1
–40
–35
+40
+35
–40°C to +85°C
Analog (RSN) input impedance
1
Longitudinal impedance at A or B
300 Hz to 3.4 kHz
Overload level
Z2WIN = 600 to 900 Ω
4-wire
2-wire
20
35
–3.1
+3.1
Unit
Note
Ω
4
mV
—
—
—
4
4
Ω
4
Vpk
2
dB
4, 11
Transmission Performance, 2-Wire Impedance
2-wire return loss
(See Test Circuit D)
300 Hz to 500 Hz
500 Hz to 2.5 kHz
2500 Hz to 3.4 kHz
26
26
20
Longitudinal Balance (2-Wire and 4-Wire, See Test Circuit C)
RL = 600 Ω
Longitudinal to metallic L-T, L-4
300 Hz to 3.4 kHz
300 Hz to 3.4 kHz
–1*
48
52
Longitudinal to metallic L-T, L-4
200 Hz to 1 kHz
normal polarity 0°C to +70°C
normal polarity –40°C to +85°C
reverse polarity
–2*
–2
–2
63
58
54
1 kHz to 3.4 kHz
normal polarity 0°C to +70°C
normal polarity –40°C to +85°C
reverse polarity
–2*
–2
–2
58
54
54
Longitudinal signal
generation 4-L
300 Hz to 800 Hz
300 Hz to 800 Hz
–1*
40
42
Longitudinal current capability
per wire
Active state
OHT state
dB
—
4
—
—
4
—
25
18
mArms
4
Insertion Loss (2- to 4-Wire and 4- to 2-Wire, See Test Circuits A and B)
Gain accuracy
Variation with frequency
Gain tracking
0 dBm, 1 kHz,
0 dBm, 1 kHz,
0 dBm, 1 kHz,
0 dBm, 1 kHz,
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
–0.15
–0.20
–0.1
–0.15
+0.15
+0.20
+0.1
+0.15
300 Hz to 3.4 kHz
Relative to 1 kHz
0°C to +70°C
–40°C to +85°C
–0.1
–0.15
+0.1
+0.15
—
4
+7 dBm to –55 dBm
0°C to +70°C
–40°C to +85°C
–0.1
–0.15
+0.1
+0.15
—
4
–1*
–1
dB
Notes:
* P.G. = Performance Grade
–2 grade performance parameters are equivalent to –1 performance parameters except where indicated.
6
Am79574 Data Sheet
—
4
—
4
ELECTRICAL CHARACTERISTICS (continued)
Description
Test Conditions (See Note 1)
Balance Return Signal (4- to 4-Wire, See Test Circuit B)
Gain accuracy
0 dBm, 1 kHz, 0°C to +70°C
0 dBm, 1 kHz, –40°C to +85°C
0 dBm, 1 kHz, 0°C to +70°C
0 dBm, 1 kHz, –40°C to +85°C
Variation with frequency
Gain tracking
Group delay
Min
Typ
Max
Unit
Note
–0.15
–0.20
–0.1
–0.15
+0.15
+0.20
+0.1
+0.15
300 Hz to 3.4 kHz
Relative to 1 kHz
0°C to +70°C
–40°C to +85°C
–0.1
–0.15
+0.1
+0.15
—
4
+7 dBm to –55 dBm
0°C to +70°C
–40°C to +85°C
–0.1
–0.15
+0.1
+0.15
—
4
–1*
–1
—
4
—
4
dB
f = 1 kHz
µs
5.3
4
Total Harmonic Distortion (2- to 4-Wire or 4- to 2-Wire, See Test Circuits A and B)
Total harmonic distortion
0 dBm, 300 Hz to 3.4 kHz
+9 dBm, 300 Hz to 3.4 kHz
–64
–55
–50
–40
–1*
+7
+7
+7
+15
+12
+15
+15
+12
+15
dB
Idle Channel Noise
C-message weighted noise
Psophometric weighted noise
2-wire,
2-wire,
2-wire,
0°C to +70°C
0°C to +70°C
–40°C to +85°C
4-wire,
4-wire,
4-wire,
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–1*
+7
+7
+7
2-wire,
2-wire,
2-wire,
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–1*
–83
–83
–83
–75
–78
–75
4-wire,
4-wire,
4-wire,
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–1*
–83
–83
–83
–75
–78
–75
Single Frequency Out-of-Band Noise (See Test Circuit E)
Metallic
4 kHz to 9 kHz
–76
9 kHz to 1 MHz
–76
256 kHz and harmonics
–57
Longitudinal
1 kHz to 15 kHz
–70
Above 15 kHz
–85
256 kHz and harmonics
–57
Line Characteristics (See Figure 1) BAT = –48 V, RL = 600 Ω and 900 Ω, RFEED = 800 Ω
Active state
Active state
Loop current—Tip Open
RL = 600 Ω
1.0
Loop current—Open Circuit
RL = 0 Ω
1.0
Loop current limit accuracy
OHT state
Active state
A and B shorted to GND
SLIC Products
–20
50
dBmp
dBm
Apparent battery voltage
Loop current accuracy
Fault current limit, ILLIM
(IAX + IBX)
47
–7.5
dBrnc
53
+7.5
—
—
4
—
—
4
7
—
4, 7
7
—
4, 7
4, 5, 9
4, 5, 9
4, 5
4, 5, 9
4, 5, 9
4, 5
V
%
mA
+20
%
130
mA
10
7
ELECTRICAL CHARACTERISTICS (continued)
Description
Test Conditions (See Note 1)
Min
Typ
Max
–1*
35
35
135
135
120
80
250
200
–1*
200
200
400
300
Power Dissipation, BAT = –48 V, Normal Polarity
On-hook Open Circuit state
–1*
On-hook OHT state
On-hook Active state
Off-hook OHT state
RL = 600 Ω
500
750
Off-hook Active state
RL = 600 Ω
650
1000
VCC on-hook supply current
Open Circuit state
OHT state
Active state
3.0
6.0
8.0
4.5
10.0
13.0
VEE on-hook supply current
Open Circuit state
OHT state
Active state
1.0
2.3
3.0
2.3
3.7
6.0
VBAT on-hook supply current
Open Circuit state
OHT state
Active state
0.4
3.2
4.5
1.0
5.5
7.0
Unit
Note
mW
Supply Currents
mA
Power Supply Rejection Ratio (VRIPPLE = 50 mVrms)
VCC
50 Hz to 3.4 kHz
–1*
25
30
22
25
45
45
35
40
–1*
20
25
40
40
10
10
27
30
20
25
25
25
45
45
40
40
–1*
3.4 kHz to 50 kHz
VEE
50 Hz to 3.4 kHz
3.4 kHz to 50 kHz
–1*
VBAT
50 Hz to 3.4 kHz
–1*
3.4 kHz to 50 kHz
–1*
Off-Hook Detector
Current threshold accuracy
IDET = 365/RD Nominal
–20
dB
+20
%
10.0
kΩ
6, 7
Ground-Key Detector Thresholds, Active State, BAT = –48 V (See Test Circuit F)
Ground-key resistance threshold
Ground-key current threshold
B(RING) to GND
B(RING) to GND
2.0
Midpoint to GND
5.0
9
9
mA
8
µA
mV
12
Ring-Trip Detector Input
Bias current
Offset voltage
Source resistance
0 Ω to 2 MΩ
Logic Inputs (C4–C1, E0, E1, and CHCLK)
Input High voltage
Input Low voltage
Input High current
Input High current
Input Low current
8
–5
–50
–0.05
0
+50
2.0
All inputs except E1
–75
Input E1
–75
–0.4
Am79574 Data Sheet
0.8
40
45
V
µA
mA
ELECTRICAL CHARACTERISTICS (continued)
Description
Test Conditions (See Note 1)
Logic Output (DET)
Output Low voltage
IOUT = 0.8 mA
Output High voltage
IOUT = –0.1 mA
Typ
Max
Unit
Note
0.4
V
2.4
Relay Driver Outputs (RINGOUT, TESTOUT)
On voltage
50 mA source
Off leakage
Clamp voltage
Min
BGND – 2 BGND –.95
0.5
50 mA sink
V
100
QBAT –2
µA
V
RELAY DRIVER SCHEMATICS
BGND
BGND
RINGOUT
QBAT
TESTOUT
QBAT
SWITCHING CHARACTERISTICS
Symbol
*tgkde
Parameter
Test Conditions
E1 Low to DET High (E0 = 1)
E1 Low to DET Low (E0 = 1)
Ground-Key Detect state
RL open, RG connected
(See Figure H)
Temperature
Range
Min
Typ
Max
0°C to +70°C
–40°C to +85°C
3.8
4.0
0°C to +70°C
–40°C to +85°C
1.1
1.6
0°C to +70°C
–40°C to +85°C
1.1
1.6
tgkdd
E0 High to DET Low (E1 = 0)
tgkd0
E0 Low to DET High (E1 = 0)
0°C to +70°C
–40°C to +85°C
3.8
4.0
*tshde
E1 High to DET Low (E0 = 1)
0°C to +70°C
–40°C to +85°C
1.2
1.7
0°C to +70°C
–40°C to +85°C
3.8
4.0
0°C to +70°C
–40°C to +85°C
1.1
1.6
0°C to +70°C
–40°C to +85°C
3.8
4.0
E1 High to DET High (E0 = 1)
*tshdd
E0 High to DET Low (E1 = 1)
*tshd0
E0 Low to DET High (E1 = 1)
Switchhook Detect state
RL = 600 Ω, RG open
(See Figure G)
Unit
Note
µs
4
Note:
E1 is internally connected to a logical 0.
SLIC Products
9
SWITCHING WAVEFORMS
E1 to DET*
E1*
DET*
tgkde
tshde
tgkde
tshde
E0 to DET
E1*
E0
DET
tshdd
tgkdd
tshd0
tgkd0
Notes:
* E1 is internally connected to a logical 0.
1. All delays measured at 1.4 V level.
Notes:
1. Unless otherwise noted, test conditions are BAT = –48 V, VCC = +5 V, VEE = –5 V, RL = 600 Ω, CHP = 0.22 µF,
RDC1 = RDC2 = 20 kΩ, CDC = 0.1 µF, Rd = 51.1 kΩ, no fuse resistors, two-wire AC output impedance, programming impedance
(ZT) = 600 kΩ resistive, receive input summing impedance (ZRX) = 300 kΩ resistive. (See Table 2 for component formulas.)
2. Overload level is defined when THD = 1%.
3. Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire AC load impedance
matches the impedance programmed by ZT.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. These tests are performed with a longitudinal impedance of 90 Ω and metallic impedance of 300 Ω for frequencies below
12 kHz and 135 Ω for frequencies greater than 12 kHz. These tests are extremely sensitive to circuit board layout.
6. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
7. When the SLIC is in the anti-sat 2 operating region, this parameter is degraded. The exact degradation depends on system
design. The anti-sat 2 region occurs at high loop resistances when VBAT – VAX – VBX is less than 14 V.
8. Midpoint is defined as the connection point between two 300 Ω series resistors connected between A(TIP) and B(RING).
9. Fundamental and harmonics from 256 kHz switch-regulator chopper are not included.
10. Calculate loop-current limit using the following equations:
10
In OHT state:
V APPARENT
I LIMIT = 0.5 -------------------------------------R FEED
In Active state:
V APPARENT
I LIMIT = 0.8 -------------------------------------R FEED
Am79574 Data Sheet
11. Assumes the following ZT network:
VTX
RSN
300 kΩ
300 kΩ
30 pF
12. Tested with 0 Ω source impedance. 2 MΩ is specified for system design purposes only.
13. Group delay can be considerably reduced by using a ZT network such as that shown in Note 11 above. The network reduces
the group delay to less than 2 µs. The effect of group delay on linecard performance may be compensated for by using
QSLAC™ or DSLAC™ devices.
Table 1. SLIC Decoding
DET Output
State
C3 C2 C1
Two-Wire Status
E0 = 1*
E1 = 0
E0 = 1*
E1 = 1
0
0
0
0
Open Circuit
Ring trip
Ring trip
1
0
0
1
Ringing
Ring trip
Ring trip
2
0
1
0
Active
Loop detector
Ground key
3
0
1
1
On-hook TX (OHT)
Loop detector
Ground key
4
1
0
0
Tip Open
Loop detector
—
5
1
0
1
Reserved
Loop detector
—
6
1
1
0
Active Polarity Reversal
Loop detector
Ground key
7
1
1
1
OHT Polarity Reversal
Loop detector
Ground key
Note:
* A logic Low on E0 disables the DET output into the Open Collector state.
Table 2. User-Programmable Components
Z T = 1000 ( Z 2WIN – 2R F )
ZT is connected between the VTX and RSN pins. The fuse
resistors are RF, and Z2WIN is the desired 2-wire AC input
impedance. When computing ZT, the internal current
amplifier pole and any external stray capacitance between
VTX and RSN must be taken into account.
ZL
1000 • Z T
- • ---------------------------------------------------Z RX = ---------G 42L Z T + 1000 ( Z L + 2R F )
ZRX is connected from VRX to the RSN pin, ZT is defined
above, and G42L is the desired receive gain.
R DC1 + R DC2 = 50 ( R FEED – 2R F )
RDC1, RDC2, and CDC form the network connected to the
RDC pin. RDC1 and RDC2 are approximately equal.
R DC1 + R DC2
C DC = 1.5 ms • ------------------------------R DC1 • R DC2
365
R D = --------- ,
IT
0.5 ms
C D = -----------------RD
RD and CD form the network connected from RD to –5 V and
IT is the threshold current between on hook and off hook.
SLIC Products
11
DC FEED CHARACTERISTICS
4
3
5
2
6
1
7
VBAT = –47.3 V
RDC = 40 kΩ
Active state
OHT state
Notes:
1. Constant-resistance feed region:
R DCö
V AB = 50 – I L æ --------è 50 ø
2. Anti-sat –1 turn-on:
V AB = 31.8 V
3. Anti-sat –2 turn-on:
V AB = 1.077 V BAT – 12.538
4. Open circuit voltage:
V AB = 0.377 V BAT + 20.48,
V BAT < 50.2 V
V AB = 39.39 V
V BAT ≥ 50.2 V
5. Anti-sat –1 region:
R DC ö
V AB = 39.39 – I L æ -----------è 118.3ø
6. Anti-sat –2 region:
R DCö
V AB = 0.377 V BAT + 20.48 – I L æ --------è 200 ø
7. Current Limit:
Active state,
OHT state,
2500
I L = 0.8 æ ------------ö
è R DC ø
2500
I L = 0.5 æ ------------ö
è R DC ø
a. VA–VB (VAB) Voltage vs. Loop Current (Typical)
12
Am79574 Data Sheet
DC FEED CHARACTERISTICS (continued)
VBAT = –47.3 V
RDC = 40 kΩ
b. Loop Current vs. Load Resistance (Typical)
A
a
IL
RL
RSN
SLIC
RDC1
b
RDC2
CDC
RDC
B
Feed resistance programmed by RDC1 and RDC2
c. Feed Programming
Figure 1.
DC Feed Characteristics
SLIC Products
13
TEST CIRCUITS
VTX
A(TIP)
VTX
A(TIP)
RL
RT
2
SLIC
VL
VAB
SLIC
VAB
AGND
RL
RT
AGND
RL
2
RRX
RRX
RSN
B(RING) RSN
B(RING)
VRX
IL4-2 = –20 log (VAB / VRX)
IL2-4 = –20 log (VTX / VAB)
BRS = 20 log (VTX / VRX)
A. Two- to Four-Wire Insertion Loss
B. Four- to Two-Wire Insertion Loss and Balance Return Signal
900 Ω
1/ωC << RL
S1
VTX
A(TIP)
VTX
A(TIP)
RL
RT
2
R
SLIC
C
VL
VL
RT
AGND
IDC
VM
AGND
VS
SLIC
R
RL
S2
2
ZIN
RRX
RSN
B(RING)
RSN
B(RING)
S2 Open, S1 Closed:
L-T Long. Bal. = 20 log (VAB / VL)
L-4 Long. Bal. = 20 log (VTX / VL)
VRX
RRX
Note:
ZD is the desired impedance (e.g., the
characteristic impedance of the line).
RL = –20 log (2 VM / VS)
S2 Closed, S1 Open:
4-L Long. Sig. Gen. = 20 log (VL /VRX)
C. Longitudinal Balance
14
D. Two-Wire Return Loss Test Circuit
Am79574 Data Sheet
TEST CIRCUITS (continued)
RL
C
A(TIP)
A(TIP)
68 Ω
SM
56 Ω
IDC
RL
SLIC
B(RING)
RE
68 Ω
B(RING)
1/ωC << 90 Ω
SE
C
Current Feed or Ground Key
E. Single-Frequency Noise
VCC
F. Ground-Key Detection
6.2 kΩ
A(TIP)
A(TIP)
DET
15 pF
RL = 600 Ω
E0
B(RING)
B(RING)
RG = 2 kΩ
E1
H. Ground-Key Switching
G. Loop-Detector Switching
SLIC Products
15
PHYSICAL DIMENSIONS
PL032
.447
.453
.485
.495
.009
.015
.585
.595
.042
.056
.125
.140
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
.026
.032
TOP VIEW
SIDE VIEW
16-038FPO-5
PL 032
DA79
6-28-94 ae
REVISION SUMMARY
Revision B to Revision C
•
Minor changes were made to the data sheet style and format to conform to Legerity standards.
Revision C to Revision D
•
In the Pin Description table, inserted/changed TP pin description to: “Thermal pin. Connection for heat dissipation. Internally connected to substrate (QBAT). Leave as open circuit or connected to QBAT. In both cases, the
TP pins can connect to an area of copper on the board to enhance heat dissipation.”
•
Minor changes were made to the data sheet style and format to conform to Legerity standards.
Revision D to Revision E
•
The physical dimensions (PL032) were added to the Physical Dimensions section.
•
Deleted the Ceramic DIP and Plastic DIP parts (Am79571 and Am79573) and references to them.
•
Updated the Pin Description table to correct inconsistencies.
SLIC Products
16
Notes:
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