ETC AMD-K6-2E+

Preliminary Information
AMD-K6™-2E+
Embedded Processor
Data Sheet
Publication # 23542
Rev: A Amendment/0
Issue Date: September 2000
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
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iii
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
To order literature:
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iv
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
About this Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
1
AMD-K6™-2E+ Embedded Processor ........................................ 1
1.1
1.2
1.3
2
Internal Architecture ................................................................ 11
2.1
2.2
2.3
2.4
2.5
2.6
3
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . . 44
Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . 54
Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Descriptors and Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Instructions Supported by the AMD-K6™-2E+ Processor . . 63
Logic Symbol Diagram ............................................................... 91
Signal Descriptions .................................................................... 93
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
Contents
Microarchitecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . 16
Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 17
Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Software Environment ............................................................... 27
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4
5
AMD-K6™-2E+ Embedded Processor Features . . . . . . . . . . . 3
Process Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Super7™ Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
A20M# (Address Bit 20 Mask) . . . . . . . . . . . . . . . . . . . . . . . . . 94
A[31:3] (Address Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ADS# (Address Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ADSC# (Address Strobe Copy) . . . . . . . . . . . . . . . . . . . . . . . . 96
AHOLD (Address Hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
AP (Address Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
APCHK# (Address Parity Check) . . . . . . . . . . . . . . . . . . . . . . 99
BE[7:0]# (Byte Enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
BF[2:0] (Bus Frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
BOFF# (Backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
BRDY# (Burst Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
BRDYC# (Burst Ready Copy) . . . . . . . . . . . . . . . . . . . . . . . . 104
BREQ (Bus Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
CACHE# (Cacheable Access) . . . . . . . . . . . . . . . . . . . . . . . . 105
CLK (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
D/C# (Data/Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
D[63:0] (Data Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
v
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
5.19
5.20
5.21
5.22
5.23
5.24
5.25
5.26
5.27
5.28
5.29
5.30
5.31
5.32
5.33
5.34
5.35
5.36
5.37
5.38
5.39
5.40
5.41
5.42
5.43
5.44
5.45
5.46
5.47
5.48
5.49
5.50
5.51
5.52
5.53
5.54
5.55
5.56
5.57
6
Enhanced Power Management Features . . . . . . . . . . . . . . . 143
Dynamic Core Frequency and Core Voltage Control . . . . . 150
Bus Cycles ................................................................................. 153
7.1
7.2
7.3
7.4
vi
DP[7:0] (Data Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
EADS# (External Address Strobe) . . . . . . . . . . . . . . . . . . . . 109
EWBE# (External Write Buffer Empty) . . . . . . . . . . . . . . . . 110
FERR# (Floating-Point Error) . . . . . . . . . . . . . . . . . . . . . . . 111
FLUSH# (Cache Flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
HIT# (Inquire Cycle Hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
HITM# (Inquire Cycle Hit To Modified Line) . . . . . . . . . . . 113
HLDA (Hold Acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . 114
HOLD (Bus Hold Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 115
IGNNE# (Ignore Numeric Exception) . . . . . . . . . . . . . . . . . 116
INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
INTR (Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 118
INV (Invalidation Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 118
KEN# (Cache Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
LOCK# (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
M/IO# (Memory or I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
NA# (Next Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
NMI (Non-Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . 123
PCD (Page Cache Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . 124
PCHK# (Parity Check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
PWT (Page Writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
RESET (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
RSVD (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SCYC (Split Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SMI# (System Management Interrupt) . . . . . . . . . . . . . . . . 130
SMIACT# (System Management Interrupt Active) . . . . . . 131
STPCLK# (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
TCK (Test Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
TDI (Test Data Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
TDO (Test Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
TMS (Test Mode Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
TRST# (Test Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
VCC2DET (VCC2 Detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
VCC2H/L# (VCC2 High/Low) . . . . . . . . . . . . . . . . . . . . . . . . 136
VID[4:0] (Voltage Identification) . . . . . . . . . . . . . . . . . . . . . 137
W/R# (Write/Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
WB/WT# (Writeback or Writethrough) . . . . . . . . . . . . . . . . 139
Pin Tables by Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Bus Cycle Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
AMD PowerNow!™ Technology ............................................. 143
6.1
6.2
7
23542A/0—September 2000
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Bus States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Memory Reads and Writes . . . . . . . . . . . . . . . . . . . . . . . . . . 158
I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Contents
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
7.5
7.6
8
Power-on Configuration and Initialization ............................ 199
8.1
8.2
8.3
8.4
9
SMM Operating Mode and Default Register Values . . . . . 241
SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
I/O Trap Doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . . 250
Test and Debug ......................................................................... 251
13.1
13.2
13.3
Contents
Floating-Point Execution Unit . . . . . . . . . . . . . . . . . . . . . . . 237
Multimedia and 3DNow!™ Execution Units . . . . . . . . . . . . 239
Floating-Point and MMX™/3DNow!™ Instruction
Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
System Management Mode (SMM) ........................................ 241
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
13
EWBE# Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Memory Type Range Registers . . . . . . . . . . . . . . . . . . . . . . . 231
Memory-Range Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 233
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Floating-Point and Multimedia Execution Units .................. 237
11.1
11.2
11.3
12
MESI States in the L1 Data Cache and L2 Cache . . . . . . . . 207
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Cache Disabling and Flushing . . . . . . . . . . . . . . . . . . . . . . . 211
L2 Cache Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Cache-Line Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Cache-Line Replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Cache States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Writethrough and Writeback Coherency States . . . . . . . . . 227
A20M# Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . 227
Write Merge Buffer ................................................................. 229
10.1
10.2
10.3
10.4
11
Signals Sampled During the Falling Transition of
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
RESET Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
State of Processor After RESET . . . . . . . . . . . . . . . . . . . . . . 200
State of Processor After INIT . . . . . . . . . . . . . . . . . . . . . . . . 203
Cache Organization .................................................................. 205
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
10
Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . . 168
Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Three-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Boundary-Scan Test Access Port (TAP) . . . . . . . . . . . . . . . . 253
vii
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
13.4
13.5
13.6
14
Clock Control States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
EPM Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Electrical Data .......................................................................... 285
15.1
15.2
15.3
15.4
15.5
16
Cache Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
L2 Cache and Tag Array Testing . . . . . . . . . . . . . . . . . . . . . 264
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Clock Control ............................................................................ 275
14.1
14.2
14.3
14.4
14.5
14.6
15
23542A/0—September 2000
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Signal Switching Characteristics ............................................ 295
16.1
16.2
CLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 296
Clock Switching Characteristics for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
16.3 Clock Switching Characteristics for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
16.4 Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . 298
16.5 Output Delay Timings for 100-MHz Bus Operation . . . . . . 298
16.6 Input Setup and Hold Timings for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
16.7 Output Delay Timings for 66-MHz Bus Operation . . . . . . . 302
16.8 Input Setup and Hold Timings for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
16.9 RESET and Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . 306
16.10 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
17
Thermal Design ........................................................................ 313
17.1
17.2
17.3
18
Pin Designations ....................................................................... 321
18.1
18.2
19
Pins Designations for CPGA Package . . . . . . . . . . . . . . . . . 322
Pins Designations for OBGA Package . . . . . . . . . . . . . . . . . 326
Package Specifications ............................................................ 331
19.1
19.2
20
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . 313
Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 317
Layout and Airflow Considerations . . . . . . . . . . . . . . . . . . . 317
321-Pin Staggered CPGA Package Specification . . . . . . . . 331
349-Ball OBGA Package Specification . . . . . . . . . . . . . . . . . 332
Ordering Information .............................................................. 333
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
viii
Contents
Preliminary Information
23542A/0—September 2000
AMD-K6™-2E+ Embedded Processor Data Sheet
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
List of Figures
AMD-K6™-2E+ Processor Block Diagram . . . . . . . . . . . . . . . . . 13
Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
The Instruction Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AMD-K6™-2E+ Processor Decode Logic . . . . . . . . . . . . . . . . . . 19
AMD-K6™-2E+ Processor Scheduler . . . . . . . . . . . . . . . . . . . . . 22
Register X and Y Pipeline Functional Units . . . . . . . . . . . . . . . 24
EAX Register with 16-Bit and 8-Bit Name Components. . . . . . 28
Integer Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FPU Status Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FPU Control Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FPU Tag Word Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Packed Decimal Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Precision Real Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 34
MMX™/3DNow!™ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MMX™ Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . . . 36
3DNow!™ Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . 37
EFLAGS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Control Register 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Control Register 3 (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Control Register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Control Register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Control Register 0 (CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . . 42
Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . . 43
Machine-Check Address Register (MCAR) . . . . . . . . . . . . . . . . 45
Machine-Check Type Register (MCTR) . . . . . . . . . . . . . . . . . . . 45
Test Register 12 (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Time Stamp Counter (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . . 47
SYSCALL/SYSRET Target Address Register (STAR) . . . . . . . 48
Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . . 48
ix
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
x
23542A/0—September 2000
UC/WC Cacheability Control Register (UWCCR) . . . . . . . . . . 49
Processor State Observability Register (PSOR) . . . . . . . . . . . . 49
Page Flush/Invalidate Register (PFIR) . . . . . . . . . . . . . . . . . . . 50
L2 Tag or Data Location for AMD-K6™-2E+
Processor—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
L2 Data —EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
L2 Tag Information for AMD-K6™-2E+ Processor—EAX . . . . 52
Enhanced Power Management Register (EPMR) . . . . . . . . . . . 53
Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 54
Task State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4-Kbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4-Mbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Page Directory Entry 4-Kbyte Page Table (PDE) . . . . . . . . . . . 58
Page Directory Entry 4-Mbyte Page Table (PDE) . . . . . . . . . . 58
Page Table Entry (PTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Application Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . 60
System Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Enhanced Power Management Register (EPMR) . . . . . . . . . . 144
EPM 16-Byte I/O Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Bus Divisor and Voltage ID Control (BVC) Field . . . . . . . . . . 147
Processor State Observability Register (PSOR)—LowPower Versions of the Processor . . . . . . . . . . . . . . . . . . . . . . . 148
Waveform Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Non-Pipelined Single-Transfer Memory Read/Write and
Write Delayed by EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Misaligned Single-Transfer Memory Read and Write . . . . . . 161
Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . . 163
Burst Writeback due to Cache-Line Replacement . . . . . . . . . 165
Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Misaligned I/O Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Basic HOLD/HLDA Operation . . . . . . . . . . . . . . . . . . . . . . . . . 169
HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . 171
HOLD-Initiated Inquire Hit to Modified Line. . . . . . . . . . . . . 173
AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . . . . . . . 175
AHOLD-Initiated Inquire Hit to Shared or Exclusive Line . . 177
AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 179
AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
List of Figures
Preliminary Information
23542A/0—September 2000
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
Figure 99.
Figure 100.
Figure 101.
Figure 102.
Figure 103.
Figure 104.
Figure 105.
List of Figures
AMD-K6™-2E+ Embedded Processor Data Sheet
BOFF# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Basic Locked Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Locked Operation with BOFF# Intervention. . . . . . . . . . . . . . 187
Interrupt Acknowledge Operation . . . . . . . . . . . . . . . . . . . . . . 189
Basic Special Bus Cycle (Halt Cycle) . . . . . . . . . . . . . . . . . . . . 191
Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Stop Grant and Stop Clock Modes, Part 1 . . . . . . . . . . . . . . . . 194
Stop Grant and Stop Clock Modes, Part 2 . . . . . . . . . . . . . . . . 195
INIT-Initiated Transition from Protected Mode to Real
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
L1 and L2 Cache Organization for the AMD-K6™-2E+
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
L1 Cache Sector Organization. . . . . . . . . . . . . . . . . . . . . . . . . . 207
Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 217
Write Allocate Logic Mechanisms and Conditions . . . . . . . . . 218
Page Flush/Invalidate Register (PFIR) . . . . . . . . . . . . . . . . . . 224
UC/WC Cacheability Control Register (UWCCR) . . . . . . . . . 232
External Logic for Supporting Floating-Point Exceptions. . . 239
SMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
TAP State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
L2 Cache Organization for AMD-K6™-2E+ Processor . . . . . . 265
L2 Cache Sector and Line Organization . . . . . . . . . . . . . . . . . 265
L2 Tag or Data Location for the AMD-K6™-2E+
Processor—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
L2 Data - EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
L2 Tag Information for the AMD-K6™-2E+
Processor—EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
LRU Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . 270
Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . 271
Clock Control State Transitions for Standard-Power
Versions of the AMD-K6™-2E+ Processor . . . . . . . . . . . . . . . . 276
Clock Control State Transitions for Low-Power
Versions of the AMD-K6™-2E+ Processor . . . . . . . . . . . . . . . . 277
Suggested Component Placement for CPGA Package . . . . . . 292
CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Key to Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
xi
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
Figure 106.
Figure 107.
Figure 108.
Figure 109.
Figure 110.
Figure 111.
Figure 112.
Figure 113.
Figure 114.
Figure 115.
Figure 116.
Figure 117.
Figure 118.
Figure 119.
Figure 120.
Figure 121.
Figure 122.
Figure 123.
Figure 124.
Figure 125.
Figure 126.
xii
23542A/0—September 2000
Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . 310
Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . 311
TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
TRST# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Test Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Thermal Model (CPGA Package) . . . . . . . . . . . . . . . . . . . . . . . 315
Power Consumption and Thermal Resistance
(CPGA Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Processor Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . 316
Measuring Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 317
Voltage Regulator Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Airflow for a Heatsink with Fan . . . . . . . . . . . . . . . . . . . . . . . . 319
Airflow Path in a Dual-Fan System . . . . . . . . . . . . . . . . . . . . . 319
Airflow Path in an ATX Form-Factor System . . . . . . . . . . . . . 320
CPGA Connection Diagram (Top-Side View) . . . . . . . . . . . . . 322
CPGA Connection Diagram (Bottom-Side View) . . . . . . . . . . 323
OBGA Connection Diagram (Top-Side View) . . . . . . . . . . . . . 326
OBGA Connection Diagram (Bottom-Side View) . . . . . . . . . . 327
321-Pin Staggered CPGA Package Specification . . . . . . . . . . 331
349-Ball OBGA Package Specification . . . . . . . . . . . . . . . . . . . 332
List of Figures
Preliminary Information
23542A/0—September 2000
AMD-K6™-2E+ Embedded Processor Data Sheet
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
List of Tables
Execution Latency and Throughput of Execution Units . . . . . 23
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
General-Purpose Register Doubleword, Word, and Byte
Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AMD-K6™-2E+ Processor Model-Specific Registers . . . . . . . . 44
Extended Feature Enable Register (EFER) Definition . . . . . . 47
SYSCALL/SYSRET Target Address Register (STAR)
Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 54
Application Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
System Segment and Gate Types . . . . . . . . . . . . . . . . . . . . . . . . 61
Summary of Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . 62
Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MMX™ Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3DNow!™ Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3DNow!™ Technology DSP Extensions . . . . . . . . . . . . . . . . . . . 90
Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . 101
Output Pin Float Conditions for VCC2 High/Low. . . . . . . . . . 136
Input Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Input/Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . 141
Test Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Bus Cycle Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Enhanced Power Management Register (EPMR) Definition 145
EPM 16-Byte I/O Block Definition . . . . . . . . . . . . . . . . . . . . . . 146
Bus Divisor and Voltage ID Control (BVC) Definition . . . . . . 147
Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . 149
Bus-Cycle Order During Misaligned Memory Transfers . . . . 160
A[4:3] Address-Generation Sequence During Bursts . . . . . . . 162
Bus-Cycle Order During Misaligned I/O Transfers . . . . . . . . . 167
Interrupt Acknowledge Operation Definition. . . . . . . . . . . . . 188
Encodings for Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . 190
Output Signal State After RESET . . . . . . . . . . . . . . . . . . . . . . 200
Register State After RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
PWT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
PCD Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
CACHE# Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
L1 and L2 Cache States for Read and Write Accesses . . . . . . 221
xiii
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
xiv
23542A/0—September 2000
Valid L1 and L2 Cache States and Effect of Inquire Cycles . 225
L1 and L2 Cache States for Snoops, Flushes, and
Invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
EWBEC Settings and Performance . . . . . . . . . . . . . . . . . . . . . 231
WC/UC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Valid Masks and Range Sizes for UWCCR Register . . . . . . . 234
Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . 243
SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
I/O Trap Doubleword Configuration . . . . . . . . . . . . . . . . . . . . 248
I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Boundary Scan Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 257
Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . 259
Supported TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Tag versus Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
DR7 LEN and RW Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 273
Operating Ranges for Low-Power AMD-K6™-2E+ Devices . . 286
Operating Ranges for Standard-Power AMD-K6™-2E+
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
DC Characteristics for the AMD-K6™-2E+ Processor . . . . . . 287
Power Dissipation for Low-Power AMD-K6™-2E+ Devices . . 289
Power Dissipation for Standard-Power AMD-K6™-2E+
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Supported Voltages and Operating Frequencies for LowPower AMD-K6™-2E+ Processors Enabled with AMD
PowerNow!™ Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
CLK Switching Characteristics for 100-MHz Bus Operation . 296
CLK Switching Characteristics for 66-MHz Bus Operation . . 297
Output Delay Timings for 100-MHz Bus Operation . . . . . . . . 298
Input Setup and Hold Timings for 100-MHz Bus Operation . 300
Output Delay Timings for 66-MHz Bus Operation . . . . . . . . . 302
Input Setup and Hold Timings for 66-MHz Bus Operation . . 304
RESET and Configuration Signals for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
RESET and Configuration Signals for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
TCK Waveform and TRST# Timing at 25 MHz . . . . . . . . . . . . 308
Test Signal Timing at 25 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Package Thermal Specification for Low-Power
AMD-K6™-2E+ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Package Thermal Specification for Standard-Power
AMD-K6™-2E+ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Pin Differences Between the CPGA and OBGA Packages. . . 321
List of Tables
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Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
List of Tables
AMD-K6™-2E+ Embedded Processor Data Sheet
CPGA Pin Designations by Functional Grouping . . . . . . . . . . 324
CPGA Pin Designations for No Connect, Reserved, Power,
and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
OBGA Pin Designations by Functional Grouping . . . . . . . . . . 328
OBGA Pin Designations for No Connect, Reserved, Power,
and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
AMD-K6™-2E+ Embedded Processor Valid Ordering Part
Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
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Revision History
Date
Rev
September 2000
A
Initial published release.
September 2000
A
Second Printing: Revised trademarks.
September 2000
A
Second Printing: Changed setting of NOL2 bit on page 148.
September 2000
A
Second Printing: Revised headings in Table 59 on page 289, Table 60 on page 290, and Table 61 on
page 290. Changed Note 2 in Table 60 on page 290 to apply to 400-MHz parts only.
Revision History
Description
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About this Data Sheet
The AMD-K6™-2E+ Embedded Processor Data Sheet is the
complete specification of the AMD-K6™-2E+ embedded
processor.
Overview
This data sheet is organized into the following sections:
Chapter 1, “AMD-K6™-2E+ Embedded Processor” on page 1,
provides a list of the AMD-K6-2E+ processor’s distinguishing
characteristics, a description of the key features, and a
discussion about the Super7™ platform initiative.
Chapter 2, “Internal Architecture” on page 11, describes the
functional elements of the advanced design techniques, known
as the RISC86 ® microarchitecture, implemented by the
AMD-K6-2E+ processor.
Chapter 3, “Software Environment” on page 27, provides a
general overview of the AMD-K6-2E processor’s x86 software
environment and briefly describes the data types, registers,
operating modes, interrupts, and instructions supported by the
A M D -K 6 -2 E + p r o c e s s o r ’s a rch i t e c t u re a n d d e s i g n
implementation.
Chapter 4, “Logic Symbol Diagram” on page 91, contains the
AMD-K6-2E+ processor logic symbol diagram.
Chapter 5, “Signal Descriptions” on page 93, lists the signals
and their descriptions alphabetically and by function.
Chapter 6, “AMD PowerNow!™ Technology” on page 143,
describes the enhanced power management features available
on the low-power versions of the AMD-K6-2E+ processor.
Chapter 7, “Bus Cycles” on page 153, describes and illustrates
the timing and relationship of bus signals during various types
of bus cycles.
About this Data Sheet
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Chapter 8, “Power-on Configuration and Initialization” on
p a g e 1 9 9 , d e s c r i b e s h ow t h e s y s t e m l og i c re s e t s t h e
AMD-K6-2E+ processor using the RESET signal.
Chapter 9, “Cache Organization” on page 205, describes the
b a si c a rch it e c t ure a n d re s o u rc e s o f t h e A M D -K 6 -2 E+
processor’s internal caches.
Chapter 10, “Write Merge Buffer” on page 229, describes the 8byte write merge buffer and how merging multiple write cycles
into a single write cycle ultimately increases overall system
performance.
Chapter 11, “Floating-Point and Multimedia Execution Units”
on page 237, describes the AMD-K6-2E+ processor’s IEEE 754compatible and 854-compatible floating point execution unit,
the multimedia and 3DNow!™ technology execution units, and
the floating-point and MMX™/3DNow! technology instruction
compatibility.
Chapter 12, “System Management Mode (SMM)” on page 241,
describes SMM, the state-save area, entry into and exit from
SMM, exceptions and interrupts in SMM, memory allocation
and addressing in SMM, and the SMI# and SMIACT# signals.
Chapter 13, “Test and Debug” on page 251, describes the
various test and debug modes that enable the functional and
manufacturing testing of systems and boards that use the
AMD-K6-2E+ processor and that allow designers to debug the
instruction execution of software components.
Chapter 14, “Clock Control” on page 275, describes the five
modes of clock control support ed by t he AMD-K6-2E+
processor.
Chapter 15, “Electrical Data” on page 285, includes operating
ranges, absolute ratings, DC characteristics, power dissipation
data, power and grounding information, and decoupling
recommendations.
Chapter 16, “Signal Switching Characteristics” on page 295,
provides tables listing valid delay, float, setup, and hold timing
specifications for the AMD-K6-2E+ processor signals.
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Chapter 17, “Thermal Design” on page 313, lists the package
thermal specifications, discusses how to measure case
temperature, and provides layout and airflow considerations.
Chapter 18, “Pin Designations” on page 321, provides top- and
bottom-view connection diagrams for each package type and
lists the AMD-K6-2E+ processor’s pin designations by
functional grouping.
Chapter 19, “Package Specifications” on page 331, provides
diagrams showing the specifications for the 321-pin CPGA
package and the 349-ball OBGA package.
Chapter 20, “Ordering Information” on page 333, provides the
ordering part number (OPN) and valid OPN combinations.
About this Data Sheet
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1
AMD-K6™-2E+ Embedded Processor Data Sheet
AMD-K6™-2E+ Embedded Processor
The following are key features of the AMD-K6™-2E processor:
■
Member of the AMD-K6™E family of 32-bit embedded processors
◆ Brings the power, performance, and value of the AMD-K6 family to the
embedded market
◆
◆
■
■
■
■
Enables improved time-to-market by leveraging existing hardware and software
infrastructure and field-proven development tools
Offers a wide software- and platform-compatible growth path with product
longevity to help preserve development investments
Functionally-compatible embedded version of the AMD-K6-2+ processor with
internal 128-Kbyte L2 cache
◆ Provides higher Super7™ platform performance with reduced total system cost
®
®
◆ Microsoft Windows compatible processor
◆ x86 binary software compatible
◆ Supports real-time operating systems such as pSOS, QNX, RTXC, and VxWorks
Advanced 6-issue RISC86® superscalar microarchitecture
◆ Ten parallel specialized execution units
◆ Multiple sophisticated x86-to-RISC86 instruction decoders
◆ Advanced two-level branch prediction
◆ Speculative and out-of-order execution
◆ Register renaming and data forwarding
◆ Up to six RISC86 instructions per clock
Innovative cache design
◆ 192-Kbyte total internal cache
• Internal split, two-way set associative, 64-Kbyte L1 Cache
- 32-Kbyte instruction cache with additional 20-Kbytes of predecode cache
- 32-Kbyte writeback dual-ported data cache
- MESI protocol support
• Internal full-speed, four-way set associative, 128-Kbyte, L2 Cache
◆ Multiport internal cache design enabling simultaneous 64-bit reads/writes of
L1 and L2 caches
Super7 platform is Socket 7-compatible
◆ Leverages high-speed 100-MHz processor bus
◆ 2x Accelerated Graphic Port (AGP) support
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Takes advantage of existing system support, logic integration, and designs for
superior value
Provides an easy upgrade path for embedded applications and a bridge to
legacy applications
AMD PowerNow!™ technology dynamically manages power and performance
◆ Monitors application requirements for performance or power utilization
◆ Supports continuously varying operating frequency and voltage, delivering
performance on demand while dissipating the lowest amount of power possible
3DNow!™ technology for better multimedia and audio performance
◆ x86 instruction set extension accelerates 3D graphics and other singleprecision floating-point compute-intensive operations
◆
■
■
Offers fast frame rates on high-resolution graphics applications, superior
modeling of real-world environments and physics, life-like images and
graphics, and big-screen sound and video
◆ Additional 3DNow! technology DSP instructions enhance communications
applications
◆ Separate multiplier and ALU for superscalar instruction execution
High-performance IEEE 754-compatible and 854-compatible floating-point unit
High-performance industry-standard MMX™ instructions
◆ Dual-integer ALU for superscalar execution
Industry-standard System Management Mode (SMM)
IEEE 1149.1 boundary scan
321-Pin Ceramic Pin Grid Array (CPGA) or 349-Ball Organic Ball Grid Array
(OBGA) package
Low-voltage 0.18-micron process technology
◆ Split-plane power with support for full 3.3 V I/O
◆ Lower core voltages enable low-power operation
Operating frequencies
◆ Standard-power and standard-temperature devices: 400, 450, and 500 MHz
◆ Low-power and extended-temperature devices: 350, 400, and 450 MHz
◆
■
■
■
■
■
■
■
2
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1.1
AMD-K6™-2E+ Embedded Processor Data Sheet
AMD-K6™-2E+ Embedded Processor Features
The innovative AMD-K6-2E+ processor brings industry-leading performance to
embedded systems. Its Super7™ platform-compatible, 321-pin ceramic pin grid array
(CPGA) or 349-ball organic ball grid array (OBGA) package enables embedded
system designers to reduce time-to-market by leveraging today’s cost-effective,
industry-standard infrastructure.
Manufactured using AMD’s 0.18 micron low-power process, the AMD-K6-2E+
processor incorporates the innovative and efficient RISC86® microarchitecture, a
192-Kbyte total internal cache, a fast 100 MHz frontside bus, and a powerful IEEE
754-compatible and 854-compatible floating-point execution unit. The AMD-K6-2E+
processor also incorporates a superscalar MMX™ unit and AMD’s innovative 3DNow!
technology for high-performance multimedia and 3D graphics operation.
The AMD-K6-2E+ processor is a functionally compatible embedded version of the
AMD-K6-2+ processor with an internal 128-Kbyte L2 cache. The AMD-K6-2E+
processor offers a clock-for-clock performance boost at a lower total system cost over
existing Socket 7 systems because no external L2 cache is required. The low-power
versions of the AMD-K6-2E+ processor also support AMD’s enhanced power
management features, called AMD PowerNow! technology.
The AMD-K6-2E+ processor is part of the AMD-K6E family of embedded processors.
Within this family:
■
■
■
The AMD-K6-2E processor provides the best value and performance for costsensitive embedded applications.
The AMD-K6-2E+ with its 128-Kbyte internal L2 cache offers higher performance
balanced with cost.
The AMD-K6-IIIE+ with its 256-Kbyte internal L2 cache offers the highest
performance available for Super7 and Socket 7 platforms.
All AMD-K6E family processors in the CPGA package share the same footprint and
support the Socket 7-compatible Super7 platform. The AMD-K6E family provides
embedded designers with an assured growth plan and supply stability, along with
product longevity. All AMD-K6E family processors are x86-binary compatible,
allowing preservation of the initial software investment.
The AMD-K6-2E+ embedded processor is particularly well-suited for use in
applications where high performance is required. It is designed to offer compelling,
yet affordable, power and performance for high-end embedded applications, such as
information appliances, set-top boxes, embedded PCs, point-of-sale terminals, public
and private communications infrastructure, and industrial control.
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The AMD-K6-2E+ embedded processor is available in two versions.
■
■
The low-power version operates at the lowest core voltage in order to offer the
lowest available power and extended temperature ratings. Enhanced power
management features are provided via AMD PowerNow! technology in the lowpower versions of the processor.
The standard-power version has a 2.0-V core voltage and offers standard power
and temperature specifications similar to desktop PC processors.
Innovative Cache Design for Faster Data Access
Recognizing the benefits of a large and fast cache design in feeding performancehungry applications, AMD developed an innovative cache architecture that enhances
the performance available for embedded applications based on the Super7 platform.
AMD’s cache design innovations include:
■
■
■
An internal 128-Kbyte L2 write-back cache operating at the full speed of the
processor and complementing the 64-Kbyte L1 cache, which is standard in all
AMD-K6 family processors.
A multiport internal cache design, enabling simultaneous 64-bit reads and writes
to both the L1 cache and the L2 cache.
A 4-way set associative backside L2 cache design enabling optimal data
management and external frontside data bus bandwidth efficiency.
The processor's multiport internal cache design enables both the 64-Kbyte L1 cache
and the 128-Kbyte L2 cache to perform simultaneous 64-bit read and write operations
in a clock cycle. This multiport capability allows data to be processed faster and more
efficiently than non-multiported designs. In addition, the processor core can access
both L1 and L2 caches simultaneously, which further enhances overall CPU
throughput.
The cache design is exceptionally fast, with the backside 128-Kbyte L2 cache
operating at full processor speed.
For example, the internal L2 cache of an AMD-K6-2E+/450 processor operates at 450
MHz and provides nine times the peak bandwidth of an external L2 cache operating
at 100 MHz. The maximum peak bandwidth of an external L2 cache operating at 100
MHz is 800 Mbytes/s, while an internal L2 cache operating at 450 MHz delivers a
maximum peak bandwidth of 3,600 Mbytes/s per port. Because the internal L2 cache
of the AMD-K6-2E+ processor is dual-ported for simultaneous reads and writes, the
total peak bandwidth is doubled to 7,200 Mbytes/s, resulting in a maximum peak
bandwidth nine times as large as a 100-MHz cache implementation.
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3DNow!™ Technology
The AMD-K6-2E+ processor supports AMD’s 3DNow! technology, an extension to the
x86 instruction set that includes 21 new instructions to accelerate 3D graphics and
other single-precision floating-point compute intensive operations.
3DNow! technology was defined and implemented in collaboration with Microsoft,
application developers, and graphics vendors, and has received an enthusiastic
reception. It is compatible with today’s existing x86 software and requires no
operating system support, thereby enabling a broad class of applications to benefit
from 3DNow! technology.
The worldwide installed base of 3DNow! technology-enhanced PCs has grown to more
than 25 million desktop and notebook systems, revolutionizing the 3D experience
with up to four times the peak floating-point performance of previous sixth
generation solutions. Support for 3DNow! technology exists today in leading industrystandard APIs, including Microsoft® DirectX and SGI’s OpenGL APIs. Additionally,
numerous hardware and software products have been optimized for 3DNow!
technology. AMD is now bringing this advanced capability to embedded systems.
3DNow! technology enables fast frame rates on high-resolution 3D-rendered scenes,
realistic physical modeling of real-world environments, sharp and detailed 3D
imaging, smooth video playback, and theater-quality audio.
In addition, the AMD-K6-2E+ processor adds support for five new digital signal
processing (DSP) instructions, developed to enhance the performance of
communications applications, including soft xDSL modems, MP3 recording, and
Dolby Digital and Surround Sound processing.
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AMD PowerNow!™ Technology for Enhanced Power Management
AMD has added a number of new power management features to the low-power
versions of the AMD-K6-2E+ processor. Collectively, these hardware and software
features are called AMD PowerNow!™ technology.
AMD PowerNow! technology allows the AMD-K6-2E+ processor to run at different
frequencies and voltages, depending on the application’s need for maximum
performance or the most efficient power utilization.
AMD PowerNow! technology includes AMD’s unique “automatic mode” feature, which
allows the system to monitor application usage and to continuously vary the operating
frequency and voltage, delivering performance on demand while dissipating the
lowest amount of power possible.
■
■
When application demands require the processor to run at maximum
performance, the AMD PowerNow! technology steps up the performance to meet
the demand.
As platform demand for performance subsides, AMD PowerNow! technology can
dynamically drop into a lower power state.
AMD PowerNow! technology enables embedded products to dynamically manage
power and performance.
System Management Mode and Other Power Management Features
The AMD-K6-2E+ processor includes the complete industry-standard system
management mode (SMM), which is critical to system resource and power
management.
The AMD-K6-2E+ processor also features the industry-standard Stop-Clock
(STPCLK#) control circuitry and the Halt instruction, both required for
implementing the ACPI power management specification.
Microarchitecture
The AMD-K6-2E+ processor’s 6-issue RISC86 microarchitecture is a decoupled
decode/execution superscalar design that implements state-of-the-art design
techniques to achieve leading-edge performance.
Advanced design techniques implemented in the AMD-K6-2E+ processor include
multiple x86 instruction decode, single-clock internal RISC operations, ten execution
units that support superscalar operation, out-of-order execution, data forwarding,
speculative execution, and register renaming.
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In addition, the processor supports advanced branch prediction logic by
implementing an 8192-entry branch history table, a branch target cache, and a return
address stack, which combine to deliver better than a 95% prediction rate. These
design techniques enable the AMD-K6-2E+ processor to issue, execute, and retire
multiple x86 instructions per clock, resulting in excellent scaleable performance.
Industry-Standard x86 Architecture
The AMD-K6-2E+ processor is x86 binary code compatible. AMD’s extensive
experience through six generations of x86 processors has been carefully integrated
into the processor to enable compatibility with Windows® 98, Windows 95, Windows
3.x, Windows NT, DOS, Linux, OS/2, Unix, Solaris, NetWare®, and other leading x86
operating systems and applications. The AMD-K6-2E+ processor is also compatible
with leading real-time operating systems (RTOS) commonly used in embedded
applications, such as pSOS, QNX, RTXC, and VxWorks. Additionally, the AMD
FusionE86SM third-party tool support program offers extensive development support
for AMD-K6-2E+ processor designs.
The AMD-K6-2E+ processor is Super7 and Socket 7-compatible. The Super7 platform
is an extension to the popular and robust Socket 7 platform. See “Super7™ Platform”
on page 8 for more information.
AMD is the world’s second-leading supplier of PC processors compatible with the
Wi n d ow s o p e ra t i n g s y s t e m , h av i n g s h i p p e d m o re t h a n 1 2 0 m i l l i o n x 8 6
microprocessors, including more than 60 million Windows-compatible processors. The
AMD-K6-2E+ processor for embedded applications is the latest member in this long
line of processors. With its combination of state-of-the-art features, industry-leading
performance, high-performance 3DNow! technology and multimedia engines, x86
compatibility, and low-cost infrastructure, the AMD-K6-2E+ processor is the superior
choice for high-performance embedded systems.
1.2
Process Technology
The AMD-K6-2E+ processor is implemented using an AMD-developed, state-of-the-art
low power 0.18-micron process technology. This process technology features a splitplane design that enables the AMD-K6-2E+ processor to deliver excellent
performance solutions while utilizing a lower processor core voltage, which results in
lower power consumption, while the I/O portion operates at the industry-standard
3.3-V level.
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1.3
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Super7™ Platform
The Super7 platform is an extension to the popular Socket 7 platform. AMD and its
industry partners have invested in the future of Socket 7 with the Super7 platform
initiative. The goal of the initiative is to maintain the competitive vitality of the
Socket 7 infrastructure through a series of enhancements, including the development
of an industry-standard 100-MHz processor bus protocol.
In addition to the 100-MHz processor bus protocol, the Super7 initiative includes the
introduction of chipsets that support the AGP specification, and support for a
backside L2 cache. Currently, over 40 motherboard vendors and all major BIOS and
chipset vendors offer Super7-based products.
All AMD-K6 embedded processors in CPGA packages remain pin compatible with
existing Socket 7 solutions; however, for maximum system performance, the
AMD-K6-2E+processor works optimally in Super7 designs that incorporate advanced
features such as support for the 100-MHz frontside bus and AGP graphics.
100-MHz Processor Bus
The AMD-K6-2E+ processor supports a 100-MHz, 800 Mbyte/second frontside bus to
provide a high-speed interface to Super7 platform-based chipsets. The 100-MHz
interface speeds up access to main memory by 50 percent over the 66-MHz Socket 7
interface — resulting in a significant 10 percent increase in overall system
performance.
Accelerated Graphics Port Support
Accelerated Graphics Port (AGP) support improves the performance of video
graphics systems that have small amounts of video memory on the graphics card. The
industry-standard AGP specification enables a 133-MHz graphics interface and will
scale to even higher levels of performance.
Support For Backside L2 Cache
The Super7 platform has the ‘headroom’ to support higher-performance AMD-K6
processors like the AMD-K6-2E+ processor, which features a full-speed, internal
backside 128-Kbyte L2 cache designed to enable new levels of performance to
leading-edge embedded systems.
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Super7™ Platform Advantages
The Super7 platform:
■
■
■
■
■
■
Delivers performance and features competitive with alternate platforms at the
same clock speed, and at a significantly lower cost
Takes advantage of existing system designs for superior value
Enables OEMs and resellers to take advantage of mature, high-volume
infrastructure supported by multiple BIOS, chipset, graphics, and motherboard
suppliers
Reduces inventory and design costs with one motherboard for a wide range of
products
Builds on a huge installed base of more than 100 million motherboards
Provides an easy upgrade path for embedded applications, as well as a bridge to
legacy applications
By taking advantage of the low-cost, mature Socket 7 infrastructure, the Super7
platform will continue to provide superior value and leading-edge performance for
embedded systems.
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2
Internal Architecture
The AMD-K6-2E+ processor implements advanced design
techniques known as the RISC86 microarchitecture. The
RISC86 microarchitecture is a decoupled decode/execution
design approach that yields superior sixth-generation
performance for x86-based software. This chapter describes the
techniques used and the functional elements of the RISC86
microarchitecture.
2.1
Microarchitecture Overview
When discussing processor design, it is important to understand
t h e t e r m s a r ch i t e c t u re , m i c r o a r ch i t e c t u re , a nd d e s i g n
implementation.
■
■
■
Chapter 2
Architecture refers to the instruction set and features of a
processor that are visible to software programs running on
the processor. The architecture determines what software
the processor can run. The architecture of the AMD-K6-2E+
processor is the industry-standard x86 instruction set.
Microarchitecture refers to the design techniques used in the
processor to reach the target cost, performance, and
functionality goals. The AMD-K6 family of processors are
based on a sophisticated RISC core known as the Enhanced
RISC86 microarchitecture. The Enhanced RISC86
microarchitecture is an advanced, second-order decoupled
decode/execution
design
approach
that
enables
industry-leading performance for x86-based software.
Design implementation refers to the actual logic and circuit
designs from which the processor is created according to the
microarchitecture specifications.
Internal Architecture
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Enhanced RISC86®
Microarchitecture
23542A/0—September 2000
Th e E n h anced RISC86 mi croarchi tecture d efi ne s t h e
characteristics of the AMD-K6 family of processors. The
innovative RISC86 microarchitecture approach implements the
x86 instruction set by internally translating x86 instructions
into RISC86 operations. These RISC86 operations were
specially designed to include direct support for the x86
instruction set while observing the RISC performance
principles of fixed length encoding, regularized instruction
fields, and a large register set.
Th e Enh a n c e d R I S C8 6 m ic ro arch i t e c t u re u s e d i n t h e
AMD-K6-2E+ processor enables higher processor core
performance and promotes straightforward extensions, such as
those added in the current AMD-K6-2E+ processor and those
planned for the future. Instead of directly executing complex
x86 instructions, which have lengths of 1 to 15 bytes, the
AMD-K6-2E+ processor executes the simpler and easier
fixed-length RISC86 operations, while maintaining the
instruction coding efficiencies found in x86 programs.
The AMD-K6-2E+ processor contains parallel decoders, a
centralized RISC86 operation scheduler, and ten execution
units that support superscalar operation — multiple decode,
execution, and retirement—of x86 instructions. These elements
are packed into an aggressive and highly efficient six-stage
pipeline.
AMD-K6-2E+
Processor Block
Diagram
As shown in Figure 1 on page 13, the high-performance,
out-of-order execution engine of the AMD-K6-2E+ processor is
mated to a split, level-one, 64-Kbyte, writeback cache with 32
Kbytes of instruction cache and 32 Kbytes of data cache.
Backing up the level-one (L1) cache is a large, unified, level-two
(L2), 128-Kbyte, writeback cache. The L1 instruction cache
feeds the decoders and, in turn, the decoders feed the
scheduler. The ICU issues and retires RISC86 operations
contained in the scheduler. The system bus interface is an
industry-standard 64-bit Super7 and Socket 7 demultiplexed
bus.
The AMD-K6-2E+ processor combines the latest in processor
microarchitecture to provide the highest x86 performance for
today’s computational systems. The AMD-K6-2E+ processor
offers true sixth-generation performance and x86 binary
software compatibility.
12
Internal Architecture
Chapter 2
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AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
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Figure 1. AMD-K6™-2E+ Processor Block Diagram
Decoders
Decoding of the x86 instructions begins when the on-chip L1
instruction cache is filled. Predecode logic determines the
length of an x86 instruction on a byte-by-byte basis. This
p re d e c o d e i n fo r m a t i o n i s s t o re d , a l o n g w i t h t h e x 8 6
instructions, in the L1 instruction cache, to be used later by the
decoders. The decoders translate on-the-fly, with no additional
latency, up to two x86 instructions per clock into RISC86
operations.
Note: In this chapter, “clock” refers to a processor clock.
The AMD-K6-2E+ processor categorizes x86 instructions into
three types of decodes—short, long, and vector. The decoders
process either two short, one long, or one vector decode at a
time.
The three types of decodes have the following characteristics:
■
Chapter 2
Short decodes—x86 instructions less than or equal to seven
bytes in length
Internal Architecture
13
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
■
Long decodes—x86 instructions less than or equal to 11
bytes in length
■
Vector decodes—complex x86 instructions
Short and long decodes are processed completely within the
decoders. Vector decodes are started by the decoders and then
completed by fetched sequences from an on-chip ROM. After
decoding, the RISC86 operations are delivered to the scheduler
for dispatching to the executions units.
Scheduler/Instruction
Control Unit
The centralized scheduler or buffer is managed by the
Instruction Control Unit (ICU). The ICU buffers and manages
up to 24 RISC86 operations at a time. This equals from 6 to 12
x86 instructions. This buffer size (24) is perfectly matched to
t h e p ro c e s s o r ’s s i x -s t a g e R I S C 8 6 p i p e l i n e a n d f o u r
RISC86-operations decode rate.
The scheduler accepts as many as four RISC86 operations at a
time from the decoders and retires up to four RISC86
o p e ra t i o n s p e r c l o ck cy c l e . T h e I C U i s c a p a b l e o f
simultaneously issuing up to six RISC86 operations at a time to
the execution units. This consists of the following types of
operations:
■
■
■
■
■
■
Registers
When managing the RISC86 operations, the ICU uses 69
p hy s i c a l re g i s t e rs c o n t a i n e d w i t h i n t h e R I S C 8 6
microarchitecture.
■
14
Memory load operation
Memory store operation
Complex integer, MMX or 3DNow! register operation
Simple integer, MMX or 3DNow! register operation
Floating-point register operation
Branch condition evaluation
Forty-eight of the physical registers are located in a general
register file.
•
Twenty-four of these are rename registers.
•
The other twenty-four are committed or architectural
registers, consisting of 16 scratch registers and 8 registers
that correspond to the x86 general-purpose registers—
EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI.
Internal Architecture
Chapter 2
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
■
An analogous set of 21 registers is available specifically for
MMX and 3DNow! operations.
Twelve of these are MMX/3DNow! rename registers.
Nine are MMX/3DNow! committed or architectural registers,
consisting of one scratch register and eight registers that
correspond to the MMX registers (mm0–mm7, as shown in
Figure 17 on page 35.
•
■
Branch Logic
Th e A M D -K 6 -2 E + p ro c e s s o r i s d e s i g n e d w i t h h i g h ly
sophisticated dynamic branch logic consisting of the following:
■
Branch history/prediction table
Branch target cache
■
Return address stack
■
The AMD-K6-2E+ processor implements a two-level branch
prediction scheme based on an 8192-entry branch history table.
The branch history table stores prediction information that is
used for predicting conditional branches. Because the branch
history table does not store predicted target addresses, special
address ALUs calculate target addresses on the fly during
instruction decode.
Th e b ra n ch t a rg e t c a ch e a u g m e n t s p re d i c t e d b ra n ch
performance by avoiding a one clock cache-fetch penalty. This
specialized target cache does this by supplying the first 16 bytes
of target instructions to the decoders when branches are
predicted. The return address stack is a unique device
specifically designed for optimizing CALL and RETURN pairs.
In summary, the AMD-K6-2E+ processor uses dynamic branch
logic to minimize delays due to the branch instructions that are
common in x86 software.
3DNow!™ Technology
Chapter 2
AMD has taken a lead role in improving the multimedia and 3D
capabilities of the x86 processor family with the introduction of
3DNow! technology, which uses a packed, single-precision,
floating-point data format and Single Instruction Multiple Data
(SIMD) operations based on the MMX technology model.
Internal Architecture
15
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
2.2
23542A/0—September 2000
Cache, Instruction Prefetch, and Predecode Bits
The writeback level-one (L1) cache on the AMD-K6-2E+
processor is organized as a separate 32-Kbyte instruction cache
and a 32-Kbyte data cache with two-way set associativity.
The level-two (L2) cache is 128 Kbytes, and is organized as a
unified, four-way set-associative cache. The cache line size is 32
bytes, and lines are fetched from external memory using an
efficient pipelined burst transaction.
As the L1 instruction cache is filled from the L2 cache or from
external memory, each instruction byte is analyzed for
instruction boundaries using predecoding logic. Predecoding
annotates information (5 bits per byte) to each instruction byte
that later enables the decoders to efficiently decode multiple
instructions simultaneously.
Cache
Tag Address
The processor cache design takes advantage of a sectored
organization (see Figure 2). Each sector consists of 64 bytes
configured as two 32-byte cache lines. The two cache lines of a
sector share a common tag but have separate pairs of MESI
(Modified, Exclusive, Shared, Invalid) bits that track the state
of each cache line.
Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Figure 2. Cache Sector Organization
Two forms of cache misses and associated cache fills can take
place—a tag-miss cache fill and a tag-hit cache fill.
■
■
16
Tag-Miss Cache Fill—The L1 cache miss is due to a tag
mismatch, in which case the required cache line is filled
either from the L2 cache or from external memory, and the
L1 cache line within the sector that was not required is
marked as invalid.
Tag-Hit Cache Fill—The address matches the tag, but the
requested cache line is marked as invalid. The required L1
cache line is filled from the L2 cache or from external
memory, and the L1 cache line within the sector that is not
required remains in the same cache state.
Internal Architecture
Chapter 2
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Prefetching
The AMD-K6-2E+ processor conditionally performs cache
prefetching, which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
burst read cycles occurring back-to-back or, if allowed, as
pipelined cycles.
The 3DNow! technology includes an instruction called
PREFETCH that allows a cache line to be prefetched into the
L1 data cache and the L2 cache. The PREFETCH instruction
format is defined in Table 15, “3DNow!™ Instructions,” on
page 89. For more detailed information, see the 3DNow!™
Technology Manual, order# 21928.
Predecode Bits
2.3
Decoding x86 instructions is particularly difficult because the
instructions are variable-length and can be from 1 to 15 bytes
long. Predecode logic supplies the five predecode bits that are
associated with each instruction byte. The predecode bits
indicate the number of bytes to the start of the next x86
instruction. The predecode bits are stored in an extended
instruction cache alongside each x86 instruction byte as shown
in Figure 2 on page 16. The predecode bits are passed with the
instruction bytes to the decoders where they assist with parallel
x86 instruction decoding.
Instruction Fetch and Decode
Instruction Fetch
The processor can fetch up to 16 bytes per clock out of the L1
instruction cache or branch target cache. The fetched
information is placed into a 16-byte instruction buffer that
feeds directly into the decoders (see Figure 3 on page 18).
Fetching can occur along a single execution stream with up to
seven outstanding branches taken.
The instruction fetch logic is capable of retrieving any 16
contiguous bytes of information within a 32-byte boundary.
There is no additional penalty when the 16 bytes of instructions
lie across a cache line boundary. The instruction bytes are
loaded into the instruction buffer as they are consumed by the
decoders.
Although instructions can be consumed with byte granularity,
the instruction buffer is managed on a memory-aligned word
Chapter 2
Internal Architecture
17
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
(two bytes) organization. Therefore, instructions are loaded and
replaced with word granularity. When a control transfer
occurs — such as a JMP instruction — the entire instruction
buffer is flushed and reloaded with a new set of 16 instruction
bytes.
16 Bytes
32-Kbyte Level-One
Instruction Cache
Branch-Target Cache
16 x 16 Bytes
16 Bytes
2:1
Branch Target
Address Adders
Return Address Stack
16 x 16 Bytes
Fetch Unit
16 Instruction Bytes
plus
16 Sets of Predecode Bits
Instruction Buffer
Figure 3. The Instruction Buffer
Instruction Decode
The AMD-K6-2E+ processor decode logic is designed to decode
multiple x86 instructions per clock (see Figure 4 on page 19).
The decode logic accepts x86 instruction bytes and their
predecode bits from the instruction buffer, locates the actual
instruction boundaries, and generates RISC86 operations from
these x86 instructions.
RISC86 operations are fixed-length internal instructions. Most
RISC86 operations execute in a single clock. RISC86 operations
are combined to perform every function of the x86 instruction
set. Some x86 instructions are decoded into as few as zero
RISC86 operations — for instance a NOP — or one RISC86
18
Internal Architecture
Chapter 2
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
operation — a register-to-register add. More complex x86
instructions are decoded into several RISC86 operations.
Instruction Buffer
Short Decoder #1
Short Decoder #2
Long Decoder
On-Chip ROM
Vector Decoder
RISC86® Sequencer
Vector Address
4 RISC86 Operations
Figure 4. AMD-K6™-2E+ Processor Decode Logic
The AMD-K6-2E+ processor uses a combination of decoders to
convert x86 instructions into RISC86 operations. The hardware
consists of three sets of decoders—two parallel short decoders,
one long decoder, and one vector decoder.
Parallel Short Decoders. The two parallel short decoders translate
the most commonly-used x86 instructions ( moves, shifts,
branches, ALU, FPU) and the extensions to the x86 instruction
set (including MMX and 3DNow! instructions) into zero, one, or
two RISC86 operations each. The short decoders only operate
on x86 instructions that are up to seven bytes long. In addition,
Chapter 2
Internal Architecture
19
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
they are designed to decode up to two x86 instructions per
clock.
Long Decoder. The commonly-used x86 instructions that are
greater than seven bytes but not more than 11 bytes long and
less-commonly-used x86 instructions that are up to seven bytes
long are handled by the long decoder. The long decoder only
performs one decode per clock and generates up to four RISC86
operations.
Vector Decoder. All other translations (complex instructions,
serializing conditions, interrupts and exceptions, etc.) are
handled by a combination of the vector decoder and RISC86
operation sequences fetched from an on-chip ROM. For
complex operations, the vector decoder logic provides the first
set of RISC86 operations and a vector (initial ROM address) to a
sequence of further RISC86 operations. The same types of
RISC86 operations are fetched from the ROM as those that are
generated by the hardware decoders.
Note: Although all three sets of decoders are simultaneously fed a
copy of the instruction buffer contents, only one of the three
types of decoders is used during any one decode clock.
Grouped Operations. The decoders or the on-chip RISC86 ROM
always generate a group of four RISC86 operations. For decodes
that cannot fill the entire group with four RISC86 operations,
RISC86 NOP operations are placed in the empty locations of
the grouping. For example, a long-decoded x86 instruction that
converts to only three RISC86 operations is padded with a
single RISC86 NOP operation and then passed to the scheduler.
Up to six groups or 24 RISC86 operations can be placed in the
scheduler at a time.
Floating Point Instructions. All of the common, and a few of the
uncommon, floating-point instructions (also known as ESC
instructions) are hardware decoded as short decodes. This
decode generates a RISC86 floating-point operation and,
optionally, an associated floating-point load or store operation.
Floating-point or ESC instruction decode is only allowed in the
first short decoder, but non-ESC instructions can be decoded
simultaneously by the second short decoder along with an ESC
instruction decode in the first short decoder.
20
Internal Architecture
Chapter 2
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
MMX™ and 3DNow!™ Instructions. All of the MMX and 3DNow!
instructions, with the exception of the EMMS, FEMMS, and
PREFETCH instructions, are hardware decoded as short
decodes. The MMX instruction decode generates a RISC86
MMX operation and, optionally, an associated MMX load or
store operation. A 3DNow! instruction decode generates a
RISC86 3DNow! operation and, optionally, an associated load or
store operation. MMX and 3DNow! instructions can be decoded
in either or both of the short decoders.
2.4
Centralized Scheduler
The scheduler is the heart of the AMD-K6-2E+ processor (see
Figure 5 on page 22). It contains the logic necessary to manage
out-of-order execution, data forwarding, register renaming,
simultaneous issue and retirement of multiple RISC86
operations, and speculative execution.
The scheduler’s buffer can hold up to 24 RISC86 operations.
This equates to a maximum of 12 x86 instructions. The
scheduler can issue RISC86 operations from any of the 24
locations in the buffer. When possible, the scheduler can
simultaneously issue a RISC86 operation to any available
e x e c u t i o n u n i t ( s t o re , l o a d , b ra n ch , re g i s t e r X
integer/multimedia, register Y integer/multimedia, or
floating-point). In total, the scheduler can issue up to six and
retire up to four RISC86 operations per clock.
The main advantage of the scheduler and its operation buffer is
the ability to examine an x86 instruction window equal to 12
x86 instructions at one time. This advantage is due to the fact
that the scheduler operates on the RISC86 operations in
parallel and allows the AMD-K6-2E+ processor to perform
dynamic on-the-fly instruction code scheduling for optimized
execution. Although the scheduler can issue RISC86 operations
for out-of-order execution, it always retires x86 instructions in
order.
Chapter 2
Internal Architecture
21
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
From Decode Logic
RISC86 #0
RISC86 #1
RISC86 #2
Centralized RISC86®
Operation Scheduler
RISC86 #3
RISC86 Issue Buses
RISC86 Operation Buffer
Figure 5. AMD-K6™-2E+ Processor Scheduler
2.5
Execution Units
The AMD-K6-2E+ processor contains ten parallel execution
units—store, load, integer X ALU, integer Y ALU, MMX ALU
(X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow! ALU,
floating-point, and branch condition. Each unit is independent
and capable of handling the RISC86 operations issued to it.
Table 1 on page 23 details the execution units, functions
performed within these units, operation latency, and operation
throughput.
Note that the integer, MMX, and 3DNow! execution units share
the register X and Y issue pipelines. See “Register X and Y
Pipelines” on page 24.
The store and load execution units are two-stage pipelined
designs.
■
22
The store unit performs data writes and register calculation
for LEA/PUSH instructions. Data memory and register
Internal Architecture
Chapter 2
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
■
writes from stores are available after one clock. Store
operations are held in a store queue prior to execution. From
there, they execute in order.
The load unit performs data memory reads. Data is available
from the load unit after two clocks.
The I nte ger X executio n unit can operat e on a ll AL U
operations, multiplies, divides (signed and unsigned), shifts,
and rotates.
The Integer Y execution unit can operate on the basic word and
doubleword ALU operations — ADD, AND, CMP, OR, SUB,
XOR, zero-extend and sign-extend operands.
The branch condition unit is separate from the branch
prediction logic (see “Branch-Prediction Logic” on page 25) in
that it resolves conditional branches such as JCC and LOOP
after the branch condition has been evaluated.
Table 1.
Execution Latency and Throughput of Execution Units
Functional Unit
Latency
Throughput
LEA/PUSH, Address (Pipelined)
1
1
Memory Store (Pipelined)
1
1
Memory Loads (Pipelined)
2
1
Integer ALU
1
1
2–3
2–3
Integer Shift
1
1
Multimedia
(processes
MMX instructions)
MMX ALU
1
1
MMX Shifts, Packs, Unpack
1
1
MMX Multiply
2
1
Integer Y
Basic ALU (16-bit and 32-bit operands)
1
1
Branch
Resolves Branch Conditions
1
1
FPU
FADD, FSUB, FMUL
2
2
3DNow! ALU
2
1
3DNow! Multiply
2
1
3DNow! Convert
2
1
Store
Load
Integer X
3DNow!
Chapter 2
Function
Integer Multiply
Internal Architecture
23
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
Register X and Y
Pipelines
23542A/0—September 2000
Th e f u n c t io n a l u n i t s t h a t ex ec u t e MM X a n d 3 D N ow !
instructions share pipeline control with the Integer X and
Integer Y units.
The register X and Y functional units are attached to the issue
bus for the register X execution pipeline or the issue bus for the
register Y execution pipeline or both.
Each register pipeline has dedicated resources that consist of
an integer execution unit and an MMX ALU execution unit,
therefore allowing superscalar operation on integer and MMX
instructions.
In addition, both the X and Y issue buses are connected to the
3DNow! ALU, the MMX/3DNow! multiplier and MMX shifter,
which allows the appropriate RISC86 operation to be issued
through either bus. Figure 6 shows the details of the X and Y
register pipelines.
Scheduler
Buffer
(24 RISC86® Operations)
Issue Bus
for the
Register Y
Execution
Pipeline
Issue Bus
for the
Register X
Execution
Pipeline
Integer X
ALU
MMXÉ
ALU
MMX/
3DNow!É
Multiplier
MMX
Shifter
3DNow!
ALU
MMX
ALU
Integer Y
ALU
Figure 6. Register X and Y Pipeline Functional Units
24
Internal Architecture
Chapter 2
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
2.6
Branch-Prediction Logic
Sophisticated branch logic that can minimize or hide the impact
of changes in program flow is designed into the AMD-K6-2E+
processor. Branches in x86 code fit into two categories:
■
■
Unconditional branches always change program flow (that is,
the branches are always taken)
Conditional branches may or may not divert program flow
(that is, the branches are taken or not-taken). When a
conditional branch is not taken, the processor simply
continues decoding and executing the next instructions in
memory.
Typical applications have up to 10% of unconditional branches
a n d a n o t h e r 1 0 % t o 2 0 % c o n d i t i o n a l b ra n ch e s . Th e
AMD-K6-2E+ processor branch logic has been designed to
handle this type of program behavior and to minimize its
negative effects on instruction execution, such as stalls due to
delayed instruction fetching and the draining of the processor
pipeline. The branch logic contains an 8192-entry branch
history table, a 16-entry by 16-byte branch target cache, a
16-entry return address stack, and a branch execution unit.
Branch History Table
The AMD-K6-2E+ processor handles unconditional branches
without any penalty by redirecting instruction fetching to the
target address of the unconditional branch. However,
c o n d i t i o n a l b ra n che s re q u i re t h e u se o f t h e dy n a m i c
branch-prediction mechanism built into the AMD-K6-2E+
processor.
A two-level adaptive history algorithm is implemented in an
8192-entry branch history table. This table stores executed
branch information, predicts individual branches, and predicts
the behavior of groups of branches.
To a c c o m m o d a t e t h e l a rg e b ra n ch h i s t o ry t a b l e , t h e
AMD-K6-2E+ processor does not store predicted target
addresses. Instead, the branch target addresses are calculated
on-the-fly using ALUs during the decode stage. The adders
calculate all possible target addresses before the instructions
are fully decoded and the processor chooses which addresses
are valid.
Chapter 2
Internal Architecture
25
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
Branch Target Cache
23542A/0—September 2000
To avoid a one clock cache-fetch penalty when a branch is
predicted taken, a built-in branch target cache supplies the first
16 bytes of instructions directly to the instruction buffer
(assuming the target address hits this cache). (See Figure 3 on
page 18.)
The branch target cache is organized as 16 entries of 16 bytes.
In total, the branch prediction logic achieves branch prediction
rates greater than 95%.
Return Address Stack
The return address stack is a special device designed to
optimize CALL and RET pairs. Software is typically compiled
with subroutines that are frequently called from various places
in a program. This is usually done to save space.
Entry into the subroutine occurs with the execution of a CALL
instruction. At that time, the processor pushes the address of
the next instruction in memory following the CALL instruction
onto the stack (allocated space in memory). When the processor
encounters a RET instruction (within or at the end of the
subroutine), the branch logic pops the address from the stack
and begins fetching from that location. To avoid the latency of
main memory accesses during CALL and RET operations, the
return address stack caches the pushed addresses.
Branch Execution
Unit
The branch execution unit enables efficient speculative
execution. This unit gives the processor the ability to execute
instructions beyond conditional branches before knowing
whether the branch prediction was correct.
The AMD-K6-2E+ processor does not permanently update the
x86 registers or memory locations until all speculatively
executed conditional branch instructions are resolved. When a
prediction is incorrect, the processor backs out to the point of
the mispredicted branch instruction and restores all registers.
Th e A M D -K 6 -2 E + p ro c e s s o r c a n s u p p o r t u p t o s eve n
outstanding branches.
26
Internal Architecture
Chapter 2
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
3
Software Environment
This chapter provides a general overview of the AMD-K6-2E+
processor’s x86 software environment and briefly describes the
data types, registers, operating modes, interrupts, and
instruc tions supported by the AMD-K6-2E+ processor
architecture and design implementation.
The AMD-K6-2E+ processor implements the same ten ModelSpecific Registers (MSRs) as the AMD-K6-2 and AMD-K6-2E
processors Model 8/[F:8], and the bits and fields within these
ten MSRs are defined identically. The AMD-K6-2E+ processor
supports an additional MSR for cache control. The low-power
versions of the AMD-K6-2E+ processor support a twelfth MSR
to control the AMD PowerNow! technology functions.
See “Model-Specific Registers (MSR)” on page 44 for the MSR
definitions.
The model number for the AMD-K6-2E+ processor is Model
D/[7:4], where the actual stepping can be any value in the range
[7:4].
3.1
Registers
The AMD-K6-2E+ processor contains all the registers defined
by the x86 architecture, including general-purpose, segment,
floating-point, MMX/3DNow!, EFLAGS, control, task, debug,
test, and descriptor/memory-management registers.
In addition, this cha pt er provides info rmation on t he
AMD-K6-2E+ processor MSRs.
Note: Areas of the register designated as Reserved should not be
modified by software.
Chapter 3
Software Environment
27
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
General-Purpose
Registers
23542A/0—September 2000
The eight 32-bit x86 general-purpose registers are used to hold
integer data or memory pointers used by instructions. Table 2
contains a list of the general-purpose registers and the
functions for which they are used.
Table 2.
General-Purpose Registers
Register Function
EAX
Commonly used as an accumulator
EBX
Commonly used as a pointer
ECX
Commonly used for counting in loop operations
EDX
Commonly used to hold I/O information and to pass parameters
EDI
Commonly used as a destination pointer by the ES segment
ESI
Commonly used as a source pointer by the DS segment
ESP
Used to point to the stack segment
EBP
Used to point to data within the stack segment
In order to support byte and word operations, EAX, EBX, ECX,
and EDX can also be used as 8-bit and 16-bit registers. The
shorter registers are overlaid on the longer ones. For example,
the name of the 16-bit version of EAX is AX (low 16 bits of
EAX) and the 8-bit names for AX are AH (high order bits) and
AL (low order bits). The same naming convention applies to
EBX, ECX, and EDX.
EDI, ESI, ESP, and EBP can be used as smaller 16-bit registers
called DI, SI, SP, and BP respectively, but these registers do not
have 8-bit versions. Figure 7 shows the EAX register with its
name components, and Table 3 on page 29 lists the doubleword
(32-bit) general-purpose registers and their corresponding word
(16-bit) and byte (8-bit) versions.
31
16 15
8
7
0
EAX
AX
AH
AL
Figure 7. EAX Register with 16-Bit and 8-Bit Name Components
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Software Environment
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 3.
Integer Data Types
General-Purpose Register Doubleword, Word, and Byte Names
32-Bit Name
(Doubleword)
16-Bit Name
(Word)
8-Bit Name
8-Bit Name
(High-order Bits) (Low-order Bits)
EAX
AX
AH
AL
EBX
BX
BH
BL
ECX
CX
CH
CL
EDX
DX
DH
DL
EDI
DI
–
–
ESI
SI
–
–
ESP
SP
–
–
EBP
BP
–
–
Four types of data are used in general-purpose registers—byte,
word, doubleword, and quadword integers. Figure 8 shows the
format of the integer data registers.
Byte Integer
7
0
Precision —
8 Bits
Word Integer
15
0
Precision — 16 Bits
Doubleword Integer
31
0
Precision — 32 Bits
Quadword Integer
63
0
Precision — 64 Bits
Figure 8. Integer Data Registers
Chapter 3
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29
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
Segment Registers
23542A/0—September 2000
The six 16-bit segment registers are used as pointers to areas
(segments) of memory. Table 4 lists the segment registers and
their functions. Figure 9 shows the format for all six segment
registers.
Table 4.
Segment Registers
Segment
Segment Register Function
Register
CS
Code segment, where instructions are located
DS
Data segment, where data is located
ES
Data segment, where data is located
FS
Data segment, where data is located
GS
Data segment, where data is located
SS
Stack segment
15
0
Figure 9. Segment Register
Segment Usage
The operating system determines the type of memory model
that is implemented. The segment register usage is determined
by the operating system’s memory model. In a real mode
memory model, the segment register points to the base address
in memory.
In a protected mode memory model the segment register is
called a selector and it selects a segment descriptor in a
descriptor table. This descriptor contains a pointer to the base
of the segment, the limit of the segment, and various protection
attributes. For more information on descriptor formats, see
“Descriptors and Gates” on page 59. Figure 10 on page 31 shows
segment usage for Real mode and Protected mode memory
models.
30
Software Environment
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Physical Memory
Segment Base
Segment Register
Real Mode Memory Model
Descriptor Table
Physical Memory
Base
Limit
Base
Base
Limit
Segment Base
Segment Selector
Protected Mode Memory Model
Figure 10. Segment Usage
Instruction Pointer
The instruction pointer (EIP or IP) is used in conjunction with
the code segment register (CS). The instruction pointer is
either a 32-bit register (EIP) or a 16-bit register (IP) that keeps
track of where the next instruction resides within memory. This
register cannot be directly manipulated, but can be altered by
modifying return pointers when a JMP or CALL instruction is
used.
Floating-Point
Registers
The floating-point execution unit in the AMD-K6-2E+ processor
is designed to perform mathematical operations on non-integer
numbers. This floating-point unit conforms to the IEEE 754 and
854 standards and uses several registers to meet these
standards — eight numeric floating-point registers, a status
word register, a control word register, and a tag word register.
Chapter 3
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
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The eight floating-point registers are physically 80 bits wide
and labeled FPR0–FPR7. Figure 11 shows the format of the
floating-point registers. See “Floating-Point Register Data
Types” on page 34 for information on allowable floating-point
data types.
79 78
64 63
Sign
0
Exponent
Significand
Figure 11. Floating-Point Register
The 16-bit FPU status word register contains information about
the state of the floating-point unit. Figure 12 shows the format
of the FPU status word register.
15 14 13 12 11 10 9 8
B
Symbol
B
C3
TOSP
C2
C1
C0
ES
SF
PE
UE
OE
ZE
DE
IE
C
3
TOSP
C
2
C C
1 0
7
6
5
4
3
2
1
0
E
S
S
F
P U O Z
E E E E
D
E
I
E
Description
Bits
FPU Busy
15
Condition Code
14
Top of Stack Pointer
13–11
Condition Code
10
Condition Code
9
Condition Code
8
Error Summary Status
7
Stack Fault
6
Exception Flags
Precision Error
5
Underflow Error
4
Overflow Error
3
Zero Divide Error
2
Denormalized Operation Error 1
Invalid Operation Error
0
TOSP Information
000 = FPR0
111 = FPR7
Figure 12. FPU Status Word Register
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AMD-K6™-2E+ Embedded Processor Data Sheet
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The FPU control word register allows a programmer to manage
the FPU processing options. Figure 13 shows the format of the
FPU control word register.
15 14 13 12 11 10 9 8
Y
R
C
7
P
C
6
5
4
3
2
1
0
P U O Z D I
M M M M M M
Reserved
Symbol
Y
RC
PC
PM
UM
OM
ZM
DM
IM
Description
Infinity Bit (80287 compatibility)
Rounding Control
Precision Control
Exception Masks
Precision
Underflow
Overflow
Zero Divide
Denormalized Operation
Invalid Operation
Bits
12
11–10
9–8
5
4
3
2
1
0
Rounding Control Information
00b = Round to the nearest or even number
01b = Round down toward negative infinity
10b = Round up toward positive infinity
11b = Truncate toward zero
Precision Control Information
00b = 24 bits Single Precision Real
01b = Reserved
10b = 53 bits Double Precision Real
11b = 64 bits Extended Precision Real
Figure 13. FPU Control Word Register
The FPU tag word register contains information about the
registers in the register stack. Figure 14 shows the format of the
FPU tag word register.
15
14 13
TAG
(FPR7)
12 11
TAG
(FPR6)
10 9
TAG
(FPR5)
87
TAG
(FPR4)
65
TAG
(FPR3)
43
TAG
(FPR2)
21
TAG
(FPR1)
0
TAG
(FPR0)
Tag Values
00 = Valid
01 = Zero
10 = Special
11 = Empty
Figure 14. FPU Tag Word Register
Chapter 3
Software Environment
33
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
Floating-Point
Register Data Types
79 78
S
23542A/0—September 2000
Floating-point registers use four different types of data —
packed decimal, single-precision real, double-precision real,
and extended-precision real. Figures 15 and 16 show the
formats for these registers.
72 71
0
Ignore
or
Zero
Precision — 18 Digits, 72 Bits Used, 4-Bits/Digit
Description
Bits
Ignored on Load, Zeros on Store 78-72
Sign Bit
79
Figure 15. Packed Decimal Data Register
31 30
Single-Precision Real
S
23 22
0
Biased
Exponent
Significand
S = Sign Bit
Double-Precision Real
52 51
63 62
S
0
Biased
Exponent
Significand
S = Sign Bit
Extended-Precision Real
79 78
S
64 63 62
Biased
Exponent
S = Sign Bit
0
I
Significand
I = Integer Bit
Figure 16. Precision Real Data Registers
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Software Environment
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AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
MMX™/3DNow!™
Registers
Th e A M D -K 6 -2 E + p ro c e s s o r i m p l e m e n t s e i g h t 6 4 -b i t
MMX/3DNow! registers for use by multimedia software. These
registers are mapped on the floating-point register stack. The
MMX and 3DNow! instructions refer to these registers as mm0
to mm7. Figure 17 shows the format of these registers. For more
information, see the AMD-K6® Processor Multimedia Technology
Manual, order# 20726 and the 3DNow! Technology Manual,
order# 21928.
63
0
mm0
mm1
mm2
mm3
mm4
mm5
mm6
mm7
Figure 17. MMX™/3DNow!™ Registers
Chapter 3
Software Environment
35
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
MMX™ Technology
Data Types
23542A/0—September 2000
For the MMX instructions, the MMX registers use three types of
data—packed eight-byte integer, packed quadword integer, and
packed dual doubleword integer. Figure 18 on page 36 shows
the format of these data types.
Packed Bytes Integer
56 55
63
Byte 7
48
47
Byte 6
40
39
Byte 5
32
31
Byte 4
24
23
Byte 3
16
15
Byte 2
8
7
Byte 1
0
Byte 0
Packed Words Integer
63
48 47
Word 3
32
31
Word 2
16
0
15
Word 1
Word 0
Packed Doubleword Integer
63
32
0
31
Doubleword 1
Doubleword 0
Figure 18. MMX™ Technology Data Types
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Software Environment
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
3DNow!™ Technology
Data Types
For 3DNow! instructions, the MMX/3DNow! registers use
packed single-precision real data. Figure 19 shows the format of
the 3DNow! data type.
Packed Single Precision Floating Point
63 62
S
55 54
32 31 30
Biased
Exponent
S
Significand
0
23 22
Biased
Exponent
S = Sign Bit
Significand
S = Sign Bit
Figure 19. 3DNow!™ Technology Data Types
Chapter 3
Software Environment
37
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
EFLAGS Register
23542A/0—September 2000
The EFLAGS register provides for three different types of
flags — system, control, and status. The system flags provide
operating system controls, the control flag provides directional
information for string operations, and the status flags provide
information resulting from logical and arithmetic operations.
Figure 20 shows the format of the EFLAGS register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
V
I I
D P
V
I
F
A V R
C M F
N
T
I
O
P
L
O D
F F
I
F
8
7
6
T
F
S
F
Z
F
5
4
A
F
3
2
P
F
1
0
C
F
Reserved
Symbol
ID
VIP
VIF
AC
VM
RF
NT
IOPL
OF
DF
IF
TF
SF
ZF
AF
PF
CF
Description
Bits
ID Flag
21
Virtual Interrupt Pending
20
Virtual Interrupt Flag
19
Alignment Check
18
Virtual-8086 Mode
17
Resume Flag
16
Nested Task
14
I/O Privilege Level
13–12
Overflow Flag
11
Direction Flag
10
Interrupt Flag
9
Trap Flag
8
Sign Flag
7
Zero Flag
6
Auxiliary Flag
4
Parity Flag
2
Carry Flag
0
Figure 20. EFLAGS Registers
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Software Environment
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Control Registers
The five control registers contain system control bits and
pointers. Figures 21 through 25 show the formats of the control
registers.
31
7
6
5
M
C
E
4
3
2
1
0
P
S
E
T
D S
E D
P V
V M
I E
4
3
1
Reserved
Symbol
MCE
PSE
DE
TSD
PVI
VME
Description
Machine Check Enable
Page Size Extensions
Debugging Extensions
Time Stamp Disable
Protected Virtual Interrupts
Virtual-8086 Mode Extensions
Bit
6
4
3
2
1
0
Figure 21. Control Register 4 (CR4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Page Directory Base
8
7
6
5
2
0
P P
C W
D T
Reserved
Symbol
PCD
PWT
Description
Page Cache Disable
Page Writethrough
Bit
4
3
Figure 22. Control Register 3 (CR3)
31
0
Page Fault Linear Address
Figure 23. Control Register 2 (CR2)
Chapter 3
Software Environment
39
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
31
0
Reserved
Figure 24. Control Register 1 (CR1)
Symbol
PG
CD
NW
Description
Paging
Cache Disable
Not Writethrough
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
P C N
G D W
A
M
W
P
Bit
31
30
29
8
7
6
5
4
3
2
1
0
N
E
E T E M P
T S M P E
Reserved
Symbol
AM
WP
NE
ET
TS
EM
MP
PE
Description
Alignment Mask
Write Protect
Numeric Error
Extension Type
Task Switched
Emulation
Monitor Coprocessor
Protection Enabled
Bit
18
16
5
4
3
2
1
0
Figure 25. Control Register 0 (CR0)
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Software Environment
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Debug Registers
Figures 26 through 29 show the 32-bit debug registers
supported by the processor. These registers are further
described in “Debug” on page 268.
Symbol
LEN 3
R/W 3
LEN 2
R/W 2
LEN 1
R/W 1
LEN 0
R/W 0
Description
Length of Breakpoint #3
Type of Transaction(s) to Trap
Length of Breakpoint #2
Type of Transaction(s) to Trap
Length of Breakpoint #1
Type of Transaction(s) to Trap
Length of Breakpoint #0
Type of Transaction(s) to Trap
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
LEN
3
R/W
3
LEN
2
R/W
2
LEN
1
R/W
1
LEN
0
R/W
0
G
D
G
E
8
7
6
Bits
31–30
29–28
27–26
25–24
23–22
21–20
19–18
17–16
5
L G L G
E 3 3 2
4
3
L G
2 1
2
1
0
L G
1 0
L
0
Reserved
Symbol
GD
GE
LE
G3
L3
G2
L2
G1
L1
G0
L0
Description
General Detect Enabled
Global Exact Breakpoint Enabled
Local Exact Breakpoint Enabled
Global Exact Breakpoint # 3 Enabled
Local Exact Breakpoint # 3 Enabled
Global Exact Breakpoint # 2 Enabled
Local Exact Breakpoint # 2 Enabled
Global Exact Breakpoint # 1 Enabled
Local Exact Breakpoint # 1 Enabled
Global Exact Breakpoint # 0 Enabled
Local Exact Breakpoint # 0 Enabled
Bit
13
9
8
7
6
5
4
3
2
1
0
Figure 26. Debug Register DR7
Chapter 3
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41
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
B B B
T S D
3
2
1
0
B
3
B
2
B
1
B
0
Reserved
Symbol
BT
BS
BD
B3
B2
B1
B0
Description
Breakpoint Task Switch
Breakpoint Single Step
Breakpoint Debug Access Detected
Breakpoint #3 Condition Detected
Breakpoint #2 Condition Detected
Breakpoint #1 Condition Detected
Breakpoint #0 Condition Detected
Bit
15
14
13
3
2
1
0
Figure 27. Debug Register DR6
DR5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Reserved
DR4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved
Figure 28. Debug Registers DR5 and DR4
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AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
DR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
5
4
3
2
1
0
8
7
5
4
3
2
1
0
Breakpoint 3 32-bit Linear Address
DR2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Breakpoint 2 32-bit Linear Address
DR1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
6
Breakpoint 1 32-bit Linear Address
DR0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
6
Breakpoint 0 32-bit Linear Address
Figure 29. Debug Registers DR3, DR2, DR1, and DR0
Chapter 3
Software Environment
43
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
3.2
23542A/0—September 2000
Model-Specific Registers (MSR)
The AMD-K6-2E+ processor provides eleven Model-Specific
Registers (MSRs) in the standard-power versions and twelve
MSRs in the low-power versions.
■
■
The value in the ECX register selects the MSR to be
addressed by the RDMSR and WRMSR instructions.
The values in EAX and EDX are used as inputs and outputs
by the RDMSR and WRMSR instructions.
Table 5 lists the MSRs and the corresponding value of the ECX
register. Figures 30 through 43 starting on page 45 show the
MSR formats.
Table 5.
AMD-K6™-2E+ Processor Model-Specific Registers
Model-Specific Register
Value of ECX
Machine Check Address Register (MCAR)
00h
Machine Check Type Register (MCTR)
01h
Test Register 12 (TR12)
0Eh
Time Stamp Counter (TSC)
10h
Extended Feature Enable Register (EFER)
C000_0080h
SYSCALL/SYSRET Target Address Register (STAR)
C000_0081h
Write Handling Control Register (WHCR)
C000_0082h
UC/WC Cacheability Control Register (UWCCR)
C000_0085h
Processor State Observability Register (PSOR)
C000_0087h
Page Flush/Invalidate Register (PFIR)
C000_0088h
Level-2 Cache Array Register (L2AAR)
C000_0089h
Enhanced Power Management Register (EPMR)1
C000_0086h
Notes:
1. The EPMR register is supported in the low-power versions only of the AMD-K6-2E+ processor.
For more information about the MSRs, see the Embedded
AMD-K6™ Processors BIOS Design Guide Application Note, order#
23913.
For mo re info rma tio n abo ut the RD MSR and WRMSR
instructions, see the AMD K86™ Family BIOS and Software Tools
Development Guide, order# 21062.
44
Software Environment
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Machine Check
Address Register
(MCAR) and Machine
Check Type Register
(MCTR)
The AMD-K6-2E+ processor does not support the generation of
a machine check exception. However, the processor does
provide a 64-bit machine check address register (MCAR), a
64-bit machine check type register (MCTR), and a machine
check enable (MCE) bit in CR4.
Because the processor does not support machine check
exceptions, the contents of the MCAR and MCTR are only
affected by the WRMSR instruction and by RESET being
sampled asserted (where all bits in each register are reset to 0).
The formats for the machine-check address register and the
machine-check type register are shown in Figure 30 and Figure
31, respectively. The MCAR register is MSR 00h, and the MCTR
register is MSR 01h.
63
0
MCAR
Figure 30. Machine-Check Address Register (MCAR)
63
5
4
0
MCTR
Reserved
Figure 31. Machine-Check Type Register (MCTR)
Chapter 3
Software Environment
45
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
Test Register 12
(TR12)
23542A/0—September 2000
Test register 12 provides a method for disabling the L1 caches.
Figure 32 shows the format of TR12. The TR12 register is MSR
0Eh.
63
4 3
2
1
0
C
I
Reserved
Symbol Description
CI
Cache Inhibit Bit
Bit
3
Figure 32. Test Register 12 (TR12)
Time Stamp Counter
With each processor clock cycle, the processor increments the
64-bit time stamp counter (TSC) MSR. Figure 33 shows the
format of the TSC. The TSC register is MSR 10h.
The counter can be written or read using the WRMSR or
RDMSR instructions when the ECX register contains the value
10h and CPL = 0. The counter can also be read using the RDTSC
instruction, but the procedure must be executing at privilege
level 0 for the RDTSC instruction to execute. This condition is
reflected by the status of the Time Stamp Disable (TSD) bit in
CR4.
With either of these instructions, the EDX and EAX registers
hold the upper and lower dwords of the 64-bit value to be
written to or read from the TSC, as follows:
■
EDX—Upper 32 bits of TSC
■
EAX—Lower 32 bits of TSC
The TSC can be loaded with any arbitrary value. This feature is
compatible with the Pentium processor.
63
0
TSC
Figure 33. Time Stamp Counter (TSC)
46
Software Environment
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Extended Feature
Enable Register
(EFER)
The Extended Feature Enable Register (EFER) contains the
control bits that enable the extended features of the processor.
Figure 34 shows the format of the EFER register, and Table 6
defines the function of each bit of the EFER register. The EFER
register is MSR C000_0080h.
63
5 4
L
2
D
Symbol
L2D
EWBEC
DPE
SCE
Reserved
Description
L2 Cache Disable
EWBE# Control
Data Prefetch Enable
System Call Extension
3
2 1
0
D S
EWBEC P C
E E
Bit
4
3-2
1
0
Figure 34. Extended Feature Enable Register (EFER)
Table 6.
Bit
Extended Feature Enable Register (EFER) Definition
Description
R/W Function
R
Writing a 1 to any reserved bit causes a general protection fault to occur. All reserved bits
are always read as 0.
L2D
R/W
If L2D is set to 1, the L2 cache is completely disabled. This bit is provided for debug and
testing purposes. For normal operation and maximum performance, this bit must be set
to 0 (this is the default setting following reset).
3-2
EWBE Control
(EWBEC)
R/W
This 2-bit field controls the behavior of the processor with respect to the ordering of write
cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE Disable (GEWBED)
and Speculative EWBE Disable (SEWBED), respectively.
1
Data Prefetch
Enable (DPE)
R/W
DPE must be set to 1 to enable data prefetching (this is the default setting following
reset). If enabled, cache misses initiated by a memory read within a 32-byte line are
conditionally followed by cache-line fetches of the other line in the 64-byte sector.
0
System Call
Extension (SCE)
R/W
SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions.
63–5
4
Reserved
For more information about the EWBEC bits, see “EWBE#
Control” on page 229.
Chapter 3
Software Environment
47
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
SYSCALL/SYSRET
Target Address
Register (STAR)
63
23542A/0—September 2000
The SYSCALL/SYSRET target address register (STAR)
contains the target EIP address used by the SYSCALL
instruction and the 16-bit code and stack segment selector
bases used by the SYSCALL and SYSRET instructions. Figure
35 shows the format of the STAR register, and Table 7 defines
the function of each bit of the STAR register. For more
information, see the SYSCALL and SYSRET Instruction
Specification Application Note, order# 21086. The STAR register
is MSR C000_0081h.
32 31
48 47
SYSRET CS Selector and SS
Selector Base
0
SYSCALL CS Selector and SS
Selector Base
Target EIP Address
Figure 35. SYSCALL/SYSRET Target Address Register (STAR)
Table 7.
Bit
Write Handling
Control Register
(WHCR)
SYSCALL/SYSRET Target Address Register (STAR) Definition
Description
R/W
63–48
SYSRET CS and SS Selector Base
R/W
47–32
SYSCALL CS and SS Selector Base
R/W
31–0
Target EIP Address
R/W
The Write Handling Control Register (WHCR) is a MSR that
contains two fields —the Write Allocate Enable Limit
(WAELIM) field, and the Write Allocate Enable 15-to-16-Mbyte
(WAE15M) bit (see Figure 36). For more information, see
“Write Allocate” on page 215. The WHCR register is MSR
C000_0082h.
63
32 31
22 21
WAELIM
17 16 15
0
W
A
E
1
5
M
Reserved
Symbol
WAELIM
WAE15M
Description
Bits
Write Allocate Enable Limit
31-22
Write Allocate Enable 15-to-16-Mbyte 16
Note: Hardware RESET initializes this MSR to all zeros.
Figure 36. Write Handling Control Register (WHCR)
48
Software Environment
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Preliminary Information
23542A/0—September 2000
AMD-K6™-2E+ Embedded Processor Data Sheet
UC/WC Cacheability
Control Register
(UWCCR)
The AMD-K6-2E+ processor provides two variable-range
Memory Type Range Registers (MTRRs)—MTRR0 and
MTRR1—that each specify a range of memory. Each range can
be defined as uncacheable (UC) or write-combining (WC)
memory. For more information, see “Memory Type Range
Re gist ers” o n pag e 231 . The UWCCR reg ist er is M SR
C000_0085h.
.
Symbol
UC1
WC1
Description
Uncacheable Memory Type
Write-Combining Memory Type
49
63
Physical Base Address 1
Bits
32
33
48
Symbol
UC0
WC0
Description
Uncacheable Memory Type
Write-Combining Memory Type
34 33 32 31
W U
Physical Address Mask 1 C C
1 1
17 16
Physical Base Address 0
MTRR1
Bits
0
1
2
1
0
W
Physical Address Mask 0 C
0
U
C
0
MTRR0
Figure 37. UC/WC Cacheability Control Register (UWCCR)
Processor State
Observability
Register (PSOR)
The AMD-K6-2E+ processor provides the Processor State
Observability Register (PSOR). The PSOR is defined as shown
in Figure 38 for all standard-power versions of the AMD-K6-2E+
processor. For a description of the PSOR register supported by
the low-power versions of the processor, see page 148.
The PSOR register is MSR C000_0087h.
.
63
9
8
N
O
L
2
4 3 2
7
STEP
0
BF
Reserved
Symbol
NOL2
STEP
BF
Description
No L2 Functionality
Processor Stepping
Bus Frequency Divisor
Bit
8
7-4
2-0
Figure 38. Processor State Observability Register (PSOR)
Chapter 3
Software Environment
49
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
Page Flush/Invalidate
Register (PFIR)
23542A/0—September 2000
The AMD-K6-2E+ processor contains the Page Flush/Invalidate
Register (PFIR) (see Figure 39) that allows cache invalidation
and optional flushing of a specific 4-Kbyte page from the linear
address space. For more detailed information on PFIR, see
“Page Flush/Invalidate Register (PFIR)” on page 223. The
PFIR register is MSR C000_0088h.
32 31
63
12 11
LINPAGE
9 8 7
P
F
1 0
F
/
I
Reserved
Symbol
LINPAGE
PF
F/I
Description
20-bit Linear Page Address
Page Fault Occurred
Flush/Invalidate Command
Bit
31-12
8
0
Figure 39. Page Flush/Invalidate Register (PFIR)
Level-2 Cache Array
Access Register
(L2AAR)
The AMD-K6-2E+ processor provides the L2AAR register that
allows for direct access to the L2 cache and L2 tag arrays. The
L2AAR register is MSR C000_0089h.
The operation that is performed on the L2 cache is a function of
the instruction executed — RDMSR or WRMSR — and the
contents of the EDX register. The EDX register specifies the
location of the access, and whether the access is to the L2 cache
data or tags (refer to Figure 40).
50
Software Environment
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AMD-K6™-2E+ Embedded Processor Data Sheet
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Symbol
T/D
Way
31
Description
Selects Tag (1) or Data (0) access
Selects desired cache way
21 20 19 18 17 16 15 14
T
/
D
Way
Set
Bit
20
17-16
6 5 4
3 2 1
L
i
n
e
D
w
o
r
d
Octet
0
Reserved
Symbol
Set
Line
Octet
Dword
Description
Selects the desired cache set
Selects Line1 (1) or Line0 (0)
Selects one of four octets
Selects upper (1) or lower (0) dword
Bit
14-6
5
4-3
2
Figure 40. L2 Tag or Data Location for AMD-K6™-2E+ Processor—EDX
If the L2 cache data is read (as opposed to reading the tag
information), the result (doubleword) is placed in EAX in the
format as illustrated in Figure 41. Similarly, if the L2 cache data
is written, the write data is taken from EAX.
31
0
Data
Figure 41. L2 Data —EAX
If the L2 tag is read (as opposed to reading the cache data), the
result is placed in EAX in the format as illustrated in Figure 42
on page 52. Similarly, if the L2 tag is written, the write data is
taken from EAX.
Chapter 3
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AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
14 13 12 11 10 9
31
Line1ST Line0ST
Tag
0
8 7
LRU
C
M
D
Reserved
Symbol
Tag
Line1ST
Line0ST
LRU
Description
Tag data read or written
Line 1 state (M=11, E=10, S=01, I=00)
Line 0 state (M=11, E=10, S=01, I=00)
Two bits of LRU for each way
Bit
31-14
11-10
9-8
7-0
Figure 42. L2 Tag Information for AMD-K6™-2E+ Processor—EAX
For more detailed information, refer to “L2 Cache and Tag
Array Testing” on page 264.
Enhanced Power
Management Register
(EPMR)
The AMD-K6-2E+ processor is designed with enhanced power
management features, called AMD PowerNow! technology,
which include dynamic bus divisor control and dynamic core
voltage control. The EPMR register (see Figure 43) defines the
base address for a 16-byte block of I/O address space. Enabling
the EPMR allows software to access the EPM 16-byte I/O block,
which contains bits for enabling, controlling, and monitoring
the AMD PowerNow! technology features. The EPMR is MSR
C000_0086h.
See “AMD PowerNow!™ Technology” on page 143 for more
information about the definition and use of this register.
Additional information can be found in the Embedded
AMD-K6™ Processors BIOS Design Guide Application Note, order#
23913.
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AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
63
4 3 2 1 0
16 15
IOBASE
G
S CE
B MN
C D
Reserved
Symbol
IOBASE
GSBC
EN
Description
I/O Base Address
Generate Special Bus Cycle
Enable AMD PowerNow! Technology
Management
Bit
15-4
1
0
Figure 43. Enhanced Power Management Register (EPMR)
Chapter 3
Software Environment
53
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
3.3
23542A/0—September 2000
Memory Management Registers
The AMD-K6-2E+ processor controls segmented memory
management with the registers listed in Table 8. Figure 44
shows the formats of these registers.
Table 8.
Memory Management Registers
Register Name
Function
Global Descriptor Table Register
Contains a pointer to the base of the global descriptor table
Interrupt Descriptor Table Register
Contains a pointer to the base of the interrupt descriptor table
Local Descriptor Table Register
Contains a pointer to the local descriptor table of the current task
Task Register
Contains a pointer to the task state segment of the current task
Global and Interrupt Descriptor Table Registers
16 15
47
32-Bit Linear Base Address
Local Descriptor Table Register and Task Register
0
16-Bit Limit
15
0
Selector
63
0
32 31
32-Bit Linear Base Address
32-Bit Limit
15
0
Attributes
Figure 44. Memory Management Registers
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Task State Segment
Figure 45 shows the format of the task state segment (TSS).
31
0
TSS Limit
from TR
I/O Permission Bitmap (IOPB)
(up to 8 Kbytes)
Interrupt Redirection Bitmap (IRB)
(eight 32-bit locations)
Operating System
Data Structure
Base Address of IOPB
0000h
0000h
LDT Selector
0000h
GS
T
64h
FS
0000h
0000h
0000h
DS
SS
0000h
CS
ES
0000h
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
EFLAGS
EIP
CR3
SS2
0000h
ESP2
0000h
SS1
ESP1
0000h
SS0
ESP0
0000h
Link (Prior TSS Selector)
0
Figure 45. Task State Segment (TSS)
Chapter 3
Software Environment
55
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
3.4
23542A/0—September 2000
Paging
The AMD-K6-2E+ processor can physically address up to four
Gbytes of memory. This memory can be segmented into pages.
The size of these pages is determined by the operating system
design and the values set up in the page directory entries (PDE)
and page table entries (PTE).
The processor can access both 4-Kbyte pages and 4-Mbyte
pages, and the page sizes can be intermixed within a page
directory. When the page size extension (PSE) bit in CR4 is set,
the processor translates linear addresses using either the
4-Kbyte translation lookaside buffer (TLB) or the 4-Mbyte TLB,
depending on the state of the page size (PS) bit in the page
directory entry. Figures 46 and Figure 47 on page 57 show how
4-Kbyte and 4-Mbyte page translations work.
Page
Directory
4-Kbyte
Page
Frame
Page
Table
PTE
Physical
Address
PDE
CR3
31
22 21
Page Directory
Offset
12 11
Page Table
Offset
0
Page
Offset
Linear Address
Figure 46. 4-Kbyte Paging Mechanism
56
Software Environment
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
4-Mbyte
Page
Frame
Page
Directory
Physical
Address
PDE
CR3
31
22 21
0
Page Directory
Offset
Page
Offset
Linear Address
Figure 47. 4-Mbyte Paging Mechanism
Figures 48 through 50 starting on page 58 show the formats of
the PDE and PTE. These entries contain information regarding
the location of pages and their status.
Chapter 3
Software Environment
57
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
31
23542A/0—September 2000
12 11 10 9 8
7
A
V
L
0
12 11 10 9 8
7
A
V
L
1
Page Table Base Address
Symbol
AVL
PS
A
PCD
PWT
U/S
W/R
P
Description
Available to Software
Reserved
Page Size
Reserved
Accessed
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
Present (valid)
6
5
4
3
2
1
0
A
P P U W
C W / / P
D T S R
5
4
A
P P U W
C W / / P
D T S R
Bits
11–9
8
7
6
5
4
3
2
1
0
Figure 48. Page Directory Entry 4-Kbyte Page Table (PDE)
31
22 21
Physical Page Base Address
Symbol
AVL
PS
A
PCD
PWT
U/S
W/R
P
Description
Available to Software
Reserved
Page Size
Reserved
Accessed
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
Present (valid)
Reserved
6
3
2
1
0
Bits
11–9
8
7
6
5
4
3
2
1
0
Figure 49. Page Directory Entry 4-Mbyte Page Table (PDE)
58
Software Environment
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
31
12 11 10 9 8
A
V
L
Physical Page Base Address
Symbol
AVL
D
A
PCD
PWT
U/S
W/R
P
Description
Available to Software
Reserved
Dirty
Accessed
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
Present (valid)
7
6
5
D A
4
3
2
1
0
P P U W
C W / / P
D T S R
Bits
11–9
8–7
6
5
4
3
2
1
0
Figure 50. Page Table Entry (PTE)
3.5
Descriptors and Gates
There are various types of structures and registers in the x86
architecture that define, protect, and isolate code segments,
data segments, task state segments, and gates. These structures
are called descriptors.
■
■
■
Chapter 3
The application segment descriptor is used to point to either a
data or code segment. Figure 51 on page 60 shows the
application segment descriptor format. Table 9 on page 60
contains information describing the memory segment type
to which the descriptor points.
The system segment descriptor is used to point to a task state
segment, a call gate, or a local descriptor table. Figure 52 on
page 61 shows the system segment descriptor format.
Table 10 on page 61 contains information describing the
type of segment or gate to which the descriptor points.
The AMD-K6-2E+ processor uses gates to transfer control
between executable segments with different privilege
levels. Figure 53 on page 62 shows the format of the gate
descriptor types. Table 10 on page 61 contains information
describing the type of segment or gate to which the
descriptor points.
Software Environment
59
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Symbol
G
D
AVL
P
DPL
DT
Type
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Base Address 31–24
G D
A
V
L
Segment
Limit
P
DPL
1
Base Address 15–0
8
7
Description
Granularity
32-Bit/16-Bit
Available to Software
Present/Valid Bit
Descriptor Privilege Level
Descriptor Type
See Table 9
6
Type
5
4
3
2
1
Bits
23
22
20
15
14-13
12
11-8
0
Base Address 23–16
Segment Limit 15–0
Figure 51. Application Segment Descriptor
Table 9.
Application Segment Types
Type Data/Code Description
0
Read-Only
1
Read-Only—Accessed
2
Read/Write
3
4
Read/Write—Accessed
Read-Only—Expand-down
5
Read-Only—Expand-down, Accessed
6
Read/Write—Expand-down
7
Read/Write—Expand-down, Accessed
8
Execute-Only
9
Execute-Only—Accessed
A
Execute/Read
B
C
60
Data
Code
Execute/Read—Accessed
Execute-Only—Conforming
D
Execute-Only—Conforming, Accessed
E
Execute/Read-Only—Conforming
F
Execute/Read-Only—Conforming, Accessed
Software Environment
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Symbol
G
X
AVL
P
DPL
DT
Type
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Base Address 31–24
A
V
L
G X
Segment
Limit
P
DPL
0
Base Address 15–0
8
7
Description
Granularity
Not Needed
Availability to Software
Present/Valid Bit
Descriptor Privilege Level
Descriptor Type
See Table 10
6
Type
5
4
3
2
1
Bits
23
22
20
15
14-13
12
11-8
0
Base Address 23–16
Segment Limit 15–0
Figure 52. System Segment Descriptor
Table 10. System Segment and Gate Types
Type Description
Chapter 3
0
Reserved
1
Available 16-bit TSS
2
LDT
3
Busy 16-bit TSS
4
16-bit Call Gate
5
Task Gate
6
16-bit Interrupt Gate
7
16-bit Trap Gate
8
Reserved
9
Available 32-bit TSS
A
Reserved
B
Busy 32-bit TSS
C
32-bit Call Gate
D
Reserved
E
32-bit Interrupt Gate
F
32-bit Trap Gate
Software Environment
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Symbol
P
DPL
DT
Type
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Offset 31–16
P
DPL
0
Segment Selector
8
7
6
5
Description
Present/Valid Bit
Descriptor Privilege Level
Descriptor Type
See Table 10 on page 61
4
3
2
1
Bits
15
14-13
12
11-8
0
Type
Offset 15–0
Figure 53. Gate Descriptor
3.6
Exceptions and Interrupts
Table 11 summarizes the exceptions and interrupts.
Table 11. Summary of Exceptions and Interrupts
Interrupt
Interrupt Type
Number
62
Cause
0
Divide by Zero Error
DIV, IDIV
1
Debug
Debug trap or fault
2
Non-Maskable Interrupt
NMI signal sampled asserted
3
Breakpoint
Int 3
4
Overflow
INTO
5
Bounds Check
BOUND
6
Invalid Opcode
Invalid instruction
7
Device Not Available
ESC and WAIT
8
Double Fault
Fault occurs while handling a fault
9
Reserved - Interrupt 13
—
10
Invalid TSS
Task switch to an invalid segment
11
Segment Not Present
Instruction loads a segment and present bit is 0 (invalid segment)
12
Stack Segment
Stack operation causes limit violation or present bit is 0
13
General Protection
Segment related or miscellaneous invalid actions
14
Page Fault
Page protection violation or a reference to missing page
16
Floating-Point Error
Arithmetic error generated by floating-point instruction
17
Alignment Check
Data reference to an unaligned operand. (The AC flag and the AM bit of CR0 are set to 1.)
0–255
Software Interrupt
INT n
Software Environment
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
3.7
Instructions Supported by the AMD-K6™-2E+ Processor
This section documents all of the x86 instructions supported by
the AMD-K6-2E+ processor. Tables 12 through 16 starting on
page 65 define the integer, floating-point, MMX, 3DNow!
technology instructions, and 3DNow! technology digital signal
processing (DSP) extensions for the AMD-K6-2E+ processor,
respectively. For details about the MMX instructions, 3DNow!
technology instructions, and 3DNow! technology DSP
extensions refer to the following manuals:
■
■
■
MMX
Instructions—AMD-K6®
Processor
Multimedia
Technology Manual, order# 20726
3DNow! Technology Instructions—3DNow! Technology
Manual, order# 21928
3DNow! Technology DSP Extensions—AMD Extensions to the
3DNow! and MMX Instruction Set Manual, order# 22466
Each table shows the instruction mnemonic, opcode, modR/M
by t e , d e c o d e t y p e, a n d R I S C 8 6 o p e ra t i o n ( s ) fo r e a ch
instruction.
Instruction
Mnemonic and
Operand Types
The first column in these tables indicates the instruction
mnemonic and operand types with the following notations:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Chapter 3
disp16/32—16-bit or 32-bit displacement value
disp32/48—doubleword or 48-bit displacement value
disp8—8-bit displacement value
eXX—register width depending on the operand size
imm16/32—16-bit or 32-bit immediate value
imm8—8-bit immediate value
mem16/32—word or doubleword integer value in memory
mem32/48—doubleword or 48-bit integer value in memory
mem32real—32-bit floating-point value in memory
mem48—48-bit integer value in memory
mem64—64-bit integer value in memory
mem64real—64-bit floating-point value in memory
mem8—byte integer value in memory
mem80real—80-bit floating-point value in memory
mmreg—MMX/3DNow! register
Software Environment
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AMD-K6™-2E+ Embedded Processor Data Sheet
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■
mmreg1—MMX/3DNow! register defined by bits 5, 4, and 3
of the modR/M byte
■
mmreg2—MMX/3DNow! register defined by bits 2, 1, and 0
of the modR/M byte
mreg16/32—word or doubleword integer register, or word or
doubleword integer value in memory defined by the
modR/M byte
mreg8—byte integer register or byte integer value in
memory defined by the modR/M byte
reg8—byte integer register defined by instruction byte(s) or
bits 5, 4, and 3 of the modR/M byte
reg16/32—word or doubleword integer register defined by
instruction byte(s) or bits 5, 4, and 3 of the modR/M byte
■
■
■
■
Opcode Bytes
The second and third columns list all applicable opcode bytes.
ModR/M Byte
The fourth column lists the modR/M byte when used by the
instruction. The modR/M byte defines the instruction as a
re g i st e r o r m e m o ry fo r m . I f m o d R / M b i t s 7 a n d 6 a re
documented as mm (memory form), mm can only be 10b, 01b or
00b.
Decode Type
The fifth column lists the type of instruction decode — short,
long, and vector. The AMD-K6-2E+ processor decode logic can
process two short, one long, or one vector decode per clock.
RISC86® Operation
The sixth column lists the type of RISC86 operation(s) required
for the instruction. The operation types and corresponding
execution units are as follows:
■
■
■
■
■
■
■
■
64
alu—either of the integer execution units
alux—integer X execution unit only
branch—branch condition unit
float—floating-point execution unit
limm—load immediate, instruction control unit
load, fload, mload—load unit
meu—multimedia execution units for MMX and 3DNow!
instructions
store, fstore, mstore—store unit
Software Environment
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions
Instruction Mnemonic
First
Byte
AAA
37h
AAD
D5h
0Ah
vector
AAM
D4h
0Ah
vector
AAS
3Fh
ADC mreg8, reg8
10h
11-xxx-xxx
vector
ADC mem8, reg8
10h
mm-xxx-xxx
vector
ADC mreg16/32, reg16/32
11h
11-xxx-xxx
vector
ADC mem16/32, reg16/32
11h
mm-xxx-xxx
vector
ADC reg8, mreg8
12h
11-xxx-xxx
vector
ADC reg8, mem8
12h
mm-xxx-xxx
vector
ADC reg16/32, mreg16/32
13h
11-xxx-xxx
vector
ADC reg16/32, mem16/32
13h
mm-xxx-xxx
vector
ADC AL, imm8
14h
vector
ADC EAX, imm16/32
15h
vector
ADC mreg8, imm8
80h
11-010-xxx
vector
ADC mem8, imm8
80h
mm-010-xxx
vector
ADC mreg16/32, imm16/32
81h
11-010-xxx
vector
ADC mem16/32, imm16/32
81h
mm-010-xxx
vector
ADC mreg16/32, imm8 (signed ext.)
83h
11-010-xxx
vector
ADC mem16/32, imm8 (signed ext.)
83h
mm-010-xxx
vector
ADD mreg8, reg8
00h
11-xxx-xxx
short
alux
ADD mem8, reg8
00h
mm-xxx-xxx
long
load, alux, store
ADD mreg16/32, reg16/32
01h
11-xxx-xxx
short
alu
ADD mem16/32, reg16/32
01h
mm-xxx-xxx
long
load, alu, store
ADD reg8, mreg8
02h
11-xxx-xxx
short
alux
ADD reg8, mem8
02h
mm-xxx-xxx
short
load, alux
ADD reg16/32, mreg16/32
03h
11-xxx-xxx
short
alu
ADD reg16/32, mem16/32
03h
mm-xxx-xxx
short
load, alu
ADD AL, imm8
04h
short
alux
ADD EAX, imm16/32
05h
short
alu
ADD mreg8, imm8
80h
11-000-xxx
short
alux
ADD mem8, imm8
80h
mm-000-xxx
long
load, alux, store
ADD mreg16/32, imm16/32
81h
11-000-xxx
short
alu
ADD mem16/32, imm16/32
81h
mm-000-xxx
long
load, alu, store
ADD mreg16/32, imm8 (signed ext.)
83h
11-000-xxx
short
alux
Chapter 3
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
vector
vector
Software Environment
65
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
ADD mem16/32, imm8 (signed ext.)
ModR/M
Byte
Decode
Type
83h
mm-000-xxx
long
load, alux, store
AND mreg8, reg8
20h
11-xxx-xxx
short
alux
AND mem8, reg8
20h
mm-xxx-xxx
long
load, alux, store
AND mreg16/32, reg16/32
21h
11-xxx-xxx
short
alu
AND mem16/32, reg16/32
21h
mm-xxx-xxx
long
load, alu, store
AND reg8, mreg8
22h
11-xxx-xxx
short
alux
AND reg8, mem8
22h
mm-xxx-xxx
short
load, alux
AND reg16/32, mreg16/32
23h
11-xxx-xxx
short
alu
AND reg16/32, mem16/32
23h
mm-xxx-xxx
short
load, alu
AND AL, imm8
24h
short
alux
AND EAX, imm16/32
25h
short
alu
AND mreg8, imm8
80h
11-100-xxx
short
alux
AND mem8, imm8
80h
mm-100-xxx
long
load, alux, store
AND mreg16/32, imm16/32
81h
11-100-xxx
short
alu
AND mem16/32, imm16/32
81h
mm-100-xxx
long
load, alu, store
AND mreg16/32, imm8 (signed ext.)
83h
11-100-xxx
short
alux
AND mem16/32, imm8 (signed ext.)
83h
mm-100-xxx
long
load, alux, store
ARPL mreg16, reg16
63h
11-xxx-xxx
vector
ARPL mem16, reg16
63h
mm-xxx-xxx
vector
BOUND
62h
BSF reg16/32, mreg16/32
0Fh
BCh
11-xxx-xxx
vector
BSF reg16/32, mem16/32
0Fh
BCh
mm-xxx-xxx
vector
BSR reg16/32, mreg16/32
0Fh
BDh
11-xxx-xxx
vector
BSR reg16/32, mem16/32
0Fh
BDh
mm-xxx-xxx
vector
BSWAP EAX
0Fh
C8h
long
alu
BSWAP ECX
0Fh
C9h
long
alu
BSWAP EDX
0Fh
CAh
long
alu
BSWAP EBX
0Fh
CBh
long
alu
BSWAP ESP
0Fh
CCh
long
alu
BSWAP EBP
0Fh
CDh
long
alu
BSWAP ESI
0Fh
CEh
long
alu
BSWAP EDI
0Fh
CFh
long
alu
BT mreg16/32, reg16/32
0Fh
A3h
11-xxx-xxx
vector
BT mem16/32, reg16/32
0Fh
A3h
mm-xxx-xxx
vector
BT mreg16/32, imm8
0Fh
BAh
11-100-xxx
vector
66
Second
Byte
RISC86
Operations
vector
Software Environment
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type
BT mem16/32, imm8
0Fh
BAh
mm-100-xxx
vector
BTC mreg16/32, reg16/32
0Fh
BBh
11-xxx-xxx
vector
BTC mem16/32, reg16/32
0Fh
BBh
mm-xxx-xxx
vector
BTC mreg16/32, imm8
0Fh
BAh
11-111-xxx
vector
BTC mem16/32, imm8
0Fh
BAh
mm-111-xxx
vector
BTR mreg16/32, reg16/32
0Fh
B3h
11-xxx-xxx
vector
BTR mem16/32, reg16/32
0Fh
B3h
mm-xxx-xxx
vector
BTR mreg16/32, imm8
0Fh
BAh
11-110-xxx
vector
BTR mem16/32, imm8
0Fh
BAh
mm-110-xxx
vector
BTS mreg16/32, reg16/32
0Fh
ABh
11-xxx-xxx
vector
BTS mem16/32, reg16/32
0Fh
ABh
mm-xxx-xxx
vector
BTS mreg16/32, imm8
0Fh
BAh
11-101-xxx
vector
BTS mem16/32, imm8
0Fh
BAh
mm-101-xxx
vector
CALL full pointer
9Ah
vector
CALL near imm16/32
E8h
short
CALL mem16:16/32
FFh
11-011-xxx
vector
CALL near mreg32 (indirect)
FFh
11-010-xxx
vector
CALL near mem32 (indirect)
FFh
mm-010-xxx
vector
CBW/CWDE EAX
98h
vector
CLC
F8h
vector
CLD
FCh
vector
CLI
FAh
vector
CLTS
0Fh
CMC
F5h
CMP mreg8, reg8
38h
11-xxx-xxx
short
alux
CMP mem8, reg8
38h
mm-xxx-xxx
short
load, alux
CMP mreg16/32, reg16/32
39h
11-xxx-xxx
short
alu
CMP mem16/32, reg16/32
39h
mm-xxx-xxx
short
load, alu
CMP reg8, mreg8
3Ah
11-xxx-xxx
short
alux
CMP reg8, mem8
3Ah
mm-xxx-xxx
short
load, alux
CMP reg16/32, mreg16/32
3Bh
11-xxx-xxx
short
alu
CMP reg16/32, mem16/32
3Bh
mm-xxx-xxx
short
load, alu
CMP AL, imm8
3Ch
short
alux
CMP EAX, imm16/32
3Dh
short
alu
CMP mreg8, imm8
80h
short
alux
Instruction Mnemonic
Chapter 3
06h
RISC86
Operations
store
vector
vector
11-111-xxx
Software Environment
67
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
CMP mem8, imm8
ModR/M
Byte
Decode
Type
80h
mm-111-xxx
short
load, alux
CMP mreg16/32, imm16/32
81h
11-111-xxx
short
alu
CMP mem16/32, imm16/32
81h
mm-111-xxx
short
load, alu
CMP mreg16/32, imm8 (signed ext.)
83h
11-111-xxx
long
load, alu
CMP mem16/32, imm8 (signed ext.)
83h
mm-111-xxx
long
load, alu
CMPSB mem8, mem8
A6h
vector
CMPSW mem16, mem32
A7h
vector
CMPSD mem32, mem32
A7h
vector
CMPXCHG mreg8, reg8
0Fh
B0h
11-xxx-xxx
vector
CMPXCHG mem8, reg8
0Fh
B0h
mm-xxx-xxx
vector
CMPXCHG mreg16/32, reg16/32
0Fh
B1h
11-xxx-xxx
vector
CMPXCHG mem16/32, reg16/32
0Fh
B1h
mm-xxx-xxx
vector
CMPXCHG8B EDX:EAX
0Fh
C7h
11-xxx-xxx
vector
CMPXCHG8B mem64
0Fh
C7h
mm-xxx-xxx
vector
CPUID
0Fh
A2h
CWD/CDQ EDX, EAX
99h
vector
DAA
27h
vector
DAS
2Fh
vector
DEC EAX
48h
short
alu
DEC ECX
49h
short
alu
DEC EDX
4Ah
short
alu
DEC EBX
4Bh
short
alu
DEC ESP
4Ch
short
alu
DEC EBP
4Dh
short
alu
DEC ESI
4Eh
short
alu
DEC EDI
4Fh
short
alu
DEC mreg8
FEh
11-001-xxx
vector
DEC mem8
FEh
mm-001-xxx
long
DEC mreg16/32
FFh
11-001-xxx
vector
DEC mem16/32
FFh
mm-001-xxx
long
DIV AL, mreg8
F6h
11-110-xxx
vector
DIV AL, mem8
F6h
mm-110-xxx
vector
DIV EAX, mreg16/32
F7h
11-110-xxx
vector
DIV EAX, mem16/32
F7h
mm-110-xxx
vector
IDIV mreg8
F6h
11-111-xxx
vector
68
Second
Byte
RISC86
Operations
vector
Software Environment
load, alux, store
load, alu, store
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
IDIV mem8
F6h
mm-111-xxx
vector
IDIV EAX, mreg16/32
F7h
11-111-xxx
vector
IDIV EAX, mem16/32
F7h
mm-111-xxx
vector
IMUL reg16/32, imm16/32
69h
11-xxx-xxx
vector
IMUL reg16/32, mreg16/32, imm16/32
69h
11-xxx-xxx
vector
IMUL reg16/32, mem16/32, imm16/32
69h
mm-xxx-xxx
vector
IMUL reg16/32, imm8 (sign extended)
6Bh
11-xxx-xxx
vector
IMUL reg16/32, mreg16/32, imm8 (signed)
6Bh
11-xxx-xxx
vector
IMUL reg16/32, mem16/32, imm8 (signed)
6Bh
mm-xxx-xxx
vector
IMUL AX, AL, mreg8
F6h
11-101-xxx
vector
IMUL AX, AL, mem8
F6h
mm-101-xxx
vector
IMUL EDX:EAX, EAX, mreg16/32
F7h
11-101-xxx
vector
IMUL EDX:EAX, EAX, mem16/32
F7h
mm-101-xxx
vector
IMUL reg16/32, mreg16/32
0Fh
AFh
11-xxx-xxx
vector
IMUL reg16/32, mem16/32
0Fh
AFh
mm-xxx-xxx
vector
IN AL, imm8
E4h
vector
IN AX, imm8
E5h
vector
IN EAX, imm8
E5h
vector
IN AL, DX
ECh
vector
IN AX, DX
EDh
vector
IN EAX, DX
EDh
vector
INC EAX
40h
short
alu
INC ECX
41h
short
alu
INC EDX
42h
short
alu
INC EBX
43h
short
alu
INC ESP
44h
short
alu
INC EBP
45h
short
alu
INC ESI
46h
short
alu
INC EDI
47h
short
alu
INC mreg8
FEh
11-000-xxx
vector
INC mem8
FEh
mm-000-xxx
long
INC mreg16/32
FFh
11-000-xxx
vector
INC mem16/32
FFh
mm-000-xxx
long
INVD
0Fh
08h
INVLPG
0Fh
01h
Chapter 3
load, alux, store
load, alu, store
vector
mm-111-xxx
Software Environment
vector
69
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
JO short disp8
70h
short
branch
JB/JNAE short disp8
71h
short
branch
JNO short disp8
71h
short
branch
JNB/JAE short disp8
73h
short
branch
JZ/JE short disp8
74h
short
branch
JNZ/JNE short disp8
75h
short
branch
JBE/JNA short disp8
76h
short
branch
JNBE/JA short disp8
77h
short
branch
JS short disp8
78h
short
branch
JNS short disp8
79h
short
branch
JP/JPE short disp8
7Ah
short
branch
JNP/JPO short disp8
7Bh
short
branch
JL/JNGE short disp8
7Ch
short
branch
JNL/JGE short disp8
7Dh
short
branch
JLE/JNG short disp8
7Eh
short
branch
JNLE/JG short disp8
7Fh
short
branch
JCXZ/JEC short disp8
E3h
vector
JO near disp16/32
0Fh
80h
short
branch
JNO near disp16/32
0Fh
81h
short
branch
JB/JNAE near disp16/32
0Fh
82h
short
branch
JNB/JAE near disp16/32
0Fh
83h
short
branch
JZ/JE near disp16/32
0Fh
84h
short
branch
JNZ/JNE near disp16/32
0Fh
85h
short
branch
JBE/JNA near disp16/32
0Fh
86h
short
branch
JNBE/JA near disp16/32
0Fh
87h
short
branch
JS near disp16/32
0Fh
88h
short
branch
JNS near disp16/32
0Fh
89h
short
branch
JP/JPE near disp16/32
0Fh
8Ah
short
branch
JNP/JPO near disp16/32
0Fh
8Bh
short
branch
JL/JNGE near disp16/32
0Fh
8Ch
short
branch
JNL/JGE near disp16/32
0Fh
8Dh
short
branch
JLE/JNG near disp16/32
0Fh
8Eh
short
branch
JNLE/JG near disp16/32
0Fh
8Fh
short
branch
JMP near disp16/32 (direct)
E9h
short
branch
JMP far disp32/48 (direct)
EAh
vector
70
Second
Byte
ModR/M
Byte
Software Environment
Decode
Type
RISC86
Operations
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
JMP disp8 (short)
EBh
JMP far mreg32 (indirect)
EFh
11-101-xxx
vector
JMP far mem32 (indirect)
EFh
mm-101-xxx
vector
JMP near mreg16/32 (indirect)
FFh
11-100-xxx
vector
JMP near mem16/32 (indirect)
FFh
mm-100-xxx
vector
LAHF
9Fh
LAR reg16/32, mreg16/32
0Fh
02h
11-xxx-xxx
vector
LAR reg16/32, mem16/32
0Fh
02h
mm-xxx-xxx
vector
LDS reg16/32, mem32/48
C5h
mm-xxx-xxx
vector
LEA reg16/32, mem16/32
8Dh
mm-xxx-xxx
short
load, alu
LEAVE
C9h
long
load, alu, alu
LES reg16/32, mem32/48
C4h
LFS reg16/32, mem32/48
0Fh
B4h
LGDT mem48
0Fh
01h
LGS reg16/32, mem32/48
0Fh
B5h
LIDT mem48
0Fh
01h
mm-011-xxx
vector
LLDT mreg16
0Fh
00h
11-010-xxx
vector
LLDT mem16
0Fh
00h
mm-010-xxx
vector
LMSW mreg16
0Fh
01h
11-100-xxx
vector
LMSW mem16
0Fh
01h
mm-100-xxx
vector
LODSB AL, mem8
ACh
long
load, alu
LODSW AX, mem16
ADh
long
load, alu
LODSD EAX, mem32
ADh
long
load, alu
LOOP disp8
E2h
short
alu, branch
LOOPE/LOOPZ disp8
E1h
vector
LOOPNE/LOOPNZ disp8
E0h
vector
LSL reg16/32, mreg16/32
0Fh
03h
11-xxx-xxx
vector
LSL reg16/32, mem16/32
0Fh
03h
mm-xxx-xxx
vector
LSS reg16/32, mem32/48
0Fh
B2h
mm-xxx-xxx
vector
LTR mreg16
0Fh
00h
11-011-xxx
vector
LTR mem16
0Fh
00h
mm-011-xxx
vector
MOV mreg8, reg8
88h
11-xxx-xxx
short
alux
MOV mem8, reg8
88h
mm-xxx-xxx
short
store
MOV mreg16/32, reg16/32
89h
11-xxx-xxx
short
alu
MOV mem16/32, reg16/32
89h
mm-xxx-xxx
short
store
Chapter 3
Second
Byte
ModR/M
Byte
Decode
Type
short
RISC86
Operations
branch
vector
mm-xxx-xxx
vector
vector
mm-010-xxx
vector
vector
Software Environment
71
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
MOV reg8, mreg8
ModR/M
Byte
Decode
Type
8Ah
11-xxx-xxx
short
alux
MOV reg8, mem8
8Ah
mm-xxx-xxx
short
load
MOV reg16/32, mreg16/32
8Bh
11-xxx-xxx
short
alu
MOV reg16/32, mem16/32
8Bh
mm-xxx-xxx
short
load
MOV mreg16, segment reg
8Ch
11-xxx-xxx
long
load
MOV mem16, segment reg
8Ch
mm-xxx-xxx
vector
MOV segment reg, mreg16
8Eh
11-xxx-xxx
vector
MOV segment reg, mem16
8Eh
mm-xxx-xxx
vector
MOV AL, mem8
A0h
short
load
MOV EAX, mem16/32
A1h
short
load
MOV mem8, AL
A2h
short
store
MOV mem16/32, EAX
A3h
short
store
MOV AL, imm8
B0h
short
limm
MOV CL, imm8
B1h
short
limm
MOV DL, imm8
B2h
short
limm
MOV BL, imm8
B3h
short
limm
MOV AH, imm8
B4h
short
limm
MOV CH, imm8
B5h
short
limm
MOV DH, imm8
B6h
short
limm
MOV BH, imm8
B7h
short
limm
MOV EAX, imm16/32
B8h
short
limm
MOV ECX, imm16/32
B9h
short
limm
MOV EDX, imm16/32
BAh
short
limm
MOV EBX, imm16/32
BBh
short
limm
MOV ESP, imm16/32
BCh
short
limm
MOV EBP, imm16/32
BDh
short
limm
MOV ESI, imm16/32
BEh
short
limm
MOV EDI, imm16/32
BFh
short
limm
MOV mreg8, imm8
C6h
11-000-xxx
short
limm
MOV mem8, imm8
C6h
mm-000-xxx
long
store
MOV mreg16/32, imm16/32
C7h
11-000-xxx
short
limm
MOV mem16/32, imm16/32
C7h
mm-000-xxx
long
store
MOV reg32, CR0
0Fh
20h
11-000-xxx
vector
MOV reg32, CR2
0Fh
20h
11-010-xxx
vector
MOV reg32, CR3
0Fh
20h
11-011-xxx
vector
72
Second
Byte
Software Environment
RISC86
Operations
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type
MOV reg32, CR4
0Fh
20h
11-100-xxx
vector
MOV CR0, reg32
0Fh
22h
11-000-xxx
vector
MOV CR2, reg32
0Fh
22h
11-010-xxx
vector
MOV CR3, reg32
0Fh
22h
11-011-xxx
vector
MOV CR4, reg32
0Fh
22h
11-100-xxx
vector
MOVSB mem8,mem8
A4h
long
load, store, alux, alux
MOVSD mem16, mem16
A5h
long
load, store, alu, alu
MOVSW mem32, mem32
A5h
long
load, store, alu, alu
MOVSX reg16/32, mreg8
0Fh
BEh
11-xxx-xxx
short
alu
MOVSX reg16/32, mem8
0Fh
BEh
mm-xxx-xxx
short
load, alu
MOVSX reg32, mreg16
0Fh
BFh
11-xxx-xxx
short
alu
MOVSX reg32, mem16
0Fh
BFh
mm-xxx-xxx
short
load, alu
MOVZX reg16/32, mreg8
0Fh
B6h
11-xxx-xxx
short
alu
MOVZX reg16/32, mem8
0Fh
B6h
mm-xxx-xxx
short
load, alu
MOVZX reg32, mreg16
0Fh
B7h
11-xxx-xxx
short
alu
MOVZX reg32, mem16
0Fh
B7h
mm-xxx-xxx
short
load, alu
MUL AL, mreg8
F6h
11-100-xxx
vector
MUL AL, mem8
F6h
mm-100-xxx
vector
MUL EAX, mreg16/32
F7h
11-100-xxx
vector
MUL EAX, mem16/32
F7h
mm-100-xxx
vector
NEG mreg8
F6h
11-011-xxx
short
NEG mem8
F6h
mm-011-xxx
vector
NEG mreg16/32
F7h
11-011-xxx
short
NEG mem16/32
F7h
mm-011-xxx
vector
NOP (XCHG EAX, EAX)
90h
NOT mreg8
F6h
NOT mem8
Instruction Mnemonic
RISC86
Operations
alux
alu
short
limm
11-010-xxx
short
alux
F6h
mm-010-xxx
vector
NOT mreg16/32
F7h
11-010-xxx
short
NOT mem16/32
F7h
mm-010-xxx
vector
OR mreg8, reg8
08h
11-xxx-xxx
short
alux
OR mem8, reg8
08h
mm-xxx-xxx
long
load, alux, store
OR mreg16/32, reg16/32
09h
11-xxx-xxx
short
alu
OR mem16/32, reg16/32
09h
mm-xxx-xxx
long
load, alu, store
OR reg8, mreg8
0Ah
11-xxx-xxx
short
alux
OR reg8, mem8
0Ah
mm-xxx-xxx
short
load, alux
Chapter 3
Software Environment
alu
73
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
OR reg16/32, mreg16/32
ModR/M
Byte
Decode
Type
0Bh
11-xxx-xxx
short
alu
OR reg16/32, mem16/32
0Bh
mm-xxx-xxx
short
load, alu
OR AL, imm8
0Ch
short
alux
OR EAX, imm16/32
0Dh
short
alu
OR mreg8, imm8
80h
11-001-xxx
short
alux
OR mem8, imm8
80h
mm-001-xxx
long
load, alux, store
OR mreg16/32, imm16/32
81h
11-001-xxx
short
alu
OR mem16/32, imm16/32
81h
mm-001-xxx
long
load, alu, store
OR mreg16/32, imm8 (signed ext.)
83h
11-001-xxx
short
alux
OR mem16/32, imm8 (signed ext.)
83h
mm-001-xxx
long
load, alux, store
OUT imm8, AL
E6h
vector
OUT imm8, AX
E7h
vector
OUT imm8, EAX
E7h
vector
OUT DX, AL
EEh
vector
OUT DX, AX
EFh
vector
OUT DX, EAX
EFh
vector
POP ES
07h
vector
POP SS
17h
vector
POP DS
1Fh
vector
POP FS
0Fh
A1h
vector
POP GS
0Fh
A9h
vector
POP EAX
58h
short
load, alu
POP ECX
59h
short
load, alu
POP EDX
5Ah
short
load, alu
POP EBX
5Bh
short
load, alu
POP ESP
5Ch
short
load, alu
POP EBP
5Dh
short
load, alu
POP ESI
5Eh
short
load, alu
POP EDI
5Fh
short
load, alu
POP mreg 16/32
8Fh
11-000-xxx
short
load, alu
POP mem 16/32
8Fh
mm-000-xxx
long
load, store, alu
POPA/POPAD
61h
vector
POPF/POPFD
9Dh
vector
PUSH ES
06h
long
PUSH CS
0Eh
vector
74
Second
Byte
Software Environment
RISC86
Operations
load, store
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
First
Byte
Second
Byte
PUSH FS
0Fh
A0h
vector
PUSH GS
0Fh
A8h
vector
PUSH SS
16h
vector
PUSH DS
1Eh
long
load, store
PUSH EAX
50h
short
store
PUSH ECX
51h
short
store
PUSH EDX
52h
short
store
PUSH EBX
53h
short
store
PUSH ESP
54h
short
store
PUSH EBP
55h
short
store
PUSH ESI
56h
short
store
PUSH EDI
57h
short
store
PUSH imm8
6Ah
long
store
PUSH imm16/32
68h
long
store
PUSH mreg16/32
FFh
11-110-xxx
vector
PUSH mem16/32
FFh
mm-110-xxx
long
PUSHA/PUSHAD
60h
vector
PUSHF/PUSHFD
9Ch
vector
RCL mreg8, imm8
C0h
11-010-xxx
vector
RCL mem8, imm8
C0h
mm-010-xxx
vector
RCL mreg16/32, imm8
C1h
11-010-xxx
vector
RCL mem16/32, imm8
C1h
mm-010-xxx
vector
RCL mreg8, 1
D0h
11-010-xxx
vector
RCL mem8, 1
D0h
mm-010-xxx
vector
RCL mreg16/32, 1
D1h
11-010-xxx
vector
RCL mem16/32, 1
D1h
mm-010-xxx
vector
RCL mreg8, CL
D2h
11-010-xxx
vector
RCL mem8, CL
D2h
mm-010-xxx
vector
RCL mreg16/32, CL
D3h
11-010-xxx
vector
RCL mem16/32, CL
D3h
mm-010-xxx
vector
RCR mreg8, imm8
C0h
11-011-xxx
vector
RCR mem8, imm8
C0h
mm-011-xxx
vector
RCR mreg16/32, imm8
C1h
11-011-xxx
vector
RCR mem16/32, imm8
C1h
mm-011-xxx
vector
RCR mreg8, 1
D0h
11-011-xxx
vector
Instruction Mnemonic
Chapter 3
ModR/M
Byte
Software Environment
Decode
Type
RISC86
Operations
load, store
75
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
RCR mem8, 1
ModR/M
Byte
Decode
Type
D0h
mm-011-xxx
vector
RCR mreg16/32, 1
D1h
11-011-xxx
vector
RCR mem16/32, 1
D1h
mm-011-xxx
vector
RCR mreg8, CL
D2h
11-011-xxx
vector
RCR mem8, CL
D2h
mm-011-xxx
vector
RCR mreg16/32, CL
D3h
11-011-xxx
vector
RCR mem16/32, CL
D3h
mm-011-xxx
vector
RDMSR
0Fh
32h
vector
RDTSC
0Fh
31h
vector
RET near imm16
C2h
vector
RET near
C3h
vector
RET far imm16
CAh
vector
RET far
CBh
vector
ROL mreg8, imm8
C0h
11-000-xxx
vector
ROL mem8, imm8
C0h
mm-000-xxx
vector
ROL mreg16/32, imm8
C1h
11-000-xxx
vector
ROL mem16/32, imm8
C1h
mm-000-xxx
vector
ROL mreg8, 1
D0h
11-000-xxx
vector
ROL mem8, 1
D0h
mm-000-xxx
vector
ROL mreg16/32, 1
D1h
11-000-xxx
vector
ROL mem16/32, 1
D1h
mm-000-xxx
vector
ROL mreg8, CL
D2h
11-000-xxx
vector
ROL mem8, CL
D2h
mm-000-xxx
vector
ROL mreg16/32, CL
D3h
11-000-xxx
vector
ROL mem16/32, CL
D3h
mm-000-xxx
vector
ROR mreg8, imm8
C0h
11-001-xxx
vector
ROR mem8, imm8
C0h
mm-001-xxx
vector
ROR mreg16/32, imm8
C1h
11-001-xxx
vector
ROR mem16/32, imm8
C1h
mm-001-xxx
vector
ROR mreg8, 1
D0h
11-001-xxx
vector
ROR mem8, 1
D0h
mm-001-xxx
vector
ROR mreg16/32, 1
D1h
11-001-xxx
vector
ROR mem16/32, 1
D1h
mm-001-xxx
vector
ROR mreg8, CL
D2h
11-001-xxx
vector
ROR mem8, CL
D2h
mm-001-xxx
vector
76
Second
Byte
Software Environment
RISC86
Operations
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
ROR mreg16/32, CL
ModR/M
Byte
Decode
Type
D3h
11-001-xxx
vector
ROR mem16/32, CL
D3h
mm-001-xxx
vector
RSM
0Fh
SAHF
9Eh
SAR mreg8, imm8
C0h
11-111-xxx
short
SAR mem8, imm8
C0h
mm-111-xxx
vector
SAR mreg16/32, imm8
C1h
11-111-xxx
short
SAR mem16/32, imm8
C1h
mm-111-xxx
vector
SAR mreg8, 1
D0h
11-111-xxx
short
SAR mem8, 1
D0h
mm-111-xxx
vector
SAR mreg16/32, 1
D1h
11-111-xxx
short
SAR mem16/32, 1
D1h
mm-111-xxx
vector
SAR mreg8, CL
D2h
11-111-xxx
short
SAR mem8, CL
D2h
mm-111-xxx
vector
SAR mreg16/32, CL
D3h
11-111-xxx
short
SAR mem16/32, CL
D3h
mm-111-xxx
vector
SBB mreg8, reg8
18h
11-xxx-xxx
vector
SBB mem8, reg8
18h
mm-xxx-xxx
vector
SBB mreg16/32, reg16/32
19h
11-xxx-xxx
vector
SBB mem16/32, reg16/32
19h
mm-xxx-xxx
vector
SBB reg8, mreg8
1Ah
11-xxx-xxx
vector
SBB reg8, mem8
1Ah
mm-xxx-xxx
vector
SBB reg16/32, mreg16/32
1Bh
11-xxx-xxx
vector
SBB reg16/32, mem16/32
1Bh
mm-xxx-xxx
vector
SBB AL, imm8
1Ch
vector
SBB EAX, imm16/32
1Dh
vector
SBB mreg8, imm8
80h
11-011-xxx
vector
SBB mem8, imm8
80h
mm-011-xxx
vector
SBB mreg16/32, imm16/32
81h
11-011-xxx
vector
SBB mem16/32, imm16/32
81h
mm-011-xxx
vector
SBB mreg16/32, imm8 (signed ext.)
83h
11-011-xxx
vector
SBB mem16/32, imm8 (signed ext.)
83h
mm-011-xxx
vector
SCASB AL, mem8
AEh
vector
SCASW AX, mem16
AFh
vector
SCASD EAX, mem32
AFh
vector
Chapter 3
Second
Byte
AAh
RISC86
Operations
vector
vector
Software Environment
alux
alu
alux
alu
alux
alu
77
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type
SETO mreg8
0Fh
90h
11-xxx-xxx
vector
SETO mem8
0Fh
90h
mm-xxx-xxx
vector
SETNO mreg8
0Fh
91h
11-xxx-xxx
vector
SETNO mem8
0Fh
91h
mm-xxx-xxx
vector
SETB/SETNAE mreg8
0Fh
92h
11-xxx-xxx
vector
SETB/SETNAE mem8
0Fh
92h
mm-xxx-xxx
vector
SETNB/SETAE mreg8
0Fh
93h
11-xxx-xxx
vector
SETNB/SETAE mem8
0Fh
93h
mm-xxx-xxx
vector
SETZ/SETE mreg8
0Fh
94h
11-xxx-xxx
vector
SETZ/SETE mem8
0Fh
94h
mm-xxx-xxx
vector
SETNZ/SETNE mreg8
0Fh
95h
11-xxx-xxx
vector
SETNZ/SETNE mem8
0Fh
95h
mm-xxx-xxx
vector
SETBE/SETNA mreg8
0Fh
96h
11-xxx-xxx
vector
SETBE/SETNA mem8
0Fh
96h
mm-xxx-xxx
vector
SETNBE/SETA mreg8
0Fh
97h
11-xxx-xxx
vector
SETNBE/SETA mem8
0Fh
97h
mm-xxx-xxx
vector
SETS mreg8
0Fh
98h
11-xxx-xxx
vector
SETS mem8
0Fh
98h
mm-xxx-xxx
vector
SETNS mreg8
0Fh
99h
11-xxx-xxx
vector
SETNS mem8
0Fh
99h
mm-xxx-xxx
vector
SETP/SETPE mreg8
0Fh
9Ah
11-xxx-xxx
vector
SETP/SETPE mem8
0Fh
9Ah
mm-xxx-xxx
vector
SETNP/SETPO mreg8
0Fh
9Bh
11-xxx-xxx
vector
SETNP/SETPO mem8
0Fh
9Bh
mm-xxx-xxx
vector
SETL/SETNGE mreg8
0Fh
9Ch
11-xxx-xxx
vector
SETL/SETNGE mem8
0Fh
9Ch
mm-xxx-xxx
vector
SETNL/SETGE mreg8
0Fh
9Dh
11-xxx-xxx
vector
SETNL/SETGE mem8
0Fh
9Dh
mm-xxx-xxx
vector
SETLE/SETNG mreg8
0Fh
9Eh
11-xxx-xxx
vector
SETLE/SETNG mem8
0Fh
9Eh
mm-xxx-xxx
vector
SETNLE/SETG mreg8
0Fh
9Fh
11-xxx-xxx
vector
SETNLE/SETG mem8
0Fh
9Fh
mm-xxx-xxx
vector
SGDT mem48
0Fh
01h
mm-000-xxx
vector
SIDT mem48
0Fh
01h
mm-001-xxx
vector
SHL/SAL mreg8, imm8
C0h
11-100-xxx
short
Instruction Mnemonic
78
Software Environment
RISC86
Operations
alux
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
SHL/SAL mem8, imm8
ModR/M
Byte
Decode
Type
C0h
mm-100-xxx
vector
SHL/SAL mreg16/32, imm8
C1h
11-100-xxx
short
SHL/SAL mem16/32, imm8
C1h
mm-100-xxx
vector
SHL/SAL mreg8, 1
D0h
11-100-xxx
short
SHL/SAL mem8, 1
D0h
mm-100-xxx
vector
SHL/SAL mreg16/32, 1
D1h
11-100-xxx
short
SHL/SAL mem16/32, 1
D1h
mm-100-xxx
vector
SHL/SAL mreg8, CL
D2h
11-100-xxx
short
SHL/SAL mem8, CL
D2h
mm-100-xxx
vector
SHL/SAL mreg16/32, CL
D3h
11-100-xxx
short
SHL/SAL mem16/32, CL
D3h
mm-100-xxx
vector
SHR mreg8, imm8
C0h
11-101-xxx
short
SHR mem8, imm8
C0h
mm-101-xxx
vector
SHR mreg16/32, imm8
C1h
11-101-xxx
short
SHR mem16/32, imm8
C1h
mm-101-xxx
vector
SHR mreg8, 1
D0h
11-101-xxx
short
SHR mem8, 1
D0h
mm-101-xxx
vector
SHR mreg16/32, 1
D1h
11-101-xxx
short
SHR mem16/32, 1
D1h
mm-101-xxx
vector
SHR mreg8, CL
D2h
11-101-xxx
short
SHR mem8, CL
D2h
mm-101-xxx
vector
SHR mreg16/32, CL
D3h
11-101-xxx
short
SHR mem16/32, CL
D3h
mm-101-xxx
vector
SHLD mreg16/32, reg16/32, imm8
0Fh
A4h
11-xxx-xxx
vector
SHLD mem16/32, reg16/32, imm8
0Fh
A4h
mm-xxx-xxx
vector
SHLD mreg16/32, reg16/32, CL
0Fh
A5h
11-xxx-xxx
vector
SHLD mem16/32, reg16/32, CL
0Fh
A5h
mm-xxx-xxx
vector
SHRD mreg16/32, reg16/32, imm8
0Fh
ACh
11-xxx-xxx
vector
SHRD mem16/32, reg16/32, imm8
0Fh
ACh
mm-xxx-xxx
vector
SHRD mreg16/32, reg16/32, CL
0Fh
ADh
11-xxx-xxx
vector
SHRD mem16/32, reg16/32, CL
0Fh
ADh
mm-xxx-xxx
vector
SLDT mreg16
0Fh
00h
11-000-xxx
vector
SLDT mem16
0Fh
00h
mm-000-xxx
vector
SMSW mreg16
0Fh
01h
11-100-xxx
vector
SMSW mem16
0Fh
01h
mm-100-xxx
vector
Chapter 3
Second
Byte
Software Environment
RISC86
Operations
alu
alux
alu
alux
alu
alux
alu
alux
alu
alux
alu
79
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
STC
F9h
vector
STD
FDh
vector
STI
FBh
vector
STOSB mem8, AL
AAh
long
store, alux
STOSW mem16, AX
ABh
long
store, alux
STOSD mem32, EAX
ABh
long
store, alux
STR mreg16
0Fh
00h
11-001-xxx
vector
STR mem16
0Fh
00h
mm-001-xxx
vector
SUB mreg8, reg8
28h
11-xxx-xxx
short
alux
SUB mem8, reg8
28h
mm-xxx-xxx
long
load, alux, store
SUB mreg16/32, reg16/32
29h
11-xxx-xxx
short
alu
SUB mem16/32, reg16/32
29h
mm-xxx-xxx
long
load, alu, store
SUB reg8, mreg8
2Ah
11-xxx-xxx
short
alux
SUB reg8, mem8
2Ah
mm-xxx-xxx
short
load, alux
SUB reg16/32, mreg16/32
2Bh
11-xxx-xxx
short
alu
SUB reg16/32, mem16/32
2Bh
mm-xxx-xxx
short
load, alu
SUB AL, imm8
2Ch
short
alux
SUB EAX, imm16/32
2Dh
short
alu
SUB mreg8, imm8
80h
11-101-xxx
short
alux
SUB mem8, imm8
80h
mm-101-xxx
long
load, alux, store
SUB mreg16/32, imm16/32
81h
11-101-xxx
short
alu
SUB mem16/32, imm16/32
81h
mm-101-xxx
long
load, alu, store
SUB mreg16/32, imm8 (signed ext.)
83h
11-101-xxx
short
alux
SUB mem16/32, imm8 (signed ext.)
83h
mm-101-xxx
long
load, alux, store
SYSCALL
0Fh
05h
vector
SYSRET
0Fh
07h
vector
TEST mreg8, reg8
84h
11-xxx-xxx
short
TEST mem8, reg8
84h
mm-xxx-xxx
vector
TEST mreg16/32, reg16/32
85h
11-xxx-xxx
short
TEST mem16/32, reg16/32
85h
mm-xxx-xxx
vector
TEST AL, imm8
A8h
long
alux
TEST EAX, imm16/32
A9h
long
alu
TEST mreg8, imm8
F6h
11-000-xxx
long
alux
TEST mem8, imm8
F6h
mm-000-xxx
long
load, alux
TEST mreg16/32, imm16/32
F7h
11-000-xxx
long
alu
80
Software Environment
alux
alu
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type
mm-000-xxx
long
RISC86
Operations
TEST mem16/32, imm16/32
F7h
VERR mreg16
0Fh
00h
11-100-xxx
vector
VERR mem16
0Fh
00h
mm-100-xxx
vector
VERW mreg16
0Fh
00h
11-101-xxx
vector
VERW mem16
0Fh
00h
mm-101-xxx
vector
WAIT
9Bh
WBINVD
0Fh
09h
vector
WRMSR
0Fh
30h
vector
XADD mreg8, reg8
0Fh
C0h
11-100-xxx
vector
XADD mem8, reg8
0Fh
C0h
mm-100-xxx
vector
XADD mreg16/32, reg16/32
0Fh
C1h
11-101-xxx
vector
XADD mem16/32, reg16/32
0Fh
C1h
mm-101-xxx
vector
XCHG reg8, mreg8
86h
11-xxx-xxx
vector
XCHG reg8, mem8
86h
mm-xxx-xxx
vector
XCHG reg16/32, mreg16/32
87h
11-xxx-xxx
vector
XCHG reg16/32, mem16/32
87h
mm-xxx-xxx
vector
XCHG EAX, EAX
90h
short
limm
XCHG EAX, ECX
91h
long
alu, alu, alu
XCHG EAX, EDX
92h
long
alu, alu, alu
XCHG EAX, EBX
93h
long
alu, alu, alu
XCHG EAX, ESP
94h
long
alu, alu, alu
XCHG EAX, EBP
95h
long
alu, alu, alu
XCHG EAX, ESI
96h
long
alu, alu, alu
XCHG EAX, EDI
97h
long
alu, alu, alu
XLAT
D7h
vector
XOR mreg8, reg8
30h
11-xxx-xxx
short
alux
XOR mem8, reg8
30h
mm-xxx-xxx
long
load, alux, store
XOR mreg16/32, reg16/32
31h
11-xxx-xxx
short
alu
XOR mem16/32, reg16/32
31h
mm-xxx-xxx
long
load, alu, store
XOR reg8, mreg8
32h
11-xxx-xxx
short
alux
XOR reg8, mem8
32h
mm-xxx-xxx
short
load, alux
XOR reg16/32, mreg16/32
33h
11-xxx-xxx
short
alu
XOR reg16/32, mem16/32
33h
mm-xxx-xxx
short
load, alu
XOR AL, imm8
34h
short
alux
XOR EAX, imm16/32
35h
short
alu
Chapter 3
load, alu
vector
Software Environment
81
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 12. Integer Instructions (continued)
Instruction Mnemonic
First
Byte
XOR mreg8, imm8
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
80h
11-110-xxx
short
alux
XOR mem8, imm8
80h
mm-110-xxx
long
load, alux, store
XOR mreg16/32, imm16/32
81h
11-110-xxx
short
alu
XOR mem16/32, imm16/32
81h
mm-110-xxx
long
load, alu, store
XOR mreg16/32, imm8 (signed ext.)
83h
11-110-xxx
short
alux
XOR mem16/32, imm8 (signed ext.)
83h
mm-110-xxx
long
load, alux, store
ModR/M
Byte
Decode
Type
Table 13. Floating-Point Instructions
Instruction Mnemonic
First
Byte
Second
Byte
F2XM1
D9h
F0h
short
float
FABS
D9h
F1h
short
float
FADD ST(0), ST(i)1
D8h
11-000-xxx
short
float
FADD ST(0), mem32real
D8h
mm-000-xxx
short
fload, float
FADD ST(i), ST(0)1
DCh
11-000-xxx
short
float
DCh
mm-000-xxx
short
fload, float
DEh
11-000-xxx
short
float
FBLD
DFh
mm-100-xxx
vector
FBSTP
DFh
mm-110-xxx
vector
FCHS
D9h
E0h
short
FCLEX
DBh
E2h
vector
FCOM ST(0), ST(i)1
D8h
11-010-xxx
short
float
FCOM ST(0), mem32real
D8h
mm-010-xxx
short
fload, float
FCOM ST(0), mem64real
DCh
mm-010-xxx
short
fload, float
FCOMP ST(0), ST(i)1
D8h
11-011-xxx
short
float
FCOMP ST(0), mem32real
D8h
mm-011-xxx
short
fload, float
FCOMP ST(0), mem64real
DCh
mm-011-xxx
short
fload, float
FCOMPP
DEh
D9h
11-011-001
short
float
FCOS
D9h
FFh
short
float
D9h
F6h
short
float
FADD ST(0), mem64real
FADDP ST(i), ST(0)
1
FDECSTP
1
RISC86
Operations
float
D8h
11-110-xxx
short
float
FDIV ST(0), ST(i) (double precision)1
D8h
11-110-xxx
short
float
FDIV ST(0), ST(i) (extended precision)1
D8h
11-110-xxx
short
float
FDIV ST(0), ST(i) (single precision)
82
Software Environment
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 13. Floating-Point Instructions (continued)
Instruction Mnemonic
First
Byte
FDIV ST(i), ST(0) (single precision)1
ModR/M
Byte
Decode
Type
DCh
11-111-xxx
short
float
FDIV ST(i), ST(0) (double precision)1
DCh
11-111-xxx
short
float
FDIV ST(i), ST(0) (extended precision)1
DCh
11-111-xxx
short
float
FDIV ST(0), mem32real
D8h
mm-110-xxx
short
fload, float
FDIV ST(0), mem64real
DCh
mm-110-xxx
short
fload, float
FDIVP ST(0), ST(i)1
DEh
11-111-xxx
short
float
FDIVR ST(0), ST(i)1
D8h
11-110-xxx
short
float
FDIVR ST(i), ST(0)1
DCh
11-111-xxx
short
float
FDIVR ST(0), mem32real
D8h
mm-111-xxx
short
fload, float
FDIVR ST(0), mem64real
DCh
mm-111-xxx
short
fload, float
FDIVRP ST(i), ST(0)1
DEh
11-110-xxx
short
float
FFREE ST(i)1
DDh
11-000-xxx
short
float
FIADD ST(0), mem32int
DAh
mm-000-xxx
short
fload, float
FIADD ST(0), mem16int
DEh
mm-000-xxx
short
fload, float
FICOM ST(0), mem32int
DAh
mm-010-xxx
short
fload, float
FICOM ST(0), mem16int
DEh
mm-010-xxx
short
fload, float
FICOMP ST(0), mem32int
DAh
mm-011-xxx
short
fload, float
FICOMP ST(0), mem16int
DEh
mm-011-xxx
short
fload, float
FIDIV ST(0), mem32int
DAh
mm-110-xxx
short
fload, float
FIDIV ST(0), mem16int
DEh
mm-110-xxx
short
fload, float
FIDIVR ST(0), mem32int
DAh
mm-111-xxx
short
fload, float
FIDIVR ST(0), mem16int
DEh
mm-111-xxx
short
fload, float
FILD mem16int
DFh
mm-000-xxx
short
fload, float
FILD mem32int
DBh
mm-000-xxx
short
fload, float
FILD mem64int
DFh
mm-101-xxx
short
fload, float
FIMUL ST(0), mem32int
DAh
mm-001-xxx
short
fload, float
FIMUL ST(0), mem16int
DEh
mm-001-xxx
short
fload, float
FINCSTP
D9h
F7h
short
FINIT
DBh
E3h
vector
FIST mem16int
DFh
mm-010-xxx
short
fload, float
FIST mem32int
DBh
mm-010-xxx
short
fload, float
FISTP mem16int
DFh
mm-011-xxx
short
fload, float
FISTP mem32int
DBh
mm-011-xxx
short
fload, float
FISTP mem64int
DFh
mm-111-xxx
short
fload, float
Chapter 3
Second
Byte
Software Environment
RISC86
Operations
83
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 13. Floating-Point Instructions (continued)
Instruction Mnemonic
First
Byte
FISUB ST(0), mem32int
ModR/M
Byte
Decode
Type
DAh
mm-100-xxx
short
fload, float
FISUB ST(0), mem16int
DEh
mm-100-xxx
short
fload, float
FISUBR ST(0), mem32int
DAh
mm-101-xxx
short
fload, float
FISUBR ST(0), mem16int
DEh
mm-101-xxx
short
fload, float
FLD ST(i)1
D9h
11-000-xxx
short
fload, float
FLD mem32real
D9h
mm-000-xxx
short
fload, float
FLD mem64real
DDh
mm-000-xxx
short
fload, float
FLD mem80real
DBh
mm-101-xxx
vector
FLD1
D9h
FLDCW
D9h
mm-101-xxx
vector
FLDENV
D9h
mm-100-xxx
short
fload, float
FLDL2E
D9h
EAh
short
float
FLDL2T
D9h
E9h
short
float
FLDLG2
D9h
ECh
short
float
FLDLN2
D9h
EDh
short
float
FLDPI
D9h
EBh
short
float
FLDZ
D9h
EEh
short
float
FMUL ST(0), ST(i)1
D8h
11-001-xxx
short
float
FMUL ST(i), ST(0)1
DCh
11-001-xxx
short
float
FMUL ST(0), mem32real
D8h
mm-001-xxx
short
fload, float
FMUL ST(0), mem64real
DCh
mm-001-xxx
short
fload, float
FMULP ST(0), ST(i)1
DEh
11-001-xxx
short
float
FNOP
D9h
D0h
short
float
FPATAN
D9h
F3h
short
float
FPREM
D9h
F8h
short
float
FPREM1
D9h
F5h
short
float
FPTAN
D9h
F2h
vector
FRNDINT
D9h
FCh
short
FRSTOR
DDh
mm-100-xxx
vector
FSAVE
DDh
mm-110-xxx
vector
FSCALE
D9h
FDh
short
float
FSIN
D9h
FEh
short
float
FSINCOS
D9h
FBh
vector
FSQRT (single precision)
D9h
FAh
short
float
FSQRT (double precision)
D9h
FAh
short
float
84
Second
Byte
E8h
short
Software Environment
RISC86
Operations
fload, float
float
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 13. Floating-Point Instructions (continued)
Instruction Mnemonic
First
Byte
Second
Byte
FSQRT (extended precision)
D9h
FAh
FST mem32real
D9h
FST mem64real
ModR/M
Byte
Decode
Type
RISC86
Operations
short
float
mm-010-xxx
short
fstore
DDh
mm-010-xxx
short
fstore
FST ST(i)1
DDh
11-010-xxx
short
fstore
FSTCW
D9h
mm-111-xxx
vector
FSTENV
D9h
mm-110-xxx
vector
FSTP mem32real
D9h
mm-011-xxx
short
fstore
FSTP mem64real
DDh
mm-011-xxx
short
fstore
FSTP mem80real
D9h
mm-111-xxx
vector
FSTP ST(i)1
DDh
11-011-xxx
short
FSTSW AX
DFh
FSTSW mem16
DDh
mm-111-xxx
vector
FSUB ST(0), mem32real
D8h
mm-100-xxx
short
fload, float
FSUB ST(0), mem64real
E0h
float
vector
DCh
mm-100-xxx
short
fload, float
1
D8h
11-100-xxx
short
float
FSUB ST(i), ST(0)1
DCh
11-101-xxx
short
float
FSUBP ST(0), ST(i)1
DEh
11-101-xxx
short
float
FSUBR ST(0), mem32real
D8h
mm-101-xxx
short
fload, float
FSUBR ST(0), mem64real
FSUB ST(0), ST(i)
DCh
mm-101-xxx
short
fload, float
1
FSUBR ST(0), ST(i)
D8h
11-100-xxx
short
float
FSUBR ST(i), ST(0)1
DCh
11-101-xxx
short
float
FSUBRP ST(i), ST(0)1
DEh
11-100-xxx
short
float
FTST
D9h
short
float
FUCOM
DDh
11-100-xxx
short
float
FUCOMP
DDh
11-101-xxx
short
float
FUCOMPP
DAh
E9h
short
float
FXAM
D9h
E5h
short
float
FXCH
D9h
short
float
FXTRACT
D9h
F4h
vector
FYL2X
D9h
F1h
short
float
FYL2XP1
D9h
F9h
short
float
FWAIT
9Bh
E4h
11-001-xxx
vector
Notes:
1. The last three bits of the modR/M byte select the stack entry ST(i).
Chapter 3
Software Environment
85
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 14. MMX™ Instructions
Prefix
Byte(s)
First
Byte
EMMS
0Fh
77h
MOVD mmreg, mreg321
0Fh
6Eh
11-xxx-xxx
short
meu
MOVD mmreg, mem32
0Fh
6Eh
mm-xxx-xxx
short
mload
MOVD mreg32, mmreg1
0Fh
7Eh
11-xxx-xxx
short
mstore, load
MOVD mem32, mmreg
0Fh
7Eh
mm-xxx-xxx
short
mstore
MOVQ mmreg1, mmreg2
0Fh
6Fh
11-xxx-xxx
short
meu
MOVQ mmreg, mem64
0Fh
6Fh
mm-xxx-xxx
short
mload
MOVQ mmreg2, mmreg1
0Fh
7Fh
11-xxx-xxx
short
meu
MOVQ mem64, mmreg
0Fh
7Fh
mm-xxx-xxx
short
mstore
PACKSSDW mmreg1, mmreg2
0Fh
6Bh
11-xxx-xxx
short
meu
PACKSSDW mmreg, mem64
0Fh
6Bh
mm-xxx-xxx
short
mload, meu
PACKSSWB mmreg1, mmreg2
0Fh
63h
11-xxx-xxx
short
meu
PACKSSWB mmreg, mem64
0Fh
63h
mm-xxx-xxx
short
mload, meu
PACKUSWB mmreg1, mmreg2
0Fh
67h
11-xxx-xxx
short
meu
PACKUSWB mmreg, mem64
0Fh
67h
mm-xxx-xxx
short
mload, meu
PADDB mmreg1, mmreg2
0Fh
FCh
11-xxx-xxx
short
meu
PADDB mmreg, mem64
0Fh
FCh
mm-xxx-xxx
short
mload, meu
PADDD mmreg1, mmreg2
0Fh
FEh
11-xxx-xxx
short
meu
PADDD mmreg, mem64
0Fh
FEh
mm-xxx-xxx
short
mload, meu
PADDSB mmreg1, mmreg2
0Fh
ECh
11-xxx-xxx
short
meu
PADDSB mmreg, mem64
0Fh
ECh
mm-xxx-xxx
short
mload, meu
PADDSW mmreg1, mmreg2
0Fh
EDh
11-xxx-xxx
short
meu
PADDSW mmreg, mem64
0Fh
EDh
mm-xxx-xxx
short
mload, meu
PADDUSB mmreg1, mmreg2
0Fh
DCh
11-xxx-xxx
short
meu
PADDUSB mmreg, mem64
0Fh
DCh
mm-xxx-xxx
short
mload, meu
PADDUSW mmreg1, mmreg2
0Fh
DDh
11-xxx-xxx
short
meu
PADDUSW mmreg, mem64
0Fh
DDh
mm-xxx-xxx
short
mload, meu
PADDW mmreg1, mmreg2
0Fh
FDh
11-xxx-xxx
short
meu
PADDW mmreg, mem64
0Fh
FDh
mm-xxx-xxx
short
mload, meu
PAND mmreg1, mmreg2
0Fh
DBh
11-xxx-xxx
short
meu
PAND mmreg, mem64
0Fh
DBh
mm-xxx-xxx
short
mload, meu
PANDN mmreg1, mmreg2
0Fh
DFh
11-xxx-xxx
short
meu
PANDN mmreg, mem64
0Fh
DFh
mm-xxx-xxx
short
mload, meu
PCMPEQB mmreg1, mmreg2
0Fh
74h
11-xxx-xxx
short
meu
Instruction Mnemonic
86
ModR/M
Byte
Decode
Type
RISC86
Operations
vector
Software Environment
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 14. MMX™ Instructions (continued)
Instruction Mnemonic
Prefix
Byte(s)
First
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
PCMPEQB mmreg, mem64
0Fh
74h
mm-xxx-xxx
short
mload, meu
PCMPEQD mmreg1, mmreg2
0Fh
76h
11-xxx-xxx
short
meu
PCMPEQD mmreg, mem64
0Fh
76h
mm-xxx-xxx
short
mload, meu
PCMPEQW mmreg1, mmreg2
0Fh
75h
11-xxx-xxx
short
meu
PCMPEQW mmreg, mem64
0Fh
75h
mm-xxx-xxx
short
mload, meu
PCMPGTB mmreg1, mmreg2
0Fh
64h
11-xxx-xxx
short
meu
PCMPGTB mmreg, mem64
0Fh
64h
mm-xxx-xxx
short
mload, meu
PCMPGTD mmreg1, mmreg2
0Fh
66h
11-xxx-xxx
short
meu
PCMPGTD mmreg, mem64
0Fh
66h
mm-xxx-xxx
short
mload, meu
PCMPGTW mmreg1, mmreg2
0Fh
65h
11-xxx-xxx
short
meu
PCMPGTW mmreg, mem64
0Fh
65h
mm-xxx-xxx
short
mload, meu
PMADDWD mmreg1, mmreg2
0Fh
F5h
11-xxx-xxx
short
meu
PMADDWD mmreg, mem64
0Fh
F5h
mm-xxx-xxx
short
mload, meu
PMULHW mmreg1, mmreg2
0Fh
E5h
11-xxx-xxx
short
meu
PMULHW mmreg, mem64
0Fh
E5h
mm-xxx-xxx
short
mload, meu
PMULLW mmreg1, mmreg2
0Fh
D5h
11-xxx-xxx
short
meu
PMULLW mmreg, mem64
0Fh
D5h
mm-xxx-xxx
short
mload, meu
POR mmreg1, mmreg2
0Fh
EBh
11-xxx-xxx
short
meu
POR mmreg, mem64
0Fh
EBh
mm-xxx-xxx
short
mload, meu
PSLLD mmreg1, mmreg2
0Fh
F2h
11-xxx-xxx
short
meu
PSLLD mmreg, mem64
0Fh
F2h
mm-xxx-xxx
short
mload, meu
PSLLD mmreg, imm8
0Fh
72h
11-110-xxx
short
meu
PSLLQ mmreg1, mmreg2
0Fh
F3h
11-xxx-xxx
short
meu
PSLLQ mmreg, mem64
0Fh
F3h
mm-xxx-xxx
short
mload, meu
PSLLQ mmreg, imm8
0Fh
73h
11-110-xxx
short
meu
PSLLW mmreg1, mmreg2
0Fh
F1h
11-xxx-xxx
short
meu
PSLLW mmreg, mem64
0Fh
F1h
mm-xxx-xxx
short
mload, meu
PSLLW mmreg, imm8
0Fh
71h
11-110-xxx
short
meu
PSRAD mmreg1, mmreg2
0Fh
E2h
11-xxx-xxx
short
meu
PSRAD mmreg, mem64
0Fh
E2h
mm-xxx-xxx
short
mload, meu
PSRAD mmreg, imm8
0Fh
72h
11-100-xxx
short
meu
PSRAW mmreg1, mmreg2
0Fh
E1h
11-xxx-xxx
short
meu
PSRAW mmreg, mem64
0Fh
E1h
mm-xxx-xxx
short
mload, meu
PSRAW mmreg, imm8
0Fh
71h
11-100-xxx
short
meu
PSRLD mmreg1, mmreg2
0Fh
D2h
11-xxx-xxx
short
meu
Chapter 3
Software Environment
87
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 14. MMX™ Instructions (continued)
Prefix
Byte(s)
First
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
PSRLD mmreg, mem64
0Fh
D2h
mm-xxx-xxx
short
mload, meu
PSRLD mmreg, imm8
0Fh
72h
11-010-xxx
short
meu
PSRLQ mmreg1, mmreg2
0Fh
D3h
11-xxx-xxx
short
meu
PSRLQ mmreg, mem64
0Fh
D3h
mm-xxx-xxx
short
mload, meu
PSRLQ mmreg, imm8
0Fh
73h
11-010-xxx
short
meu
PSRLW mmreg1, mmreg2
0Fh
D1h
11-xxx-xxx
short
meu
PSRLW mmreg, mem64
0Fh
D1h
mm-xxx-xxx
short
mload, meu
PSRLW mmreg, imm8
0Fh
71h
11-010-xxx
short
meu
PSUBB mmreg1, mmreg2
0Fh
F8h
11-xxx-xxx
short
meu
PSUBB mmreg, mem64
0Fh
F8h
mm-xxx-xxx
short
mload, meu
PSUBD mmreg1, mmreg2
0Fh
FAh
11-xxx-xxx
short
meu
PSUBD mmreg, mem64
0Fh
FAh
mm-xxx-xxx
short
mload, meu
PSUBSB mmreg1, mmreg2
0Fh
E8h
11-xxx-xxx
short
meu
PSUBSB mmreg, mem64
0Fh
E8h
mm-xxx-xxx
short
mload, meu
PSUBSW mmreg1, mmreg2
0Fh
E9h
11-xxx-xxx
short
meu
PSUBSW mmreg, mem64
0Fh
E9h
mm-xxx-xxx
short
mload, meu
PSUBUSB mmreg1, mmreg2
0Fh
D8h
11-xxx-xxx
short
meu
PSUBUSB mmreg, mem64
0Fh
D8h
mm-xxx-xxx
short
mload, meu
PSUBUSW mmreg1, mmreg2
0Fh
D9h
11-xxx-xxx
short
meu
PSUBUSW mmreg, mem64
0Fh
D9h
mm-xxx-xxx
short
mload, meu
PSUBW mmreg1, mmreg2
0Fh
F9h
11-xxx-xxx
short
meu
PSUBW mmreg, mem64
0Fh
F9h
mm-xxx-xxx
short
mload, meu
PUNPCKHBW mmreg1, mmreg2
0Fh
68h
11-xxx-xxx
short
meu
PUNPCKHBW mmreg, mem64
0Fh
68h
mm-xxx-xxx
short
mload, meu
PUNPCKHDQ mmreg1, mmreg2
0Fh
6Ah
11-xxx-xxx
short
meu
PUNPCKHDQ mmreg, mem64
0Fh
6Ah
mm-xxx-xxx
short
mload, meu
PUNPCKHWD mmreg1, mmreg2
0Fh
69h
11-xxx-xxx
short
meu
PUNPCKHWD mmreg, mem64
0Fh
69h
mm-xxx-xxx
short
mload, meu
PUNPCKLBW mmreg1, mmreg2
0Fh
60h
11-xxx-xxx
short
meu
PUNPCKLBW mmreg, mem32
0Fh
60h
mm-xxx-xxx
short
mload, meu
PUNPCKLDQ mmreg1, mmreg2
0Fh
62h
11-xxx-xxx
short
meu
PUNPCKLDQ mmreg, mem32
0Fh
62h
mm-xxx-xxx
short
mload, meu
PUNPCKLWD mmreg1, mmreg2
0Fh
61h
11-xxx-xxx
short
meu
PUNPCKLWD mmreg, mem32
0Fh
61h
mm-xxx-xxx
short
mload, meu
PXOR mmreg1, mmreg2
0Fh
EFh
11-xxx-xxx
short
meu
Instruction Mnemonic
88
Software Environment
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 14. MMX™ Instructions (continued)
Instruction Mnemonic
PXOR mmreg, mem64
Prefix
Byte(s)
First
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
0Fh
EFh
mm-xxx-xxx
short
mload, meu
ModR/M
Byte
Decode
Type
RISC86
Operations
Notes:
1. Bits 2, 1, and 0 of the modR/M byte select the integer register.
Table 15. 3DNow!™ Instructions
Prefix
Byte(s)
Opcode
Byte
0Fh
0Eh
PAVGUSB mmreg1, mmreg2
0Fh, 0Fh
BFh
11-xxx-xxx
short
meu
PAVGUSB mmreg, mem64
0Fh, 0Fh
BFh
mm-xxx-xxx
short
mload, meu
PF2ID mmreg1, mmreg2
0Fh, 0Fh
1Dh
11-xxx-xxx
short
meu
PF2ID mmreg, mem64
0Fh, 0Fh
1Dh
mm-xxx-xxx
short
mload, meu
PFACC mmreg1, mmreg2
0Fh, 0Fh
AEh
11-xxx-xxx
short
meu
PFACC mmreg, mem64
0Fh, 0Fh
AEh
mm-xxx-xxx
short
mload, meu
PFADD mmreg1, mmreg2
0Fh, 0Fh
9Eh
11-xxx-xxx
short
meu
PFADD mmreg, mem64
0Fh, 0Fh
9Eh
mm-xxx-xxx
short
mload, meu
PFCMPEQ mmreg1, mmreg2
0Fh, 0Fh
B0h
11-xxx-xxx
short
meu
PFCMPEQ mmreg, mem64
0Fh, 0Fh
B0h
mm-xxx-xxx
short
mload, meu
PFCMPGE mmreg1, mmreg2
0Fh, 0Fh
90h
11-xxx-xxx
short
meu
PFCMPGE mmreg, mem64
0Fh, 0Fh
90h
mm-xxx-xxx
short
mload, meu
PFCMPGT mmreg1, mmreg2
0Fh, 0Fh
A0h
11-xxx-xxx
short
meu
PFCMPGT mmreg, mem64
0Fh, 0Fh
A0h
mm-xxx-xxx
short
mload, meu
PFMAX mmreg1, mmreg2
0Fh, 0Fh
A4h
11-xxx-xxx
short
meu
PFMAX mmreg, mem64
0Fh, 0Fh
A4h
mm-xxx-xxx
short
mload, meu
PFMIN mmreg1, mmreg2
0Fh, 0Fh
94h
11-xxx-xxx
short
meu
PFMIN mmreg, mem64
0Fh, 0Fh
94h
mm-xxx-xxx
short
mload, meu
PFMUL mmreg1, mmreg2
0Fh, 0Fh
B4h
11-xxx-xxx
short
meu
PFMUL mmreg, mem64
0Fh, 0Fh
B4h
mm-xxx-xxx
short
mload, meu
PFRCP mmreg1, mmreg2
0Fh, 0Fh
96h
11-xxx-xxx
short
meu
PFRCP mmreg, mem64
0Fh, 0Fh
96h
mm-xxx-xxx
short
mload, meu
PFRCPIT1 mmreg1, mmreg2
0Fh, 0Fh
A6h
11-xxx-xxx
short
meu
PFRCPIT1 mmreg, mem64
0Fh, 0Fh
A6h
mm-xxx-xxx
short
mload, meu
PFRCPIT2 mmreg1, mmreg2
0Fh, 0Fh
B6h
11-xxx-xxx
short
meu
PFRCPIT2 mmreg, mem64
0Fh, 0Fh
B6h
mm-xxx-xxx
short
mload, meu
PFRSQIT1 mmreg1, mmreg2
0Fh, 0Fh
A7h
11-xxx-xxx
short
meu
Instruction Mnemonic
FEMMS
Chapter 3
vector
Software Environment
89
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 15. 3DNow!™ Instructions (continued)
Instruction Mnemonic
Prefix
Byte(s)
Opcode
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
PFRSQIT1 mmreg, mem64
0Fh, 0Fh
A7h
mm-xxx-xxx
short
mload, meu
PFRSQRT mmreg1, mmreg2
0Fh, 0Fh
97h
11-xxx-xxx
short
meu
PFRSQRT mmreg, mem64
0Fh, 0Fh
97h
mm-xxx-xxx
short
mload, meu
PFSUB mmreg1, mmreg2
0Fh, 0Fh
9Ah
11-xxx-xxx
short
meu
PFSUB mmreg, mem64
0Fh, 0Fh
9Ah
mm-xxx-xxx
short
mload, meu
PFSUBR mmreg1, mmreg2
0Fh, 0Fh
AAh
11-xxx-xxx
short
meu
PFSUBR mmreg, mem64
0Fh, 0Fh
AAh
mm-xxx-xxx
short
mload, meu
PI2FD mmreg1, mmreg2
0Fh, 0Fh
0Dh
11-xxx-xxx
short
meu
PI2FD mmreg, mem64
0Fh, 0Fh
0Dh
mm-xxx-xxx
short
mload, meu
PMULHRW mmreg1, mmreg2
0Fh, 0Fh
B7h
11-xxx-xxx
short
meu
PMULHRW mmreg1, mem64
0Fh, 0Fh
B7h
mm-xxx-xxx
short
mload, meu
PREFETCH mem81
0Fh
0Dh
mm-000-xxx
vector
load
PREFETCHW mem81,2
0Fh
0Dh
mm-001-xxx
vector
load
Notes:
1. For PREFETCH and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be prefetched.
2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-2E+ processor, this instruction performs in the same manner as the PREFETCH instruction.
Table 16. 3DNow!™ Technology DSP Extensions
Instruction Mnemonic
Prefix
Byte(s)
Opcode
Byte
ModR/M
Byte
Decode
Type
PF2IW mmreg1, mmreg2
0Fh, 0Fh
1Ch
11-xxx-xxx
short
meu
PF2IW mmreg, mem64
0Fh, 0Fh
1Ch
mm-xxx-xxx
short
mload, meu
PFNACC mmreg1, mmreg2
0Fh, 0Fh
8Ah
11-xxx-xxx
short
meu
PFNACC mmreg, mem64
0Fh, 0Fh
8Ah
mm-xxx-xxx
short
mload, meu
PFPNACC mmreg1, mmreg2
0Fh, 0Fh
8Eh
11-xxx-xxx
short
meu
PFPNACC mmreg, mem64
0Fh, 0Fh
8Eh
mm-xxx-xxx
short
mload, meu
PI2FW mmreg1, mmreg2
0Fh, 0Fh
0Ch
11-xxx-xxx
short
meu
PI2FW mmreg, mem64
0Fh, 0Fh
0Ch
mm-xxx-xxx
short
mload, meu
PSWAPD mmreg1, mmreg2
0Fh, 0Fh
BBh
11-xxx-xxx
short
meu
PSWAPD mmreg, mem64
0Fh, 0Fh
BBh
mm-xxx-xxx
short
mload, meu
90
Software Environment
RISC86
Operations
Chapter 3
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
4
Logic Symbol Diagram
Voltage Detection2
Clock
CLK
Bus
Arbitration
Address
and
Address
Parity
Cycle
Definition
and
Control
Cache
Control
VID[4:0]
BF[2:0]
AHOLD
BOFF#
BREQ
HLDA
HOLD
A20M#
A[31:3]
AP
ADS#
ADSC#
APCHK#
BE[7:0]#
AMD-K6-2E+
Processor1
D/C#
EWBE#
LOCK#
M/IO#
NA#
SCYC
W/R#
CACHE#
KEN#
PCD
PWT
WB/WT#
TCK
TDI
TDO
VCC2DET VCC2H/L#
BRDY#
BRDYC#
D[63:0]
DP[7:0]
PCHK#
Data
and
Data
Parity
EADS#
HIT#
HITM#
INV
Inquire
Cycles
FERR#
IGNNE#
Floating-Point
Error Handling
FLUSH#
INIT
INTR
NMI
RESET
SMI#
SMIACT#
STPCLK#
External
Interrupts,
SMM, Reset and
Initialization
TMS TRST#
JTAG Test
Notes:
1. The signals are grouped by function. The arrows show the direction of the signal, either into or out of the processor. Signals with doubleheaded arrows are bidirectional. Signals with pound signs (#) are active Low.
2. The VID[4:0] outputs are supported on low-power versions only. The VCC2DET and VCC2H/L# outputs are supported on the CPGA
package only.
Chapter 4
Logic Symbol Diagram
91
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
92
Logic Symbol Diagram
23542A/0—September 2000
Chapter 4
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
5
Signal Descriptions
This chapter includes a detailed description of each signal
supported on the AMD-K6-2E+ processor. This chapter also
provides tables listing the signals grouped by type, beginning
on page 140.
The logic symbol diagram on page 91 shows the signals grouped
by function.
Connection diagrams and pins listed by high-level function are
included in Chapter 18, “Pin Designations” on page 321.
5.1
Signal Terminology
The following terminology is used in this chapter:
■
■
■
■
■
Chapter 5
Driven—The processor actively pulls the signal up to the
High-voltage state or pulls the signal down to the
Low-voltage state.
Floated—The signal is not being driven by the processor
(high-impedance state), which allows another device to
drive this signal.
Asserted—For all active High signals, the term asserted
means the signal is in the High-voltage state. For all active
Low signals, the term asserted means the signal is in the
Low-voltage state. See Table 19 on page 140 for information
on asserting signals synchronously and asynchronously.
Negated—For all active High signals, the term negated means
the signal is in the Low-voltage state. For all active Low
signals, the term negated means the signal is in the
High-voltage state.
Sampled—The processor has measured the state of a signal
at predefined points in time and will take the appropriate
action based on the state of the signal. If a signal is not
sampled by the processor, its assertion or negation has no
effect on the operation of the processor.
Signal Descriptions
93
Preliminary Information
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A20M# (Address Bit 20 Mask)
Pin Attribute
Input
Summary
A20M# is used to simulate the behavior of the 8086 when
running in Real mode. The assertion of A20M # causes the
processor to force bit 20 of the physical address to 0 prior to
accessing the caches or driving out a memory bus cycle. The
clearing of address bit 20 maps addresses that extend above the
8086 1-Mbyte limit to below 1 Mbyte.
Sampled
The processor samples A20M # as a level-sensitive input on
every clock edge. The system logic can drive the signal either
s y n ch ro n o u s ly o r a s y n ch ro n o u s ly. I f i t i s a s s e r t e d
asynchronously, it must be asserted for a minimum pulse width
of two clocks.
The following list explains the effects of the processor sampling
A20M# asserted under various conditions:
■
■
■
■
■
94
Inquire cycles and writeback cycles are not affected by the
state of A20M#.
The assertion of A20M# in System Management Mode
(SMM) is ignored.
When A20M# is sampled asserted in Protected mode, it
causes unpredictable processor operation. A20M# is only
defined in Real mode.
To ensure that A20M# is recognized before the first ADS#
occurs following the negation of RESET, A20M# must be
sampled asserted on the same clock edge that RESET is
sampled negated or on one of the two subsequent clock
edges.
To ensure A20M# is recognized before the execution of an
instruction, a serializing instruction must be executed
between the instruction that asserts A20M# and the
targeted instruction. (A serializing instruction is an
instruction inserted between operations to enforce program
order. It forces the processor to finish all modifications to
flags, registers, and memory before the next instruction is
executed.)
Signal Descriptions
Chapter 5
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
5.3
A[31:3] (Address Bus)
Pin Attribute
A[31:5] Bidirectional, A[4:3] Output
Summary
A[31:3] contain the physical address for the current bus cycle.
The processor drives addresses on A[31:3] during memory and
I/O cycles, and cycle definition information during special bus
cycles. The processor samples addresses on A[31:5] during
inquire cycles.
Driven, Sampled, and
Floated
As Outputs: A[31:3] are driven valid off the same clock edge as
ADS # and remain in the same state until the clock edge on
which NA# or the last expected BRDY# of the cycle is sampled
asserted. A[31:3] are driven during memory cycles, I/O cycles,
special bus cycles, and interrupt acknowledge cycles. The
processor continues to drive the address bus while the bus is
idle.
As Inputs: The processor samples A[31:5] during inquire cycles
on the clock edge on which EADS# is sampled asserted. Even
though A4 and A3 are not used during the inquire cycle, they
must be driven to a valid state and must meet the same timings
as A[31:5].
A[31:3] are floated off the clock edge that AHOLD or BOFF# is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD.
The processor resumes driving A[31:3] off the clock edge on
which the processor samples AHOLD or BOFF# negated and off
the clock edge on which the processor negates HLDA.
Chapter 5
Signal Descriptions
95
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
5.4
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ADS# (Address Strobe)
Pin Attribute
Output
Summary
The assertion of ADS # indicates the beginning of a new bus
cycle. The address bus and all cycle definition signals
corresponding to this bus cycle are driven valid off the same
clock edge as ADS#.
Driven and Floated
ADS # is asserted for one clock at the beginning of each bus
cycle. For non-pipelined cycles, ADS# can be asserted as early
as the clock edge after the clock edge on which the last
expected BRDY# of the cycle is sampled asserted, resulting in a
single idle state between cycles. For pipelined cycles if the
processor is prepared to start a new cycle, ADS# can be asserted
as early as one clock edge after NA# is sampled asserted.
If AHOLD is sampled asserted, ADS# is only driven in order to
perform a writeback cycle due to an inquire cycle that hits a
modified cache line.
The processor floats ADS # off the clock edge that BOFF # is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD.
5.5
ADSC# (Address Strobe Copy)
Pin Attribute
Output
Summary
ADSC # has the identical function and timing as ADS#. In the
event ADS# becomes too heavily loaded due to a large fanout in
a system, ADSC # can be used to split the load across two
outputs, which can improve system timing.
96
Signal Descriptions
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AMD-K6™-2E+ Embedded Processor Data Sheet
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5.6
AHOLD (Address Hold)
Pin Attribute
Input
Summary
AHOLD can be asserted by the system to initiate one or more
inquire cycles. To allow the system to drive the address bus
during an inquire cycle, the processor floats A[31:3] and AP off
the clock edge on which AHOLD is sampled asserted. The data
bus and all other control and status signals remain under the
control of the processor and are not floated. This allows a bus
cycle that is in progress when AHOLD is sampled asserted to
continue to completion. The processor resumes driving the
address bus off the clock edge on which AHOLD is sampled
negated.
If AHOLD is sampled asserted, ADS# is only asserted in order
to perform a writeback cycle due to an inquire cycle that hits a
modified cache line.
Sampled
Chapter 5
The processor samples AHOLD on every clock edge. AHOLD is
recognized while INIT and RESET are sampled asserted.
Signal Descriptions
97
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
5.7
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AP (Address Parity)
Pin Attribute
Bidirectional
Summary
AP contains the even parity bit for cache line addresses driven
and sampled on A[31:5]. Even parity means that the total
number of 1 bits on AP and A[31:5] is even. (A4 and A3 are not
used for the generation or checking of address parity because
these bits are not required to address a cache line.) AP is driven
by the processor during processor-initiated cycles and is
sampled by the processor during inquire cycles. If AP does not
reflect even parity during an inquire cycle, the processor
asserts APCHK # to indicate an address bus parity check. The
processor does not take an internal exception as the result of
detecting an address bus parity check, and system logic must
respond appropriately to the assertion of this signal.
Driven, Sampled, and
Floated
As an Output: The processor drives AP valid off the clock edge
on which ADS# is asserted until the clock edge on which NA# or
the last expected BRDY# of the cycle is sampled asserted. AP is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles. The processor continues to drive
AP while the bus is idle.
As an Input: The processor samples AP during inquire cycles on
the clock edge on which EADS# is sampled asserted.
The processor floats AP off the clock edge that AHOLD or
BOFF # is sampled asserted and off the clock edge that the
processor asserts HLDA in recognition of HOLD.
The processor resumes driving AP off the clock edge on which
the processor samples AHOLD or BOFF # negated and off the
clock edge on which the processor negates HLDA.
98
Signal Descriptions
Chapter 5
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
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5.8
APCHK# (Address Parity Check)
Pin Attribute
Output
Summary
If the processor detects an address parity error during an
inquire cycle, APCHK# is asserted for one clock. The processor
does not take an internal exception as the result of detecting an
address bus parity check, and system logic must respond
appropriately to the assertion of this signal.
The processor is designed so that APCHK # does not glitch,
enabling the signal to be used as a clocking source for system
logic.
Driven
APCHK# is driven valid off the clock edge after the clock edge
on which the processor samples EADS# asserted. It is negated
off the next clock edge.
APCHK# is always driven except in the Three-State Test mode.
Chapter 5
Signal Descriptions
99
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
5.9
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BE[7:0]# (Byte Enables)
Pin Attribute
Output
Summary
BE[7:0]# are used by the processor to indicate the valid data
bytes during a write cycle and the requested data bytes during
a read cycle. The byte enables can be used to derive address bits
A[2:0], which are not physically part of the processor’s address
bus. The processor checks and generates valid data parity for
the data bytes that are valid as defined by the byte enables. The
eight byte enables correspond to the eight bytes of the data bus
as follows:
■
■
■
■
BE7#: D[63:56]
BE6#: D[55:48]
BE5#: D[47:40]
BE4#: D[39:32]
■
■
■
■
BE3#: D[31:24]
BE2#: D[23:16]
BE1#: D[15:8]
BE0#: D[7:0]
The processor expects data to be driven by the system logic on
all eight bytes of the data bus during a burst cache-line read
cycle, independent of the byte enables that are asserted.
The byte enables are also used to distinguish between special
bus cycles as defined in Table 24 on page 142.
Driven and Floated
BE[7:0]# are driven off the same clock edge as ADS # and
remain in the same state until the clock edge on which NA# or
the last expected BRDY # of the cycle is sampled asserted.
BE[7:0]# are driven during memory cycles, I/O cycles, special
bus cycles, and interrupt acknowledge cycles.
The processor floats BE[7:0]# off the clock edge that BOFF# is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD. Unlike the address bus,
BE[7:0]# are not floated in response to AHOLD.
100
Signal Descriptions
Chapter 5
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
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5.10
BF[2:0] (Bus Frequency)
Pin Attribute
Inputs, Internal Pullups
Summary
BF[2:0] determine the internal operating frequency of the
processor. The frequency of the CLK input signal is multiplied
internally by a ratio determined by the state of these signals as
defined in Table 17. BF[2:0] have weak internal pullups and
default to the 3.5 multiplier if left unconnected.
Table 17. Processor-to-Bus Clock Ratios
Sampled
Chapter 5
State of BF[2:0] Inputs
Processor-Clock to Bus-Clock Ratio
100b
2.0x
101b
3.0x
110b
6.0x
111b
3.5x
000b
4.5x
001b
5.0x
010b
4.0x
011b
5.5x
BF[2:0] are sampled during the falling transition of RESET.
They must meet a minimum setup time of 1.0 ms and a
minimum hold time of two clocks relative to the negation of
RESET.
Signal Descriptions
101
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
5.11
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BOFF# (Backoff)
Pin Attribute
Input
Summary
If BOFF # is sampled asserted, the processor unconditionally
aborts any cycles in progress and transitions to a bus hold state
by floating the following signals: A[31:3], ADS #, ADSC #, AP,
BE[7:0]#, CACHE #, D[63:0], D/C #, DP[7:0], LOCK #, M/IO #,
PCD, PWT, SCYC, and W/R#. These signals remain floated until
BOFF# is sampled negated. This allows an alternate bus master
or the system to control the bus.
When BOFF# is sampled negated, any processor cycle that was
aborted due to the assertion of BOFF # is restarted from the
beginning of the cycle, regardless of the number of transfers
that were completed. If BOFF# is sampled asserted on the same
clock edge as BRDY# of a bus cycle of any length, then BOFF#
takes precedence over the BRDY #. In this case, the cycle is
aborted and restarted after BOFF# is sampled negated.
Sampled
BOFF# is sampled on every clock edge. The processor floats its
bus signals off the clock edge on which BOFF # is sampled
asserted. These signals remain floated until the clock edge on
which BOFF# is sampled negated.
BOFF # is recognized while INIT and RESET are sampled
asserted.
102
Signal Descriptions
Chapter 5
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AMD-K6™-2E+ Embedded Processor Data Sheet
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5.12
BRDY# (Burst Ready)
Pin Attribute
Input, Internal Pullup
Summary
BRDY# is asserted to the processor by system logic to indicate
either that the data bus is being driven with valid data during a
read cycle or that the data bus has been latched during a write
cycle. If necessary, the system logic can insert bus cycle wait
states by negating BRDY# until it is ready to continue the data
transfer. BRDY # is also used to indicate the completion of
special bus cycles.
Sampled
BRDY# is sampled every clock edge within a bus cycle starting
with the clock edge after the clock edge that negates ADS #.
BRDY# is ignored while the bus is idle. The processor samples
the following inputs on the clock edge on which BRDY # is
sampled asserted: D[63:0], DP[7:0], and KEN # during read
cycles, EWBE # during write cycles (if not masked off), and
WB/WT # during read and write cycles. If NA # is sampled
asserted prior to BRDY#, then KEN# and WB/WT# are sampled
on the clock edge on which NA# is sampled asserted.
The number of times the processor expects to sample BRDY #
asserted depends on the type of bus cycle, as follows:
■
■
One time for a single-transfer cycle, a special bus cycle, or
each of two cycles in an interrupt acknowledge sequence
Four times for a burst cycle (once for each data transfer)
BRDY # can be held asserted for four consecutive clocks
throughout the four transfers of the burst, or it can be negated
to insert wait states.
Chapter 5
Signal Descriptions
103
Preliminary Information
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BRDYC# (Burst Ready Copy)
Pin Attribute
Input, Internal Pullup
Summary
BRDYC # has the identical function as BRDY #. In the event
BRDY # becomes too heavily loaded due to a large fanout or
loading in a system, BRDYC # can be used to reduce this
loading, which improves timing.
Sampled
BRDYC# is sampled every clock edge within a bus cycle starting
with the clock edge after the clock edge that negates ADS#.
5.14
BREQ (Bus Request)
Pin Attribute
Output
Summary
BREQ is asserted by the processor to request the bus in order to
complete an internally pending bus cycle. The system logic can
use BREQ to arbitrate among the bus participants. If the
processor does not own the bus, BREQ is asserted until the
processor gains access to the bus in order to begin the pending
cycle or until the processor no longer needs to run the pending
cycle. If the processor currently owns the bus, BREQ is asserted
with ADS#. The processor asserts BREQ for each assertion of
ADS# but does not necessarily assert ADS# for each assertion of
BREQ.
Driven
BREQ is asserted off the same clock edge on which ADS # is
asserted. BREQ can also be asserted off any clock edge,
independent of the assertion of ADS#. BREQ can be negated
one clock edge after it is asserted.
The processor always drives BREQ except in the Three-State
Test mode.
104
Signal Descriptions
Chapter 5
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
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5.15
CACHE# (Cacheable Access)
Pin Attribute
Output
Summary
For reads, CACHE# is asserted to indicate the cacheability of
the current bus cycle. In addition, if the processor samples
KEN # assert ed, which indicates t he driven address is
cacheable, the cycle is a 32-byte burst read cycle. For write
cycles, CACHE# is asserted to indicate the current bus cycle is a
modified cache-line writeback. KEN # is ignored during
writebacks. If CACHE# is not asserted, or if KEN # is sampled
negated during a read cycle, the cycle is not cacheable and
defaults to a single-transfer cycle.
Driven and Floated
CACHE# is driven off the same clock edge as ADS# and remains
in the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
CACHE # is floated off the clock edge that BOFF # is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
5.16
CLK (Clock)
Pin Attribute
Input
Summary
The CLK signal is the bus clock for the processor and is the
reference for all signal timings under normal operation (except
for TDI, TDO, TMS, and TRST#). BF[2:0] determine the internal
frequency multiplier applied to CLK to obtain the processor’s
core operating frequency. See “BF[2:0] (Bus Frequency)” on
page 101 for a list of the processor-to-bus clock ratios.
Sampled
The CLK signal must be stable a minimum of 1.0 ms prior to the
negation of RESET to ensure the proper operation of the
processor. See “CLK Switching Characteristics” on page 296 for
details regarding the CLK specifications.
Chapter 5
Signal Descriptions
105
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
5.17
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D/C# (Data/Code)
Pin Attribute
Output
Summary
The processor drives D/C # during a memory bus cycle to
indicate whether it is addressing data or executable code. D/C#
is also used to define other bus cycles, including interrupt
acknowledge and special cycles. See Table 23 and Table 24 on
page 142 for more details.
Driven and Floated
D/C# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA # or the last
expected BRDY # of the cycle is sampled asserted. D/C # is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
D/C # is floated off the clock edge that BOFF # is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
106
Signal Descriptions
Chapter 5
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
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5.18
D[63:0] (Data Bus)
Pin Attribute
Bidirectional
Summary
D[63:0] represent the processor’s 64-bit data bus. Each of the
eight bytes of data that comprise this bus is qualified as valid
by its corresponding byte enable. See “BE[7:0]# (Byte
Enables)” on page 100.
Driven, Sampled, and
Floated
As Outputs: For single-transfer write cycles, the processor drives
D[63:0] with valid data one clock edge after the clock edge on
which ADS# is asserted and D[63:0] remain in the same state
until the clock edge on which BRDY# is sampled asserted. If the
cycle is a writeback—in which case four 8-byte transfers
occur—D[63:0] are driven one clock edge after the clock edge
on which ADS# is asserted and are subsequently changed off
the clock edge on which each BRDY# assertion of the burst
cycle is sampled.
If the assertion of ADS# represents a pipelined write cycle that
follows a read cycle, the processor does not drive D[63:0] until it
is certain that contention on the data bus will not occur. In this
case, D[63:0] are driven the clock edge after the last expected
BRDY# of the previous cycle is sampled asserted.
As Inputs: During read cycles, the processor samples D[63:0] on
the clock edge on which BRDY# is sampled asserted.
The processor always floats D[63:0] except when they are being
driven during a write cycle as described above. In addition,
D[63:0] are floated off the clock edge that BOFF # is sampled
asserted and off the clock edge that the processor asserts
HLDA in recognition of HOLD.
Chapter 5
Signal Descriptions
107
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DP[7:0] (Data Parity)
Pin Attribute
Bidirectional
Summary
DP[7:0] are even parity bits for each valid byte of data — as
defined by BE[7:0]#—driven and sampled on the D[63:0] data
bus. Even parity means that the total number of 1 bits within
each byte of data and its respective data parity bit is an even
number. DP[7:0] are driven by the processor during write cycles
and sampled by the processor during read cycles.
If the processor detects bad parity on any valid byte of data
during a read cycle, PCHK# is asserted for one clock beginning
the clock edge after BRDY# is sampled asserted. The processor
does not take an internal exception as the result of detecting a
data parity check, and system logic must respond appropriately
to the assertion of this signal.
The eight data parity bits correspond to the eight bytes of the
data bus as follows:
■
■
■
■
DP7: D[63:56]
DP6: D[55:48]
DP5: D[47:40]
DP4: D[39:32]
■
■
■
■
DP3: D[31:24]
DP2: D[23:16]
DP1: D[15:8]
DP0: D[7:0]
For systems that do not support data parity, DP[7:0] should be
connected to VCC3 through pullup resistors.
Driven, Sampled, and
Floated
As Outputs: For single-transfer write cycles, the processor drives
DP[7:0] with valid parity one clock edge after the clock edge on
which ADS# is asserted and DP[7:0] remain in the same state
until the clock edge on which BRDY# is sampled asserted. If the
cycle is a writeback, DP[7:0] are driven one clock edge after the
clock edge on which ADS# is asserted and are subsequently
changed off the clock edge on which each BRDY# assertion of
the burst cycle is sampled.
As Inputs: During read cycles, the processor samples DP[7:0] on
the clock edge BRDY# is sampled asserted.
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The processor always floats DP[7:0] except when they are being
driven during a write cycle as described above. In addition,
DP[7:0] are floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts
HLDA in recognition of HOLD.
5.20
EADS# (External Address Strobe)
Pin Attribute
Input
Summary
System logic asserts EADS # during a cache inquire cycle to
indicate that the address bus contains a valid address. EADS#
can only be driven after the system logic has taken control of
the address bus by asserting AHOLD or BOFF# or by receiving
HLDA. The processor responds to the sampling of EADS# and
the address bus by driving HIT#, which indicates if the inquired
cache line exists in the processor’s caches, and HITM #, which
indicates if it is in the modified state.
Sampled
If AHOLD or BOFF# is asserted by the system logic in order to
execute a cache inquire cycle, the processor begins sampling
EADS # two clock edges after AHOLD or BOFF # is sampled
asserted. If the system logic asserts HOLD in order to execute a
cache inquire cycle, the processor begins sampling EADS# two
clock edges after the clock edge HLDA is asserted by the
processor.
EADS# is ignored during the following conditions:
■
■
■
■
Chapter 5
One clock edge after the clock edge on which EADS# is
sampled asserted
Two clock edges after the clock edge on which ADS# is
asserted
When the processor is driving the address bus
When the processor asserts HITM#
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EWBE# (External Write Buffer Empty)
Pin Attribute
Input
Summary
The system logic can negate EWBE# to the processor to indicate
that its external write buffers are full and that additional data
cannot be stored at this time. This causes the processor to delay
the following activities until EWBE# is sampled asserted:
■
■
■
■
The commitment of write hit cycles to cache lines in the
modified state or exclusive state in the processor’s caches
The decode and execution of an instruction that follows a
currently-executing serializing instruction
The assertion or negation of SMIACT#
The entering of the Halt state and the Stop Grant state
Negating EWBE# does not prevent the completion of any type
of cycle that is currently in progress.
Sampled
The processor samples EWBE# on each clock edge that BRDY#
is sampled asserted during all memory write cycles (except
writeback cycles), I/O write cycles, and special bus cycles.
If EWBE# is sampled negated, it is sampled on every clock edge
until it is asserted, and then it is ignored until BRDY # is
sampled asserted in the next write cycle or special cycle.
If EFER[3] is set to 1, then EWBE# is ignored by the processor.
For more information on the EFER settings and EWBE#, see
“EWBE# Control” on page 229.
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5.22
FERR# (Floating-Point Error)
Pin Attribute
Output
Summary
The assertion of FERR # indicates the occurrence of an
unmasked floating-point exception resulting from the
execution of a floating-point instruction. This signal is provided
to allow the system logic to handle this exception in a manner
consistent with IBM-compatible PC/AT systems. See “Handling
Floating-Point Exceptions” on page 237 for a system logic
implementation that supports floating-point exceptions.
The state of the numeric error (NE) bit in CR0 does not affect
the FERR# signal.
The processor is designed so that FERR # does not glitch,
enabling the signal to be used as a clocking source for system
logic.
Driven
The processor asserts FERR # on the instruction boundary of
the next floating-point instruction, MMX instruction, 3DNow!
instruction, or WAIT instruction that occurs following the
f l o a t i ng -po i nt i ns t r u c t i o n t h a t c a u s e d t h e u n m a s ke d
floating-point exception—that is, FERR# is not asserted at the
time the exception occurs. The IGNNE# signal does not affect
the assertion of FERR#.
FERR# is negated during the following conditions:
■
■
■
Following the successful execution of the floating-point
instructions FCLEX, FINIT, FSAVE, and FSTENV
Under certain circumstances, following the successful
execution of the floating-point instructions FLDCW,
FLDENV, and FRSTOR, which load the floating-point status
word or the floating-point control word
Following the falling transition of RESET
FERR# is always driven except in the Three-State Test mode.
See “IGNNE# (Ignore Numeric Exception)” on page 116 for
more details on floating-point exceptions.
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FLUSH# (Cache Flush)
Pin Attribute
Input
Summary
In response to sampling FLUSH# asserted, the processor writes
back any cache lines in the L1 data cache or L2 cache that are in
the modified state, invalidates all lines in the L1 and L2 caches,
and then executes a flush acknowledge special cycle. See
Table 24 on page 142 for the bus definition of special cycles.
In addition, FLUSH # is sampled when RESET is negated to
determine if the processor enters the Three-State Test mode. If
FLUSH # is 0 during the falling transition of RESET, the
processor enters the Three-State Test mode instead of
performing the normal RESET functions.
Sampled
FLUSH # is sampled and latched as a falling edge-sensitive
signal. During normal operation (not RESET), FLUSH # is
sampled on every clock edge but is not recognized until the next
instruction boundary.
■
■
If FLUSH# is asserted synchronously (see Table 19 on
page 140), it can be asserted for a minimum of one clock.
If FLUSH# is asserted asynchronously, it must have been
negated for a minimum of two clocks, followed by an
assertion of a minimum of two clocks.
FLUSH# is also sampled during the falling transition of RESET.
If RESET and FLUSH# are driven synchronously, FLUSH# is
sampled on the clock edge prior to the clock edge on which
RESET is sampled negated. If RESET is driven asynchronously,
the minimum setup and hold time for FLUSH#, relative to the
negation of RESET, is two clocks.
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5.24
HIT# (Inquire Cycle Hit)
Pin Attribute
Output
Summary
The processor asserts HIT# during an inquire cycle to indicate
that the cache line is valid within the processor’s L1 and/or L2
caches (also known as a cache hit). The cache line can be in the
modified, exclusive, or shared state.
Driven
HIT# is always driven—except in the Three-State Test mode—
and only changes state the clock edge after the clock edge on
which EADS# is sampled asserted. It is driven in the same state
until the next inquire cycle.
5.25
HITM# (Inquire Cycle Hit To Modified Line)
Pin Attribute
Output
Summary
The processor asserts HITM # during an inquire cycle to
indicate that the cache line exists in the processor’s L1 data
cache or L2 cache in the modified state. The processor performs
a writeback cycle as a result of this cache hit. If an inquire cycle
hits a cache line that is currently being written back, the
processor asserts HITM # but does not execute another
writeback cycle. The system logic must not expect the processor
to assert ADS# each time HITM# is asserted.
Driven
HITM # is always driven — except in the Three-State Test
mode—and, in particular, is driven to represent the result of an
inquire cycle the clock edge after the clock edge on which
EADS# is sampled asserted. If HITM# is negated in response to
the inquire address, it remains negated until the next inquire
cycle. If HITM# is asserted in response to the inquire address, it
remains asserted throughout the writeback cycle and is negated
one clock edge after the last BRDY # of the writeback is
sampled asserted.
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HLDA (Hold Acknowledge)
Pin Attribute
Output
Summary
When HOLD is sampled asserted, the processor completes the
current bus cycles, floats the processor bus, and asserts HLDA
in an acknowledgment that these events have been completed.
The processor does not assert HLDA until the completion of a
locked sequence of cycles. While HLDA is asserted, another bus
master can drive cycles on the bus, including inquire cycles to
the processor. The following signals are floated when HLDA is
asserted: A[31:3], ADS #, ADSC #, AP, BE[7:0]#, CACHE #,
D[63:0], D/C#, DP[7:0], LOCK #, M/IO#, PCD, PWT, SCYC, and
W/R#.
The processor is designed so that HLDA does not glitch.
Driven
HLDA is always driven except in the Three-State Test mode. If a
processor cycle is in progress while HOLD is sampled asserted,
HLDA is asserted one clock edge after the last BRDY # of the
cycle is sampled asserted. If the bus is idle, HLDA is asserted
one clock edge after HOLD is sampled asserted. HLDA is
negated one clock edge after the clock edge on which HOLD is
sampled negated.
The assertion of HLDA is independent of the sampled state of
BOFF#.
The processor floats the bus every clock in which HLDA is
asserted.
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5.27
HOLD (Bus Hold Request)
Pin Attribute
Input
Summary
The system logic can assert HOLD to gain control of the
processor’s bus. When HOLD is sampled asserted, the processor
completes the current bus cycles, floats the processor bus, and
asserts HLDA in an acknowledgment that these events have
been completed.
Sampled
The processor samples HOLD on every clock edge. If a
processor cycle is in progress while HOLD is sampled asserted,
HLDA is asserted one clock edge after the last BRDY # of the
cycle is sampled asserted. If the bus is idle, HLDA is asserted
one clock edge after HOLD is sampled asserted. HOLD is
recognized while INIT and RESET are sampled asserted.
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IGNNE# (Ignore Numeric Exception)
Pin Attribute
Input
Summary
IGNNE#, in conjunction with the numeric error (NE) bit in the
CR0 register, is used by the system logic to control the effect of
a n u n m a s ke d f l o a t i n g -p o i n t ex c e p t i o n o n a p rev i o u s
f l o a t i n g -p o i n t i n s t r u c t i o n d u r i n g t h e ex e c u t i o n o f a
f l oa t i n g -po i n t i n st r u c ti on , MMX i n st r u c t i on , 3D N ow !
instruction, or the WAIT instruction—hereafter referred to as
the target instruction.
If an unmasked floating-point exception is pending and the
target instruction is considered error-sensitive, then the
relationship between NE and IGNNE# is as follows:
■
If NE = 0, then:
•
If IGNNE# is sampled asserted, the processor ignores the
floating-point exception and continues with the
execution of the target instruction.
If IGNNE# is sampled negated, the processor waits until
it samples IGNNE#, INTR, SMI#, NMI, or INIT asserted.
• If IGNNE# is sampled asserted while waiting, the
processor ignores the floating-point exception and
continues with the execution of the target
instruction.
• If INTR, SMI#, NMI, or INIT is sampled asserted
while waiting, the processor handles its assertion
appropriately.
If NE = 1, the processor invokes the INT 10h exception
handler.
•
■
If an unmasked floating-point exception is pending and the
target instruction is considered error-insensitive, then the
processor ignores the floating-point exception and continues
with the execution of the target instruction.
FERR # is not affected by the state of the NE bit or IGNNE #.
FERR # is always asserted at the instruction boundary of the
target instruction that follows the floating-point instruction
that caused the unmasked floating-point exception.
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This signal is provided to allow the system logic to handle
exceptions in a manner consistent with IBM-compatible PC/AT
systems.
Sampled
5.29
The processor samples IGNNE # as a level-sensitive input on
every clock edge. The system logic can drive the signal either
s y n ch ro n o u s ly o r a s y n ch ro n o u s ly. I f i t i s a s s e r t e d
asynchronously, it must be asserted for a minimum pulse width
of two clocks.
INIT (Initialization)
Pin Attribute
Input
Summary
The assertion of INIT causes the processor to empty its
pipelines, to initialize most of its internal state, and to branch
to address FFFF_FFF0h—the same instruction execution
starting point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the floating-point state, the
MMX state, Model-Specific Registers, the CD and NW bits of
the CR0 register, and other specific internal resources.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from Protected mode back to Real mode.
Sampled
INIT is sampled and latched as a rising edge-sensitive signal.
INIT is sampled on every clock edge but is not recognized until
the next instruction boundary. During an I/O write cycle, it must
be sampled asserted a minimum of three clock edges before
BRDY # is sampled asserted if it is to be recognized on the
boundary between the I/O write instruction and the following
instruction.
■
■
Chapter 5
If INIT is asserted synchronously (see Table 19 on page 140),
it can be asserted for a minimum of one clock.
If it is asserted asynchronously, it must have been negated
for a minimum of two clocks, followed by an assertion of a
minimum of two clocks.
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INTR (Maskable Interrupt)
Pin Attribute
Input
Summary
INTR is the system’s maskable interrupt input to the processor.
When the processor samples and recognizes INTR asserted, the
processor executes a pair of interrupt acknowledge bus cycles
and then jumps to the interrupt service routine specified by the
interrupt number that was returned during the interrupt
acknowledge sequence. The processor only recognizes INTR if
the interrupt flag (IF) in the EFLAGS register equals 1.
Sampled
The processor samples INTR as a level-sensitive input on every
clock edge, but the interrupt request is not recognized until the
next instruction boundary. The system logic can drive INTR
either synchronously or asynchronously. If it is asserted
asynchronously, it must be asserted for a minimum pulse width
of two clocks. In order to be recognized, INTR must remain
asserted until an interrupt acknowledge sequence is complete.
5.31
INV (Invalidation Request)
Pin Attribute
Input
Summary
During an inquire cycle, the state of INV determines whether
an addressed cache line that is found in the processor’s L1
and/or L2 caches transitions to the invalid state or the shared
state.
If INV is sampled asserted during an inquire cycle, the
processor transitions the cache line (if found) to the invalid
state, regardless of its previous state. If INV is sampled negated
during an inquire cycle, the processor transitions the cache line
(if found) to the shared state. In either case, if the cache line is
found in the modified state, the processor writes it back to
memory before changing its state.
Sampled
118
INV is sampled on the clock edge on which EADS# is sampled
asserted.
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5.32
KEN# (Cache Enable)
Pin Attribute
Input
Summary
If KEN # is sampled asserted, it indicates that the address
presented by the processor is cacheable. If KEN # is sampled
asserted and the processor intends to perform a cache-line fill
(signified by the assertion of CACHE#), the processor executes
a 32-byte burst read cycle and expects to sample BRDY #
asserted a total of four times. If KEN # is sampled negated
during a read cycle, a single-transfer cycle is executed and the
processor does not cache the data. For write cycles, CACHE# is
asserted to indicate the current bus cycle is a modified
cache-line writeback. KEN# is ignored during writebacks.
If PCD is asserted during a bus cycle, the processor does not
cache any data read during that cycle, regardless of the state of
KEN#. See “PCD (Page Cache Disable)” on page 124 for more
details.
If the processor has sampled the state of KEN# during a cycle,
and that cycle is aborted due to the sampling of BOFF #
asserted, the system logic must ensure that KEN# is sampled in
the same state when the processor restarts the aborted cycle.
Sampled
Chapter 5
KEN# is sampled on the clock edge on which the first BRDY# or
NA # of a read cycle is sampled asserted. If the read cycle is a
burst, KEN # is ignored during the last three assertions of
BRDY #. KEN # is sampled during read cycles only when
CACHE# is asserted.
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LOCK# (Bus Lock)
Pin Attribute
Output
Summary
The processor asserts LOCK# during a sequence of bus cycles to
ensure that the cycles are completed without allowing other bus
masters to intervene. Locked operations consist of two to five
bus cycles. LOCK# is asserted during the following operations:
■
An interrupt acknowledge sequence
Descriptor Table accesses
Page Directory and Page Table accesses
XCHG instruction
■
An instruction with an allowable LOCK prefix
■
■
■
In order to ensure that locked operations appear on the bus and
are visible to the entire system, any data operands addressed
during a locked cycle that reside in the processor’s caches are
flushed and invalidated from the caches prior to the locked
operation. If the cache line is in the modified state, it is written
back and invalidated prior to the locked operation. Likewise,
any data read during a locked operation is not cached.
The processor is designed so that LOCK# does not glitch.
Driven and Floated
During a locked cycle, LOCK# is asserted off the same clock
edge on which ADS# is asserted and remains asserted until the
last BRDY# of the last bus cycle is sampled asserted. The
processor negates LOCK# for at least one clock between
consecutive sequences of locked operations to allow the system
logic to arbitrate for the bus.
LOCK# is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD. When LOCK# is floated due to BOFF#
sampled asserted, the system logic is responsible for preserving
the lock condition while LOCK# is in the high-impedance state.
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5.34
M/IO# (Memory or I/O)
Pin Attribute
Output
Summary
The processor drives M/IO# during a bus cycle to indicate
whether it is addressing the memory or I/O space. If M/IO# = 1,
the processor is addressing memory or a memory-mapped I/O
port as the result of an instruction fetch or an instruction that
loads or stores data. If M/IO# = 0, the processor is addressing an
I/O port during the execution of an I/O instruction. In addition,
M/IO# is used to define other bus cycles, including interrupt
acknowledge and special cycles. See Table 23 and Table 24 on
page 142 for more details.
Driven and Floated
M/IO# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted. M/IO# is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
M/IO# is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
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NA# (Next Address)
Pin Attribute
Input
Summary
System logic asserts NA# to indicate to the processor that it is
ready to accept another bus cycle pipelined into the previous
bus cycle. ADS#, along with address and status signals, can be
asserted as early as one clock edge after NA# is sampled
asserted if the processor is prepared to start a new cycle.
Because the processor allows a maximum of two cycles to be in
progress at a time, the assertion of NA# is sampled while two
cycles are in progress, but ADS# is not asserted until the
completion of the first cycle.
Sampled
NA# is sampled every clock edge during bus cycles, starting one
clock edge after the clock edge that negates ADS#, until the last
expected BRDY# of the last executed cycle is sampled asserted
(with the exception of the clock edge after the clock edge that
negates the ADS# for a second pending cycle). Because the
processor latches NA# when sampled, the system logic only
needs to assert NA# for one clock.
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5.36
NMI (Non-Maskable Interrupt)
Pin Attribute
Input
Summary
When NMI is sampled asserted, the processor jumps to the
interrupt service routine defined by interrupt number 02h.
Unlike the INTR signal, software cannot mask the effect of NMI
if it is sampled asserted by the processor. However, NMI is
temporarily masked upon entering System Management Mode
(SMM). In addition, an interrupt acknowledge cycle is not
executed because the interrupt number is predefined.
If NMI is sampled asserted while the processor is executing the
interrupt service routine for a previous NMI, the subsequent
NMI remains pending until the completion of the execution of
the IRET instruction at the end of the interrupt service routine.
Sampled
NMI is sampled and latched as a rising edge-sensitive signal.
During normal operation, NMI is sampled on every clock edge
but is not recognized until the next instruction boundary.
■
■
Chapter 5
If NMI is asserted synchronously (see Table 19 on page 140),
it can be asserted for a minimum of one clock.
If NMI is asserted asynchronously, it must have been
negated for a minimum of two clocks, followed by an
assertion of a minimum of two clocks.
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PCD (Page Cache Disable)
Pin Attribute
Output
Summary
The processor drives PCD to indicate the operating system’s
specification of cacheability for the page being addressed.
System logic can use PCD to control external caching. If PCD is
asserted, the addressed page is not cached. If PCD is negated,
the cacheability of the addressed page depends upon the state
of CACHE# and KEN#.
The state of PCD depends upon the processor’s operating mode
and the state of certain bits in its control registers and TLB as
follows:
■
■
Driven and Floated
In Real mode, or in Protected and Virtual-8086 modes while
paging is disabled (PG bit in CR0 set to 0):
PCD output = CD bit in CR0
In Protected and Virtual-8086 modes while caching is
enabled (CD bit in CR0 set to 0) and paging is enabled (PG
bit in CR0 set to 1):
•
For accesses to I/O space, page directory entries, and
other non-paged accesses:
PCD output = PCD bit in CR3
•
For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PCD output = PCD bit in page directory entry
•
For accesses to 4-Kbyte pages:
PCD output = PCD bit in page table entry
PCD is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
PCD is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
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5.38
PCHK# (Parity Check)
Pin Attribute
Output
Summary
The processor asserts PCHK# during read cycles if it detects an
even parity error on one or more valid bytes of D[63:0] during a
read cycle. (Even parity means that the total number of 1 bits
within each byte of data and its respective data parity bit is
even.) The processor checks data parity for the data bytes that
are valid, as defined by BE[7:0]#, the byte enables.
PCHK# is always driven but is only asserted for memory and I/O
re a d b u s cy c l es a n d t he se c o n d cy c l e of a n i n t e r ru p t
acknowledge sequence. PCHK# is not driven during any type of
write cycles or special bus cycles. The processor does not take
an internal exception as the result of detecting a data parity
error, and system logic must respond appropriately to the
assertion of this signal.
The processor is designed so that PCHK# does not glitch,
enabling the signal to be used as a clocking source for system
logic.
Driven
Chapter 5
PCHK# is always driven except in the Three-State Test mode.
For each BRDY# returned to the processor during a read cycle
with a parity error detected on the data bus, PCHK# is asserted
for one clock, one clock edge after BRDY# is sampled asserted.
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PWT (Page Writethrough)
Pin Attribute
Output
Summary
The processor drives PWT to indicate the operating system’s
specification of the writeback state or writethrough state for
the page being addressed. PWT, together with WB/WT#,
specifies the data cache-line state during cacheable read misses
and write hits to shared cache lines. See “WB/WT# (Writeback
or Writethrough)” on page 139 for more details.
The state of PWT depends upon the processor’s operating mode
and the state of certain bits in its control registers and TLB as
follows:
■
■
Driven and Floated
In Real mode, or in Protected and Virtual-8086 modes while
paging is disabled (PG bit in CR0 set to 0):
PWT output = 0 (writeback state)
In Protected and Virtual-8086 modes while paging is
enabled (PG bit in CR0 set to 1):
•
For accesses to I/O space, page directory entries, and
other non-paged accesses:
PWT output = PWT bit in CR3
•
For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PWT output = PWT bit in page directory entry
•
For accesses to 4-Kbyte pages:
PWT output = PWT bit in page table entry
PWT is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
PWT is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge on which the processor asserts
HLDA in response to HOLD.
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5.40
RESET (Reset)
Pin Attribute
Input
Summary
When the processor samples RESET asserted, it immediately
flushes and initializes all internal resources and its internal
state including its pipelines and caches, the floating-point
state, the MMX state, the 3DNow! state, and all registers, and
then the processor jumps to address FFFF_FFF0h to start
instruction execution.
The FLUSH# signal is sampled during the falling transition of
RESET to invoke the Three-State Test mode.
Sampled
RESET is sampled as a level-sensitive input on every clock
edge. System logic can drive the signal either synchronously or
asynchronously.
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and VCC
reach specification before it is negated.
During a warm reset, while CLK and V CC are within their
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
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RSVD (Reserved)
Pin Attribute
Not Applicable
Summary
Reserved signals are a special class of pins that can be treated
in one of the following ways:
■
■
■
As no-connect (NC) pins, in which case these pins are left
unconnected
As pins connected to the system logic as defined by the
industry-standard Super7 and Socket 7 interface
Any combination of NC and Socket 7 pins
In any case, if the RSVD pins are treated accordingly, the
normal operation of the AMD-K6-2E+ processor is not adversely
affected in any manner.
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5.42
SCYC (Split Cycle)
Pin Attribute
Output
Summary
The processor asserts SCYC during misaligned, locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
For purposes of bus cycles, the term aligned means:
■
Any 1-byte transfers
2-byte and 4-byte transfers that lie within 4-byte address
boundaries
■
8-byte transfers that lie within 8-byte address boundaries
■
Driven and Floated
SCYC is asserted off the same clock edge as ADS#, and negated
off the clock edge on which NA# or the last expected BRDY# of
the entire locked sequence is sampled asserted. SCYC is only
valid during locked memory cycles.
SCYC is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
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SMI# (System Management Interrupt)
Pin Attribute
Input, Internal Pullup
Summary
The assertion of SMI# causes the processor to enter System
Management Mode (SMM). Upon recognizing SMI#, the
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycles
3. Acknowledges the interrupt by asserting SMIACT# after
sampling EWBE# asserted (if EWBE# is masked off, then
SMIACT# is not affected by EWBE#)
4. Saves the internal processor state in SMM memory
5. Disables interrupts by clearing the interrupt flag (IF) in
EFLAGS and disables NMI interrupts
6. Jumps to the entry point of the SMM service routine at the
SMM base physical address, which defaults to 0003_8000h
in SMM memory
See “System Management Mode (SMM)” on page 241 for more
details regarding SMM.
Sampled
SMI# is sampled and latched as a falling edge-sensitive signal.
SMI# is sampled on every clock edge but is not recognized until
the next instruction boundary. If SMI# is to be recognized on
the instruction boundary associated with a BRDY#, it must be
sampled asserted a minimum of three clock edges before the
BRDY# is sampled asserted.
■
■
If SMI# is asserted synchronously (see Table 19 on
page 140), it can be asserted for a minimum of one clock.
If SMI# is asserted asynchronously, it must have been
negated for a minimum of two clocks followed by an
assertion of a minimum of two clocks.
A second assertion of SMI# while in SMM is latched but is not
recognized until the SMM service routine is exited.
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5.44
SMIACT# (System Management Interrupt Active)
Pin Attribute
Output
Summary
The processor acknowledges the assertion of SMI# with the
assertion of SMIACT# to indicate that the processor has
entered System Management Mode (SMM). The system logic
can use SMIACT# to enable SMM memory. See “SMI# (System
Management Interrupt)” on page 130 for more details.
See “System Management Mode (SMM)” on page 241 for more
details regarding SMM.
Driven
The processor asserts SMIACT# after the last BRDY# of the last
pending bus cycle is sampled asserted (including all pending
write cycles) and after EWBE# is sampled asserted (if EWBE#
is masked off, then SMIACT# is not affected by EWBE#).
SMIACT# remains asserted until after the last BRDY# of the
last pending bus cycle associated with exiting SMM is sampled
asserted.
SMIACT# remains asserted during any flush, internal snoop, or
writeback cycle due to an inquire cycle.
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STPCLK# (Stop Clock)
Pin Attribute
Input, Internal Pullup
Summary
The assertion of STPCLK# causes the processor to enter the
Stop Grant state, during which the processor’s internal clock is
stopped. From the Stop Grant state, the processor can
subsequently transition to the Stop Clock state, in which the
bus clock CLK is stopped. Upon recognizing STPCLK#, the
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycles
3. Acknowledges the STPCLK# assertion by executing a Stop
Grant special bus cycle (see Table 24 on page 142)
4. Stops its internal clock after BRDY# of the Stop Grant
special bus cycle is sampled asserted and after EWBE# is
sampled asserted (if EWBE# is masked off, then entry into
the Stop Grant state is not affected by EWBE#)
5. Enters the Stop Clock state if the system logic stops the bus
clock CLK (optional)
See “Clock Control” on page 275 for more details regarding
clock control.
Sampled
STPCLK# is sampled as a level-sensitive input on every clock
edge but is not recognized until the next instruction boundary.
System logic can drive the signal either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks.
STPCLK# must remain asserted until recognized, which is
indicated by the completion of the Stop Grant special cycle.
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5.46
TCK (Test Clock)
Pin Attribute
Input, Internal Pullup
Summary
TCK is the clock for boundary-scan testing using the Test
Access Port (TAP). See “Boundary-Scan Test Access Port
(TAP)” on page 253 for details regarding the operation of the
TAP controller.
Sampled
The processor always samples TCK, except while TRST# is
asserted.
5.47
TDI (Test Data Input)
Pin Attribute
Input, Internal Pullup
Summary
T D I i s t h e s e r i a l t e s t d a t a a n d i n s t r u c t i o n i n p u t fo r
boundary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 253 for
details regarding the operation of the TAP controller.
Sampled
The processor samples TDI on every rising TCK edge, but only
while in the Shift-IR and Shift-DR states.
5.48
TDO (Test Data Output)
Pin Attribute
Output
Summary
TDO is the serial test data and instruction out put for
boundary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 253 for
details regarding the operation of the TAP controller.
Driven and Floated
The processor drives TDO on every falling TCK edge, but only
while in the Shift-IR and Shift-DR states. TDO is floated at all
other times.
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TMS (Test Mode Select)
Pin Attribute
Input, Internal Pullup
Summary
TMS specifies the test function and sequence of state changes
for boundary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 253 for
details regarding the operation of the TAP controller.
Sampled
The processor samples TMS on every rising TCK edge. If TMS is
sampled High for five or more consecutive clocks, the TAP
controller enters its Test-Logic-Reset state, regardless of the
controller state. This action is the same as that achieved by
asserting TRST#.
5.50
TRST# (Test Reset)
Pin Attribute
Input, Internal Pullup
Summary
The assertion of TRST# initializes the Test Access Port (TAP) by
resetting its state machine to the Test-Logic-Reset state. See
“Boundary-Scan Test Access Port (TAP)” on page 253 for
details regarding the operation of the TAP controller.
Sampled
TRST# is a completely asynchronous input that does not
require a minimum setup and hold time relative to TCK. See
Ta b l e 7 0 o n p a g e 3 0 8 f o r t h e m i n i m u m p u l s e w i d t h
requirement.
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5.51
VCC2DET (VCC2 Detect)
Pin Attribute
Output (supported on the CPGA package only)
Summary
VCC2DET is internally tied to VSS (logic level 0) to indicate to
the system logic that it must supply the specified dual-voltage
requirements to the VCC2 and VCC3 pins. The VCC2 pins supply
voltage to the processor core, independent of the voltage
supplied to the I/O buffers on the V CC3 pins. Upon sampling
VCC2DET Low, system logic should sample VCC2H/L# to
identify core voltage requirements
Note that this pin is not supported on the OBGA package.
Driven
Chapter 5
VCC2DET always equals 0 and is never floated—even during
the Three-State Test mode.
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VCC2H/L# (VCC2 High/Low)
Pin Attribute
Output (supported on the CPGA package only)
Summary
VCC2H/L# is internally tied to VSS (logic level 0) to indicate to
the system logic that it must supply the specified processor core
voltage to the VCC2 pins. The VCC2 pins supply voltage to the
processor core, independent of the voltage supplied to the I/O
buffers on the V CC3 pins. Upon sampling VCC2DET Low to
identify dual-voltage processor requirements, system logic
should sample VCC2H/L# to identif y the core voltage
requirements: 2.9-V and 3.2-V products (High) or 2.4-V and
lower products (Low).
■
VCC2H/L# is only driven High on older legacy (0.35-micron
process technology) AMD-K6 processors to indicate core
voltages of 2.9 V and 3.2 V.
■
VCC2H/L# is driven Low for all AMD-K6 processors with a
core voltage requirement of 2.4 V or less. Note that all AMD
products based on the 0.18-micron process technology,
including the AMD-K6-2E+ processor, are 2.0 V or less.
Note that this pin is not supported on the OBGA package.
Driven
VCC2H/L# always equals 0 and is never floated for 2.4 -V and
lower products — even during the Three-State Test mode. To
ensure proper operation for 2.9 -V and 3.2-V products, system
logic that samples VCC2H/L# should design a weak pullup
resistor for this signal.
Table 18. Output Pin Float Conditions for VCC2 High/Low
Name
Floated At:
VCC2DET1
Always Driven
VCC2H/L#1
Always Driven
Notes:
1. All outputs except VCC2DET, VCC2H/L#, and TDO float during the Three-State Test mode.
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5.53
VID[4:0] (Voltage Identification)
Pin Attribute
Output
Summary
For AMD PowerNow! technology-enabled processors, the
VID[4:0] signals are used to drive the VID inputs of the DC/DC
regulator that generates the core voltage for the processor. The
processor VID[4:0] outputs default to 01010b when RESET is
sampled asserted.
Note that these pins are supported on the low-power versions
only of the AMD-K6-2+ processor. For more information about
these signals, see the Embedded AMD-K6™ Processors BIOS
Design Guide Application Note, order# 23913.
Driven
Chapter 5
VID[4:0] are initialized to the default state after RESET is
sampled asserted, the CPU input clock is running, and the core
and I/O voltages are applied. Thereafter, the VID [4:0] outputs
are always driven.
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W/R# (Write/Read)
Pin Attribute
Output
Summary
The processor drives W/R# to indicate whether it is performing
a write or a read cycle on the bus. In addition, W/R# is used to
define other bus cycles, including interrupt acknowledge and
special cycles. See Table 23 and Table 24 on page 142 for more
details.
Driven and Floated
W/R# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted. W/R# is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
W/R# is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
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5.55
WB/WT# (Writeback or Writethrough)
Pin Attribute
Input
Summary
WB/WT#, together with PWT, specifies the data cache-line state
during cacheable read misses and write hits to shared cache
lines.
Sampled
Chapter 5
■
If WB/WT# = 0 or PWT = 1 during a cacheable read miss or
write hit to a shared cache line, the accessed line is cached
in the shared state. This is referred to as the writethrough
state because all write cycles to this cache line are driven
externally on the bus.
■
If WB/WT# = 1 and PWT = 0 during a cacheable read miss or
a write hit to a shared cache line, the accessed line is cached
in the exclusive state. Subsequent write hits to the same line
cause its state to transition from exclusive to modified. This
is referred to as the writeback state because the L1 data
cache and the L2 cache can contain modified cache lines
that are subject to be written back—referred to as a
writeback cycle—as the result of an inquire cycle, an
internal snoop, a flush operation, or the WBINVD
instruction.
WB/WT# is sampled on the clock edge that the first BRDY# or
NA# of a bus cycle is sampled asserted. If the cycle is a burst
read, WB/WT# is ignored during the last three assertions of
BRDY #. WB /WT# is sampled during mem ory re ad and
non-writeback write cycles and is ignored during all other types
of cycles.
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Pin Tables by Type
Table 19. Input Pin Types
Name
Type
Name
Type
A20M#1
Asynchronous
IGNNE#1
Asynchronous
AHOLD
Synchronous
INIT2
Asynchronous
BF[2:0]3
Synchronous
INTR1
Asynchronous
BOFF#
Synchronous
INV
Synchronous
BRDY#
Synchronous
KEN#
Synchronous
BRDYC#
Synchronous
NA#
Synchronous
CLK
Clock
NMI2
Asynchronous
EADS#
Synchronous
RESET4,5
Asynchronous
EWBE#6
Synchronous
SMI#2
Asynchronous
FLUSH#2,7
Asynchronous
STPCLK#1
Asynchronous
HOLD
Synchronous
WB/WT#
Synchronous
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold
times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold
times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain
asserted at least two clocks.
3. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold time
of two clocks relative to the negation of RESET.
4. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification before it is negated.
5. During a warm reset, while CLK and VCC are within their specification, RESET must remain asserted for a minimum of 15 clocks prior to
its negation.
6. When register bit EFER[3] is set to 1, EWBE# is ignored by the processor.
7. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be sampled on
a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which RESET is sampled
negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks relative to the negation of
RESET.
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Table 20. Output Pin Float Conditions
Name
Floated At: 1
Name
Floated At:1
A[4:3]2,3
HLDA, AHOLD, BOFF#
LOCK#2
HLDA, BOFF#
ADS#2
HLDA, BOFF#
M/IO#2
HLDA, BOFF#
ADSC#2
HLDA, BOFF#
PCD2
HLDA, BOFF#
Always Driven
PCHK#
Always Driven
APCHK#
HLDA, BOFF#
2
PWT
HLDA, BOFF#
BREQ
Always Driven
SCYC2
HLDA, BOFF#
CACHE#2
HLDA, BOFF#
SMIACT#
Always Driven
D/C#2
HLDA, BOFF#
VCC2DET
Always Driven
FERR#
Always Driven
VCC2H/L#
Always Driven
HIT#
Always Driven
VID[4:0]4
Always Driven
HITM#
Always Driven
W/R#2
HLDA, BOFF#
HLDA
Always Driven
BE[7:0]#
2
Notes:
1.
2.
3.
4.
All outputs except VCC2DET, VCC2H/L#, and TDO float during the Three-State Test mode.
Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.
Floated off the clock edge that AHOLD is sampled asserted.
Supported on the low-power versions only.
Table 21. Input/Output Pin Float Conditions
Name
Floated At:1
A[31:5]2,3
HLDA, AHOLD, BOFF#
AP2,3
HLDA, AHOLD, BOFF#
D[63:0]2
HLDA, BOFF#
DP[7:0]2
HLDA, BOFF#
Notes:
1. All outputs except VCC2DET and TDO float during the Three-State Test mode.
2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.
3. Floated off the clock edge that AHOLD is sampled asserted.
Table 22. Test Pin Types
Name
Type
TCK
Clock
Comment
TDI
Input
Sampled on the rising edge of TCK
TDO
Output
Driven on the falling edge of TCK
TMS
Input
Sampled on the rising edge of TCK
TRST#
Input
Asynchronous (Independent of TCK)
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Bus Cycle Definitions
Table 23. Bus Cycle Definition
Generated
by System Logic
Generated by the CPU
Bus Cycle Initiated
M/IO#
D/C#
W/R#
CACHE#
KEN#
Code Read, L1 Instruction Cache and L2 Cache Line Fill
1
0
0
0
0
Code Read, Noncacheable
1
0
0
1
x1
Code Read, Noncacheable
1
0
0
x
1
Encoding for Special Cycle
0
0
1
1
x
Interrupt Acknowledge
0
0
0
1
x
I/O Read
0
1
0
1
x
I/O Write
0
1
1
1
x
Memory Read, L1 Data Cache and L2 Cache Line Fill
1
1
0
0
0
Memory Read, Noncacheable
1
1
0
1
x
Memory Read, Noncacheable
1
1
0
x
1
Memory Write, L1 Data Cache or L2 Cache Writeback
1
1
1
0
x
Memory Write, Noncacheable
1
1
1
1
x
Notes:
1. x means “don’t care”
A4
BE7#
BE6#
BE5#
BE4#
BE3#
BE2#
BE1#
BE0#
M/IO#
D/C#
W/R#
CACHE#
KEN#
Table 24. Special Cycles
Stop Grant
1
1
1
1
1
1
0
1
1
0
0
1
1
x1
Enhanced Power Management (EPM)
Stop Grant2
0
1
0
1
1
1
1
1
1
0
0
1
1
x
Flush Acknowledge
(FLUSH# sampled asserted)
0
1
1
1
0
1
1
1
1
0
0
1
1
x
Writeback (WBINVD instruction)
0
1
1
1
1
0
1
1
1
0
0
1
1
x
Halt
0
1
1
1
1
1
0
1
1
0
0
1
1
x
Flush (INVD, WBINVD instruction)
0
1
1
1
1
1
1
0
1
0
0
1
1
x
Shutdown
0
1
1
1
1
1
1
1
0
0
0
1
1
x
Special Cycle
Notes:
1. x means “don’t care”.
2. Supported on the low-power versions only.
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6
AMD PowerNow!™ Technology
The AMD PowerNow!™ technology is an advanced secondgeneration power management feature that reduces the overall
power consumed by the processor through control of voltage
and frequency. This power saving technology is designed to be
dynamic and flexible by enabling instant “on-the-fly” and
independent control of both the processor’s core voltage and
frequency.
AMD PowerNow! technology can be used in conjunction with
the existing power management schemes in an embedded
system to provide a better combination of performance and
power savings than previously possible.
6.1
Enhanced Power Management Features
AMD PowerNow! technology-enabled processors include two
new f eat ure s spe cifically designed to enhance powe r
management functionality:
■
■
Dynamic core frequency control
Dynamic core voltage control
These enhanced power management features are accessed and
controlled through an I/O block and two registers:
■
■
■
An aligned 16-byte block of I/O address space is defined by
the Enhanced Power Management Register (EPMR).
The Enhanced Power Management Register (EPMR) is
supported on low-power versions of the processor only.
The Processor State Observability Register (PSOR) is
defined differently on the low-power versions of the
AMD-K6-2E+ processor to support AMD PowerNow!
technology features.
The EPMR and PSOR registers and the I/O block are defined in
this section, followed by a discussion of how to implement and
use the AMD PowerNow! technology features (see “Dynamic
Core Frequency and Core Voltage Control” on page 150). The
Embedded AMD-K6™ Processors BIOS Design Guide Application
Note, order# 23913, contains additional information.
Chapter 6
AMD PowerNow!™ Technology
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Enhanced Power
Management Register
(EPMR)
23542A/0—September 2000
The EPMR register allows software to access the aligned
Enhanced Power Management (EPM) 16-byte block of I/O
address space, which contains bits for enabling, controlling,
and monitoring the enhanced power management features. All
accesses to the EPM 16-byte I/O block must be aligned dword
accesses. Valid accesses to the EPM 16-byte block do not
generate I/O cycles on the host bus, while non-aligned and nondword accesses are passed to the host bus.
The EPMR is MSR C000_0086h.
Figure 54 and Table 25 define the EPMR register. An assertion
of RESET clears all of the bits of the 16-byte I/O block to zero
(excluding the Voltage ID Output bits which default to
01010b). BIOS must always initialize the EPMR register and
enhanced power management features whenever RESET is
asserted.
For more information about the EPMR register, see the
Embedded AMD-K6™ Processors BIOS Design Guide Application
Note, order# 23913.
63
4 3 2 1 0
16 15
IOBASE
G
S E
B N
C
Reserved
Symbol
IOBASE
GSBC
EN
Description
I/O Base Address
Generate Special Bus Cycle
Enable AMD PowerNow! Technology
Management
Bit
15-4
1
0
Figure 54. Enhanced Power Management Register (EPMR)
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Table 25. Enhanced Power Management Register (EPMR) Definition
Bit
63–16
R/W Function1
Description
Reserved
R
15-4
I/O BASE Address (IOBASE)
3-2
Reserved
R/W
R
All reserved bits are always read as 0.
IOBASE defines a base address for a 16-byte block of I/O address
space accessible for enabling, controlling, and monitoring the EPM
features.
All reserved bits are always read as 0.
1
Generate Special Bus Cycle (GSBC)
R/W
This bit controls whether a special bus cycle is generated upon dword
accesses within the EPM 16-byte I/O block. If set to 1, an EPM special
bus cycle is generated, where BE[7:0]# = BFh and A[4:3] = 00b.
0
Enable AMD PowerNow! Technology
Management (EN)
R/W
This bit controls access to the I/O-mapped address space for the AMD
PowerNow! technology EPM features. Clearing this bit to zero does
not affect the state of bits defined in the EPM 16-byte I/O block.
Notes:
1. All bits default to 0 when RESET is asserted.
IOBASE Field. The IOBASE field is initialized during POST to an
I/O address range used by an SMM handler to access the
enhanced power management features. Because the I/O range
is only enabled and accessed by the SMM handler during SMM,
the EPM features are hidden from all other software (OS
included)—BIOS does not need to report the I/O range to the
operating system.
GSBC Bit. If the GSBC bit is enabled (set to 1), a special bus
cycle is generated upon a dword access within the EPM 16-byte
I/O block. The EPM special bus cycle is defined as the
processor driving D/C# = 0, M/IO# = 0, and W/R# = 1, BE[7:0]# =
BFh and A[31:3] = 0000h. The system logic must return BRDY#
in response to all processor special cycles.
EN Bit. The EN bit should only be enabled (set to 1) by an SMM
handler when the SMM handler accesses the EPM features.
Upon exiting, the SMM handler should disable the EN bit and
thereby protect the EPM 16-byte I/O block from unwanted
accesses. When the EN bit is disabled, accesses to the EPM
block 16-byte I/O block are passed to the host bus.
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EPM 16-Byte I/O
Block
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The EPM 16-byte I/O block contains one 4-byte field—Bus
D iv iso r a n d Vol ta ge I D Co n t rol (B V C) — for e n abl in g,
controlling, and monitoring the enhanced power management
features (see Figure 55). Table 26 defines the function of the
BVC field within the EPM 16-byte I/O block mapped by the
EPMR.
8
12 11
15
7
0
BVC
Reserved
Symbol Description
BVC
Bus Divisor and Voltage ID Control
Bytes
11-8
Figure 55. EPM 16-Byte I/O Block
Table 26. EPM 16-Byte I/O Block Definition
R/W Function1
Byte
Description
15-12
Reserved
11-8
Bus Divisor and Voltage ID Control (BVC)
7-0
Reserved
R
R/W
R
All reserved bits are always read as 0.
The bit fields within the BVC bytes allow software to change the
processor bus divisor and core voltage.
All reserved bits are always read as 0.
Notes:
1. All bits default to 0 when RESET is asserted.
BVC. Figure 56 on page 147 shows the format, and Table 27 on
page 147 defines the function of each bit of the BVC field
located within the EPM 16-byte I/O block.
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12 11 10 9 8 7
31
B
V
C
M
SGTC
V
I BDC
D
C
IBF[2:0]
5 4
0
VIDO
Reserved
Symbol
SGTC
BVCM
VIDC
BDC
IBF[2:0]
VIDO
Description
Stop Grant Time-out Counter
Bus Divisor and VID Change Mode
Voltage ID Control
Bus Divisor Control
Internal BF Divisor
Voltage ID Output
Bits
31-12
11
10
9-8
7-5
4-0
Figure 56. Bus Divisor and Voltage ID Control (BVC) Field
Table 27. Bus Divisor and Voltage ID Control (BVC) Definition
Bit
31-12
11
10
R/W Function1
Description
Stop Grant Time-Out Counter (SGTC)
Bus Divisor and VID Change Mode
(BVCM)
Voltage ID Control (VIDC)
W
Writing a non-zero value to this field causes the processor to enter the
EPM Stop Grant state internally. This 20-bit value is multiplied by 4096
to determine the duration of the EPM Stop Grant state, measured in
processor bus clocks.
R/W
This bit controls the mode in which the bus-divisor and the voltage
control bits are allowed to change. If BVCM=0, the Bus Divisor and
Voltage ID changes take effect only upon entering the EPM Stop Grant
state as a result of the SGTC field being programmed. BVCM=1 is
reserved.
R/W
This bit controls the mode of Voltage ID control. If VIDC=0, the processor VID[4:0] pins are unchanged upon entering the EPM Stop Grant
state. If VIDC=1, the processor VID[4:0] pins are programmed to the
VIDO value upon entering the EPM Stop Grant state. BIOS should initialize this bit to 1 during the POST routine.
9-8
Bus Divisor Control (BDC)
R/W
This 2-bit field controls the mode of Bus Divisor control. If
BDC[1:0]=00b, the BF[2:0] pins are sampled at the falling edge of
RESET. If BDC[1:0]=1xb, the IBF[2:0] field is sampled upon entering the
EPM Stop Grant state. BDC[1:0]=01b is reserved. BIOS should initialize
these bits to 10b during the POST routine.
7-5
Internal BF Divisor (IBF[2:0])
R/W
If BDC[1:0]=1xb, the processor EBF[2:0] field of the PSOR is programmed to the IBF[2:0] value upon entering the EPM Stop Grant
state.
4-0
Voltage ID Output (VIDO)
R/W
This 5-bit value is driven out on the processor VID[4:0] pins upon
entering the EPM Stop Grant state if the VIDC bit=1. These bits are initialized to 01010b and driven on the processor VID[4:0] pins at RESET.
Notes:
1. All bits default to 0 when RESET is asserted, except the VIDO bits which default to 01010b.
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Processor State
Observability
Register (PSOR)
23542A/0—September 2000
To support AMD PowerNow! technology, all low-power versions
of the AMD-K6-2E+ processor provide a different version of the
Processor State Observability Register (PSOR), as shown in
Figure 57 and fully described in this section. All standardpower versions of the processor support the PSOR register as
defined on page 49. The PSOR register is MSR C000_0087h.
.
Symbol
PBF
VID
63
24
23
21 20
PBF[2:0]
16 15
VID
Description
Pin Bus Frequency Divisor
Voltage ID
9 8
N
O
L
2
7
4
STEP
Bits
23-21
20-16
3 2
0
EBF[2:0]
Reserved
Symbol
NOL2
STEP
EBF
Description
No L2 Functionality
Processor Stepping
Effective Bus Frequency Divisor
Bits
8
7-4
2-0
Figure 57. Processor State Observability Register (PSOR)—Low-Power Versions of the Processor
PBF[2:0] Field. This read-only field contains the BF divisor values
externally applied to the processor BF[2:0] pins. These input BF
values are sampled by the processor during the falling
transition of RESET.
Note: This BF divisor value may be different than the BF divisor
value supplied to the processor’s internal PLL.
VID Field. This read-only field contains the Voltage ID bits driven
to the processor VID[4:0] pins at RESET. These bits are
initialized to 01010b and driven on the VID[4:0] pins at RESET.
Note: Low-power AMD-K6-2E+ processors support AMD
PowerNow! technology, which enables dynamic alteration of
the processor’s core voltage. See “Enhanced Power
Management Register (EPMR)” on page 144 for
information on programming the VID[4:0] pins.
NOL2 Bit. This read-only bit indicates whether the processor
contains an L2 cache. This bit is always set to 0 for the
AMD-K6-2E+ processor.
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STEP Field. This read-only field contains the stepping ID. This is
identical to the value returned by CPUID standard function 1 in
EAX[3:0].
EBF[2:0] Field. This read-only field contains the effective value of
the BF divisor supplied to the processor’s internal PLL, which
allows the BIOS to determine the frequency of the host bus. The
core frequency must first be determined using the Time Stamp
Counter (TSC) method (see “Time Stamp Counter” on page 46).
The core frequency is then divided by the processor-to-bus clock
ratio as determined by the EBF field (see Table 28). The result
is the frequency of the processor bus.
Table 28. Processor-to-Bus Clock Ratios
State of EBF[2:0]
Processor-to-Bus Clock Ratio
100b
2.0x1
101b
3.0x
110b
6.0x
111b
3.5x
000b
4.5x
001b
5.0x
010b
4.0x
011b
5.5x
Notes:
1. The AMD-K6-2E+ processor does not support the 2.5x ratio supported by earlier AMD-K6 processors. Instead, a ratio of 2.0x is selected when EBF[2:0] equals 100b.
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6.2
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Dynamic Core Frequency and Core Voltage Control
AMD PowerNow! technology-enabled processors support the
ability to change the bus frequency divisor and core voltage
transparently to the user during run-time. These features are
implemented in conjunction with a new clock control state—
the EPM Stop Grant state.
For AMD PowerNow! technology state transitions, the EPMR
register is accessed using an SMM handler.
■
The SMM handler initiates core voltage and frequency
transitions by writing a non-zero value to the Stop Grant
Time-Out Counter (SGTC) field.
■
This action automatically places the processor into the EPM
Stop Grant State and transitions the CPU core voltage and
frequency to the values specified in the Voltage ID Output
(VIDO) and Internal BF Divisor (IBF) fields of the BVC field.
Once the timer of the SGTC has expired, the EPM Stop
Grant State is exited and the AMD PowerNow! technology
state transition is completed.
■
See “Clock Control” on page 275 for more information about
the EPM Stop Grant State.
Effective Bus
Frequency Divisor
(EBF[2:0])
The processor core frequency is controlled by the Effective Bus
Frequency Divisor—EBF[2:0]—which dictates the processor-tobus clock ratio supplied to the processor’s internal PLL. This
processor-to-bus clock ratio is multiplied by the external bus
frequency to set the frequency of operation for the processor
core.
■
■
At the fall of RESET, the EBF[2:0] value is determined by
the state of the processor BF[2:0] input pins.
Afterwards, the EBF[2:0] value can be dynamically
controlled through AMD PowerNow! technology state
transitions.
Table 28 on page 149 lists valid EBF[2:0] states and equivalent
processor-to-bus clock ratios.
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Dynamic Core
Frequency Control
For AMD PowerNow! technology core frequency transitions,
the BVC field of the EPM 16-byte I/O block is accessed through
an SMM handler.
■
To change the processor core frequency, the SMM handler
initiates core voltage and frequency transitions by writing a
non-zero value to the SGTC field.
This action automatically places the processor into the EPM
Stop Grant state and transitions the CPU core voltage and
frequency to the values specified in the VIDO and IBF fields
of the BVC field.
Note: System-initiated inquire (snoop) cycles are not supported
and must be prevented during the EPM Stop Grant state.
■
Voltage Identification
(VID) Outputs
AMD PowerNow! technology-enabled processors feature
Voltage ID (VID) outputs to support dynamic control of the
core voltage.
■
■
■
Chapter 6
These outputs serve as inputs to a DC/DC regulator that
supplies the processor core voltage.
Based on its VID[4:0] inputs, the regulator outputs a
corresponding voltage.
For those regulators that do not support VID inputs, the
processor VID[4:0] outputs must be used to manipulate the
regulator’s feedback voltage to vary the regulator output
voltage.
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7
Bus Cycles
The following sections describe and illustrate the timing and
relationship of bus signals during various types of bus cycles. A
representative set of bus cycles is illustrated.
7.1
Timing Diagrams
The timing diagrams illustrate the signals on the external local
bus as a function of time, as measured by the bus clock (CLK).
Bus Clock (CLK)
Throughout this chapter, the term clock refers to a single
bus-clock cycle. A clock extends from one rising CLK edge to
the next rising CLK edge. The processor samples and drives
most signals relative to the rising edge of CLK. The exceptions
to this rule include the following:
■
■
■
Waveform
Definitions
BF[2:0]—Sampled on the falling edge of RESET
FLUSH#—Sampled on the falling edge of RESET, also
sampled on the rising edge of CLK
All inputs and outputs are sampled relative to TCK in
Boundary-Scan Test Mode. Inputs are sampled on the rising
edge of TCK, outputs are driven off of the falling edge of
TCK.
For each signal in the timing diagrams, the High level
represents 1, the Low level represents 0, and the Middle level
represents the floating (high-impedance) state.
When both the High and Low levels are shown, the meaning
depends on the signal:
■
■
A single signal indicates ‘don’t care’.
In the case of bus activity, if both High and Low levels are
shown, it indicates that the processor, alternate master, or
system logic is driving a value, but this value may or may not
be valid. (For example, the value on the address bus is valid
only during the assertion of ADS#, but addresses are also
driven on the bus at other times.)
Figure 58 on page 154 defines the different waveform
representations.
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Active High Signals
For all active High signals, the term asserted means the signal is
in the High-voltage state and the term negated means the signal
is in the Low-voltage state.
Active Low Signals
For all active Low signals, the term asserted means the signal is
in the Low-voltage state and the term negated means the signal
is in the High-voltage state.
Description
Waveform
Don’t care or bus is driven
Signal or bus is changing from Low to High
Signal or bus is changing from High to Low
Bus is changing
Bus is changing from valid to invalid
Signal or bus is floating
Denotes multiple clock periods
Figure 58. Waveform Definitions
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7.2
Bus States
The bus states illustrated in Figure 59 are described in this
section.
Bus State
Addr
Pending
Request?
No
Branch Condition
Yes
Address
Data
Idle
Data
Idle
Yes
Last BRDY#
Asserted?
No
NA# Sampled
Asserted?
Data-NA#
Yes
No
Yes
Data-NA#
Requested
Last BRDY#
Asserted?
No
Yes
No
Pending
Request?
Pipe-A
NA# Sampled
Asserted?
No
Yes
Pipeline
Address
Pipe-D
No
Pipeline
Data
Last BRDY#
Asserted?
Yes
Trans
Yes
NA# Sampled
Asserted?
Transition
Yes
Bus Transition?
No
No
Note: The processor transitions to the IDLE state on the clock edge on which BOFF# or RESET is sampled asserted.
Figure 59. Bus State Machine Diagram
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Idle
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The processor does not drive the system bus in the Idle state
and remains in this state until a new bus cycle is requested. The
processor enters this state off the clock edge on which the last
BRDY# of a cycle is sampled asserted during the following
conditions:
■
■
The processor is in the Data state
The processor is in the Data-NA# Requested state and no
internal pending cycle is requested
In addition, the processor is forced into this state when the
system logic asserts RESET or BOFF#. The transition to this
state occurs on the clock edge on which RESET or BOFF# is
sampled asserted.
Address
In this state, the processor drives ADS# to indicate the
beginning of a new bus cycle by validating the address and
control signals. The processor remains in this state for one clock
and unconditionally enters the Data state on the next clock
edge.
Data
In the Data state, the processor drives the data bus during a
write cycle or expects data to be returned during a read cycle.
The processor remains in this state until either NA# or the last
BRDY# is sampled asserted. If the last BRDY# is sampled
asserted or both the last BRDY# and NA# are sampled asserted
on the same clock edge, the processor enters the Idle state. If
NA# is sampled asserted first, the processor enters the
Data-NA# Requested state.
Data-NA# Requested
If the processor samples NA# asserted while in the Data state
and the current bus cycle is not completed (the last BRDY# is
not sampled asserted), it enters the Data-NA# Requested state.
The processor remains in this state until either the last BRDY#
is sampled asserted or an internal pending cycle is requested. If
the last BRDY# is sampled asserted before the processor drives
a new bus cycle, the processor enters the Idle state (no internal
pending cycle is requested) or the Address state (processor has
a internal pending cycle).
Pipeline Address
In this state, the processor drives ADS#, indicating the
beginning of a new bus cycle and validating the address and
control signals. In this state, the processor is still waiting for the
current bus cycle to be completed (until the last BRDY# is
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sampled asserted). If the last BRDY# is not sampled asserted,
the processor enters the Pipeline Data state.
If the processor samples the last BRDY# asserted in this state, it
determines if a bus transition is required between the current
bus cycle and the pipelined bus cycle. A bus transition is
required when the data bus direction changes between bus
cycles, such as a memory write cycle followed by a memory read
cycle. If a bus transition is required, the processor enters the
Transition state for one clock to prevent data bus contention. If
a bus transition is not required, the processor enters the Data
state.
The processor does not transition to the Data-NA# Requested
state from the Pipeline Address state because the processor
does not begin sampling NA# until it has exited the Pipeline
Address state.
Pipeline Data
Two bus cycles are executing concurrently in this state. The
processor cannot issue any additional bus cycles until the
current bus cycle is completed. The processor drives the data
bus during write cycles or expects data to be returned during
read cycles for the current bus cycle until the last BRDY# of the
current bus cycle is sampled asserted.
If the processor samples the last BRDY# asserted in this state, it
determines if a bus transition is required between the current
bus cycle and the pipelined bus cycle. If the bus transition is
required, the processor enters the Transition state for one clock
to prevent data bus contention. If a bus transition is not
required, the processor enters the Data state (NA# was not
sampled asserted) or the Data-NA# Requested state (NA# was
sampled asserted).
Transition
Chapter 7
The processor enters this state for one clock during data bus
transitions and enters the Data state on the next clock edge if
NA# is not sampled asserted. The sole purpose of this state is to
avoid bus contention caused by bus transitions during pipeline
operation.
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Memory Reads and Writes
The AMD-K6-2E+ processor performs single or burst-memory
bus cycles.
■
■
■
Single-Transfer
Memory Read and
Write
The single-transfer memory bus cycle transfers 1, 2, 4, or 8
bytes and requires a minimum of two clocks.
Misaligned instructions or operands result in a split cycle,
which requires multiple transactions on the bus.
A burst cycle consists of four back-to-back 8-byte (64-bit)
transfers on the data bus.
Figure 60 on page 159 shows a single-transfer read from
memory, followed by two single-transfer writes to memory. For
the memory read cycle, the processor asserts ADS# for one
clock to validate the bus cycle and also drives A[31:3], BE[7:0]#,
D/C#, W/R#, and M/IO# to the bus. The processor then waits for
the system logic to return the data on D[63:0] (with DP[7:0] for
parity checking) and assert BRDY#. The processor samples
BRDY# on every clock edge starting with the clock edge after
the clock edge that negates ADS#. See “BRDY# (Burst Ready)”
on page 103.
During the read cycle, the processor drives PCD, PWT, and
CACHE# to indicate its caching and cache-coherency intent for
the access. The system logic returns KEN# and WB/WT# to
either confirm or change this intent. If the processor asserts
PCD and negates CACHE#, the accesses are noncacheable, even
though the system logic asserts KEN# during the BRDY# to
indicate its support for cacheability. The processor (which
drives CACHE#) and the system logic (which drives KEN#) must
agree in order for an access to be cacheable.
The processor can drive another cycle (in this example, a write
cycle) by asserting ADS# off the next clock edge after BRDY# is
sampled asserted. Therefore, an idle clock is guaranteed
between any two bus cycles. The processor drives D[63:0] with
valid data one clock edge after the clock edge on which ADS# is
asserted. To minimize processor idle times, the system logic
stores the address and data in write buffers, returns BRDY#,
and performs the store to memory later. If the processor
samples EWBE# negated during a write cycle, it suspends
certain activities until EWBE# is sampled asserted. See
“EWBE# (External Write Buffer Empty)” on page 110. In
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Figure 60, the second write cycle occurs during the execution of
a serializing instruction. The processor delays the following
cycle until EWBE# is sampled asserted.
Read Cycle
ADDR DATA
IDLE
Write Cycle (Next Cycle Delayed by EWBE#)
Write Cycle
ADDR DATA DATA
IDLE
ADDR DATA DATA
IDLE
IDLE
IDLE
IDLE
IDLE
ADDR
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BREQ
D[63:0]
DP[7:0]
CACHE#
EWBE#
KEN#
BRDY#
WB/WT#
Figure 60. Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE#
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Misaligned
Single-Transfer
Memory Read and
Write
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Figure 61 on page 161 shows a misaligned (split) memory read
followed by a misaligned memory write. Any cycle that is not
aligned as defined in “SCYC (Split Cycle)” on page 129 is
considered misaligned. When the processor encounters a
misaligned access, it determines the appropriate pair of bus
cycles — each with its own ADS# and BRDY# — required to
complete the access.
The AMD-K6-2E+ processor performs misaligned memory reads
and memory writes using least-significant bytes (LSBs) first
followed by most-significant bytes (MSBs). Table 29 shows the
order. In the first memory read cycle in Figure 61, the processor
reads the least-significant bytes. Immediately after the
processor samples BRDY# asserted, it drives the second bus
cycle to read the most-significant bytes to complete the
misaligned transfer.
Table 29. Bus-Cycle Order During Misaligned Memory Transfers
Type of Access
First Cycle
Second Cycle
Memory Read
LSBs
MSBs
Memory Write
LSBs
MSBs
Similarly, the misaligned memory write cycle in Figure 61
transfers the LSBs to the memory bus first. In the next cycle,
after the processor samples BRDY# asserted, the MSBs are
written to the memory bus.
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Memory Read (Misaligned)
Memory Write (Misaligned)
ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA DATA DATA IDLE ADDR DATA DATA DATA IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
LSB
MSB
LSB
MSB
BRDY#
Figure 61. Misaligned Single-Transfer Memory Read and Write
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Burst Reads and
Pipelined Burst Reads
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Figure 62 on page 163 shows normal burst read cycles and a
pipelined burst read cycle. The AMD-K6-2E+ processor drives
CACHE# and ADS# together to specify that the current bus
cycle is a burst cycle. If the processor samples KEN# asserted
with the first BRDY#, it performs burst transfers. During the
burst transfers, the system logic must ignore BE[7:0]# and must
return all eight bytes beginning at the starting address the
processor asserts on A[31:3]. Depending on the starting
address, the system logic must determine the successive
quadword addresses (A[4:3]) for each transfer in a burst, as
shown in Table 30. The processor expects the second, third, and
fourth quadwords to occur in the sequences shown in Table 30.
Table 30. A[4:3] Address-Generation Sequence During Bursts
A[4:3] Addresses of Subsequent
Quadwords1 Generated by System Logic
Address Driven By
Processor on A[4:3]
Quadword 1
Quadword 2
Quadword 3
Quadword 4
00b
01b
10b
11b
01b
00b
11b
10b
10b
11b
00b
01b
11b
10b
01b
00b
Notes:
1. Quadword = 8 bytes.
In Figure 62, the processor drives CACHE# throughout all burst
read cycles. In the first burst read cycle, the processor drives
ADS# and CACHE#, then samples BRDY# on every clock edge
starting with the clock edge after the clock edge that negates
ADS#. The processor samples KEN# asserted on the clock edge
on which the first BRDY# is sampled asserted, executes a
32-byte burst read cycle, and expects a total of four BRDY#
signals. An ideal no-wait state access is shown in Figure 62,
whereas most system logic solutions add wait states between
the transfers.
The second burst read cycle illustrates a similar sequence, but
the processor samples NA# asserted on the same clock edge
that the first BRDY# is sampled asserted. NA# assertion
indicates the system logic is requesting the processor to output
the next address early (also known as a pipeline transfer
request). Without waiting for the current cycle to complete, the
processor drives ADS# and related signals for the next burst
cycle. Pipelining can reduce processor cycle-to-cycle idle times.
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Burst Read
Burst Read
Pipelined Burst Read
DATA PIPE
ADDR DATA DATA DATA DATA IDLE ADDR DATA DATA
DATA DATA DATA DATA IDLE
-NA -ADDR
CLK
A[31:3]
ADDR1
ADDR2
ADDR3
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
NA#
D[63:0]
DATA1
DATA2
DATA3
CACHE#
KEN#
BRDY#
Figure 62. Burst Reads and Pipelined Burst Reads
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Burst Writeback
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Figure 63 on page 165 shows a burst read followed by a
writeback transaction. The AMD-K6-2E+ processor initiates
writebacks under the following conditions:
■
■
■
■
Replacement—If a cache-line fill is initiated for a cache line
currently filled with valid entries, the processor selects a
line for replacement based on a least-recently-used (LRU)
algorithm for the L1 instruction cache and the L2 cache, and
a least-recently-allocated (LRA) algorithm for the L1 data
cache. Before a replacement is made to a L1 data cache or L2
cache line that is in the modified state, the modified line is
scheduled to be written back to memory.
Internal Snoop—The processor snoops its L1 instruction
cache during read or write misses to its L1 data cache, and it
snoops its L1 data cache during read misses to its L1
instruction cache. This snooping is performed to determine
whether the same address is stored in both caches, a
situation that is taken to imply the occurrence of
self-modifying code. If an internal snoop hits a L1 data cache
line in the modified state, the line is written back to memory
before being invalidated.
WBINVD Instruction—When the processor executes a
WBINVD instruction, it writes back all modified lines in the
L1 data cache and L2 cache, and then invalidates all lines in
all caches.
Cache Flush—When the processor samples FLUSH#
asserted, it executes a flush acknowledge special cycle and
writes back all modified lines in the L1 data cache and L2
cache, and then invalidates all lines in all caches.
The processor drives writeback cycles during inquire or cache
flush cycles. The writeback shown in Figure 63 is caused by a
cache-line replacement. The processor completes the burst read
cycle that fills the cache line. Immediately following the burst
read cycle is the burst writeback cycle that represents the
modified line to be written back to memory. D[63:0] are driven
one clock edge after the clock edge on which ADS# is asserted
and are subsequently changed off the clock edge on which each
of the four BRDY# signals of the burst cycle are sampled
asserted.
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Burst Writeback from L1 Cache
Burst Read
ADDR
DATA
DATA
DATA
DATA
IDLE
ADDR
DATA
DATA
DATA
DATA
IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
CACHE#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
WB/WT#
Figure 63. Burst Writeback due to Cache-Line Replacement
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7.4
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I/O Read and Write
Basic I/O Read and
Write
The processor accesses I/O when it executes an I/O instruction
(for example, IN or OUT). Figure 64 shows an I/O read followed
by an I/O write. The processor drives M/IO# Low and D/C# High
during I/O cycles. In this example, the first cycle shows a single
wait state I/O read cycle. It follows the same sequence as a
single-transfer memory read cycle. The processor drives ADS#
to initiate the bus cycle, then it samples BRDY# on every clock
edge starting with the clock edge after the clock edge that
negates ADS#. The system logic must return BRDY# to
complete the cycle. When the processor samples BRDY#
asserted, it can assert ADS# for the next cycle off the next clock
edge. (In this example, an I/O write cycle.)
The I/O write cycle is similar to a memory write cycle, but the
processor drives M/IO# low during an I/O write cycle. The
processor asserts ADS# to initiate the bus cycle. The processor
drives D[63:0] with valid data one clock edge after the clock
edge on which ADS# is asserted. The system logic must assert
BRDY# when the data is properly stored to the I/O destination.
The processor samples BRDY# on every clock edge starting with
the clock edge after the clock edge that negates ADS#. In this
example, two wait states are inserted while the processor waits
for BRDY# to be asserted.
I/O Write Cycle
I/O Read Cycle
ADDR
DATA
DATA
IDLE
ADDR
DATA
DATA
DATA
IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
BRDY#
Figure 64. Basic I/O Read and Write
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AMD-K6™-2E+ Embedded Processor Data Sheet
Misaligned I/O Read
and Write
Table 31 shows the misaligned I/O read and write cycle order
executed by the AMD-K6-2E+ processor. In Figure 65, the
least-significant bytes (LSBs) are transferred first. Immediately
after the processor samples BRDY# asserted, it drives the
second bus cycle to transfer the most-significant bytes (MSBs)
to complete the misaligned bus cycle.
Table 31. Bus-Cycle Order During Misaligned I/O Transfers
Type of Access
First Cycle
Second Cycle
I/O Read
LSBs
MSBs
I/O Write
LSBs
MSBs
Misaligned I/O Write
Misaligned I/O Read
ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA DATA DATA IDLE ADDR DATA DATA DATA IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
SCYC
D[63:0]
LSB
MSB
LSB
MSB
BRDY#
Figure 65. Misaligned I/O Transfer
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7.5
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Inquire and Bus Arbitration Cycles
The AMD-K6-2E+ processor provides built-in level-one (L1)
data and instruction caches, and a unified level-two (L2) cache.
Each L1 cache is 32 Kbytes and two-way set-associative. The L2
cache is 128 Kbytes and four-way set-associative. The system
logic or other bus master devices can initiate an inquire cycle to
maintain cache/memory coherency. In response to the inquire
cycle, the processor compares the inquire address with its cache
tag addresses in all caches, and, if necessary, updates the MESI
state of the cache line and performs writebacks to memory.
An inquire cycle can be initiated by asserting AHOLD, BOFF#,
or HOLD. AHOLD is exclusively used to support inquire cycles.
During AHOLD-initiated inquire cycles, the processor only
floats the address bus. BOFF# provides the fastest access to the
bus because it aborts any processor cycle that is in-progress,
whereas AHOLD and HOLD both permit an in-progress bus
cycle to complete. During HOLD-initiated and BOFF#-initiated
inquire cycles, the processor floats all of its bus-driving signals.
The AMD-K6-2E+ processor does not support system-initiated
inquire cycles during the Enhanced Power Management (EPM)
Stop Grant State. For more information on the EPM Stop Grant
State, see “Clock Control” on page 275.
Hold and Hold
Acknowledge Cycle
The system logic or another bus device can assert HOLD to
initiate an inquire cycle or to gain full control of the bus. When
the AMD-K6-2E+ processor samples HOLD asserted, it
completes any in-progress bus cycle and asserts HLDA to
acknowledge release of the bus. The processor floats the
following signals off the same clock edge on which HLDA is
asserted:
■
■
■
■
■
■
■
168
A[31:3]
ADS#
AP#
BE[7:0]#
CACHE#
D[63:0]
D/C#
■
■
■
■
■
■
■
Bus Cycles
DP[7:0]
LOCK#
M/IO#
PCD
PWT
SCYC
W/R#
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AMD-K6™-2E+ Embedded Processor Data Sheet
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Figure 66 on page 169 shows a basic HOLD/HLDA operation. In
this example, the processor samples HOLD asserted during the
memory read cycle. It continues the current memory read cycle
until BRDY# is sampled asserted. The processor drives HLDA
and floats its outputs one clock edge after the last BRDY# of the
cycle is sampled asserted. The system logic can assert HOLD for
as long as it needs to utilize the bus. The processor samples
HOLD on every clock edge but does not assert HLDA until any
in-progress cycle or sequence of locked cycles is completed.
When the processor samples HOLD negated during a hold
acknowledge cycle, it negates HLDA off the next clock edge.
The processor regains control of the bus and can assert ADS#
off the same clock edge on which HLDA is negated.
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
HOLD
HLDA
BRDY#
Figure 66. Basic HOLD/HLDA Operation
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HOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
23542A/0—September 2000
Figure 67 on page 171 shows a HOLD-initiated inquire cycle. In
this example, the processor samples HOLD asserted during the
burst memory read cycle. The processor completes the current
cycle (until the last expected BRDY# is sampled asserted),
asserts HLDA and floats its outputs as described in “Hold and
Hold Acknowledge Cycle” on page 168.
The system logic drives an inquire cycle within the hold
acknowledge cycle. It asserts EADS#, which validates the
inquire address on A[31:5]. If EADS# is sampled asserted
before HOLD is sampled negated, the processor recognizes it as
a valid inquire cycle.
In Figure 67, the processor asserts HIT# and negates HITM# on
the clock edge after the clock edge on which EADS# is sampled
asserted, indicating the current inquire cycle hit a shared or
exclusive cache line. (Shared and exclusive cache lines have not
been modified and do not need to be written back.) During an
inquire cycle, the processor samples INV to determine whether
the addressed cache line found in the processor’s caches
transitions to the invalid state or the shared state. In this
example, the processor samples INV asserted with EADS#,
which invalidates the cache line.
The system logic can negate HOLD off the same clock edge on
which EADS# is sampled asserted. The processor continues
driving HIT# in the same state until the next inquire cycle.
HITM# is not asserted unless HIT# is asserted.
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Burst Memory Read
Inquire
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
HOLD
HLDA
EADS#
INV
Figure 67. HOLD-Initiated Inquire Hit to Shared or Exclusive Line
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HOLD-Initiated
Inquire Hit to
Modified Line
23542A/0—September 2000
Figure 68 on page 173 shows the same sequence as Figure 67 on
page 171, but in Figure 68 the inquire cycle hits a modified line
and the processor asserts both HIT# and HITM#. In this
example, the processor performs a writeback cycle immediately
after the inquire cycle. It updates the modified cache line to
external memory (normally, external cache or DRAM). The
processor uses the address (A[31:5]) that was latched during the
inquire cycle to perform the writeback cycle. The processor
asserts HITM# throughout the writeback cycle and negates
HITM# one clock edge after the last expected BRDY# of the
writeback is sampled asserted.
When the processor samples EADS# during the inquire cycle, it
also samples INV to determine the cache line MESI state after
the inquire cycle. If INV is sampled asserted during an inquire
cycle, the processor transitions the line (if found) to the invalid
stat e, regardless of its previous sta te. The cache line
invalidation operation is not visible on the bus. If INV is
sampled negated during an inquire cycle, the processor
transitions the line (if found) to the shared state. In Figure 68
the processor samples INV asserted during the inquire cycle.
In a HOLD-initiated inquire cycle, the system logic can negate
HOLD off the same clock edge on which EADS# is sampled
asserted. The processor drives HIT# and HITM# on the clock
edge after the clock edge on which EADS# is sampled asserted.
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Burst Memory Read
Inquire
Writeback Cycle
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
HOLD
HLDA
EADS#
INV
Figure 68. HOLD-Initiated Inquire Hit to Modified Line
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AHOLD-Initiated
Inquire Miss
23542A/0—September 2000
AHOLD can be asserted by the system to initiate one or more
inquire cycles. To allow the system to drive the address bus
during an inquire cycle, the processor floats A[31:3] and AP off
the clock edge on which AHOLD is sampled asserted. The data
bus and all other control and status signals remain under the
control of the processor and are not floated. This functionality
allows a bus cycle in progress when AHOLD is sampled asserted
to continue to completion. The processor resumes driving the
address bus off the clock edge on which AHOLD is sampled
negated.
In Figure 69 on page 175, the processor samples AHOLD
asserted during the memory burst read cycle, and it floats the
address bus off the same clock edge on which it samples
AHOLD asserted. While the processor still controls the bus, it
completes the current cycle until the last expected BRDY# is
sampled asserted. The system logic drives EADS# with an
inquire address on A[31:5] during an inquire cycle. The
processor samples EADS# asserted and compares the inquire
address to its tag address in the L1 instruction and data caches,
and in the L2 cache. In Figure 69, the inquire address misses the
tag address in the processor (both HIT# and HITM# are
negated). Therefore, the processor proceeds to the next cycle
when it samples AHOLD negated. (The processor can drive a
new cycle by asserting ADS# off the same clock edge that it
samples AHOLD negated.)
For an AHOLD-initiated inquire cycle to be recognized, the
processor must sample AHOLD asserted for at least two
consecutive clocks before it samples EADS# asserted. If the
processor detects an address parity error during an inquire
cycle, APCHK# is asserted for one clock. The system logic must
respond appropriately to the assertion of this signal.
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Inquire
Read
CLK
A[31:3]
BE[7:0]#
AP
APCHK#
ADS#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 69. AHOLD-Initiated Inquire Miss
Chapter 7
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AHOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
23542A/0—September 2000
In Figure 70 on page 177, the processor asserts HIT# and
negates HITM# off the clock edge after the clock edge on which
EADS# is sampled asserted, indicating the current inquire
cycle hits either a shared or exclusive line. (HIT# is driven in
the same state until the next inquire cycle.) The processor
samples INV asserted during the inquire cycle and transitions
the line to the invalid state regardless of its previous state.
During an AHOLD-initiated inquire cycle, the processor
samples AHOLD on every clock edge until it is negated. In
Figure 70, the processor asserts ADS# off the same clock on
which AHOLD is sampled negated. If the inquire cycle hits a
modified line, the processor performs a writeback cycle before
it drives a new bus cycle. The next section describes the
AHOLD-initiated inquire cycle that hits a modified line.
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Inquire
Burst Memory Read
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 70. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line
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AHOLD-Initiated
Inquire Hit to
Modified Line
23542A/0—September 2000
Figure 71 on page 179 shows an AHOLD-initiated inquire cycle
that hits a modified line. During the inquire cycle in this
example, the processor asserts both HIT# and HITM# on the
clock edge after the clock edge that it samples EADS# asserted.
This condition indicates that the cache line exists in the
processor’s L1 data cache or L2 cache in the modified state.
If the inquire cycle hits a modified line, the processor performs
a writeback cycle immediately after the inquire cycle to update
the modified cache line to shared memory (normally external
cache or DRAM). In Figure 71, the system logic holds AHOLD
asserted throughout the inquire cycle and the processor
writeback cycle. In this case, the processor is not driving the
address bus during the writeback cycle because AHOLD is
sampled asserted. The system logic writes the data to memory
by using its latched copy of the inquire cycle address. If the
processor samples AHOLD negated before it performs the
writeback cycle, it drives the writeback cycle by using the
address (A[31:5]) that it latched during the inquire cycle.
If INV is sampled asserted during an inquire cycle, the
processor transitions the line (if found) to the invalid state,
regardless of its previous state (the cache invalidation
operation is not visible on the bus). If INV is sampled negated
during an inquire cycle, the processor transitions the line (if
found) to the shared state. In either case, if the line is found in
the modified state, the processor writes it back to memory
before changing its state. Figure 71 shows that the processor
samples INV asserted during the inquire cycle and invalidates
the cache line after the inquire cycle.
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Burst Memory Read
Inquire
Writeback
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 71. AHOLD-Initiated Inquire Hit to Modified Line
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AMD-K6™-2E+ Embedded Processor Data Sheet
AHOLD Restriction
When the system logic drives an AHOLD-initiated inquire
cycle, it must assert AHOLD for at least two clocks before it
asserts EADS#. This requirement guarantees the processor
recognizes and responds to the inquire cycle properly. The
processor’s 32 address bus drivers turn on almost immediately
after AHOLD is sampled negated. If the processor switches the
data bus (D[63:0] and DP[7:0]) during a write cycle off the same
clock edge that switches the address bus (A[31:3] and AP), the
processor switches 102 drivers simultaneously, which can lead
to ground-bounce spikes. Therefore, before negating AHOLD
the following restrictions must be observed by the system logic:
■
■
■
180
23542A/0—September 2000
When the system logic negates AHOLD during a write cycle,
it must ensure that AHOLD is not sampled negated on the
clock edge on which BRDY# is sampled asserted (See
Figure 72 on page 181).
When the system logic negates AHOLD during a writeback
cycle, it must ensure that AHOLD is not sampled negated on
the clock edge on which ADS# is negated (See Figure 72).
When a write cycle is pipelined into a read cycle, AHOLD
must not be sampled negated on the clock edge after the
clock edge on which the last BRDY# of the read cycle is
sampled asserted to avoid the processor simultaneously
driving the data bus (for the pending write cycle) and the
address bus off this same clock edge.
Bus Cycles
Chapter 7
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
CLK
ADS#
W/R#
HITM#
EADS#
D[63:0]
BRDY#
Legal AHOLD negation during write cycle
AHOLD
Illegal AHOLD negation during write cycle
The system must ensure that AHOLD is not sampled negated on the clock edge that ADS# is negated.
The system must ensure that AHOLD is not sampled negated on the clock edge on which BRDY# is sampled asserted.
Figure 72. AHOLD Restriction
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Bus Backoff (BOFF#)
23542A/0—September 2000
BOFF# provides the fastest response among bus-hold inputs.
Either the system logic or another bus master can assert BOFF#
to gain control of the bus immediately. BOFF# is also used to
resolve potential deadlock problems that arise as a result of
inquire cycles. The processor samples BOFF# on every clock
e d g e . I f B O F F # i s s a m p l e d a s s e r t e d , t h e p ro c e s s o r
unconditionally aborts any cycles in progress and transitions to
a bus hold state. (See “BOFF# (Backoff)” on page 102.)
Figure 73 on page 183 shows a read cycle that is aborted when
the processor samples BOFF# asserted even though BRDY# is
sampled asserted on the same clock edge. The read cycle is
restarted after BOFF# is sampled negated (KEN# must be in
the same state during the restarted cycle as its state during the
aborted cycle).
During a BOFF#-initiated inquire cycle that hits a shared or
exclusive line, the processor samples BOFF# negated and
restarts any bus cycle that was aborted when BOFF# was
asserted. If a BOFF#-initiated inquire cycle hits a modified line,
the processor performs a writeback cycle before it restarts the
aborted cycle.
If the processor samples BOFF# asserted on the same clock
edge that it asserts ADS#, ADS# is floated but the system logic
may erroneously interpret ADS# as asserted. In this case, the
system logic must properly interpret the state of ADS# when
BOFF# is negated.
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Read
Backoff Cycle
Restart Read Cycle
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BOFF#
D[63:0]
BRDY#
Figure 73. BOFF# Timing
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Locked Cycles
23542A/0—September 2000
The processor asserts LOCK# during a sequence of bus cycles to
ensure the cycles are completed without allowing other bus
masters to intervene. Locked operations can consist of two to
five cycles. LOCK# is asserted during the following operations:
■
■
■
■
■
An interrupt acknowledge sequence
Descriptor Table accesses
Page Directory and Page Table accesses
XCHG instruction
An instruction with an allowable LOCK prefix
In order to ensure that locked operations appear on the bus and
are visible to the entire system, any data operands addressed
during a locked cycle that reside in the processor’s caches are
flushed and invalidated from the caches prior to the locked
operation. If the cache line is in the modified state, it is written
back and invalidated prior to the locked operation. Likewise,
any data read during a locked operation is not cached. The
processor negates LOCK# for at least one clock between
consecutive sequences of locked operations to allow the system
logic to arbitrate for the bus.
The processor asserts SCYC during misaligned locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
Basic Locked
Operation
184
Figure 74 on page 185 shows a pair of read-write bus cycles. It
represents a typical read-modify-write locked operation. The
processor asserts LOCK# off the same clock edge that it asserts
ADS# of the first bus cycle in the locked operation and holds it
asserted until the last expected BRDY# of the last bus cycle in
the locked operation is sampled asserted. (The processor
negates LOCK# off of the same clock edge.)
Bus Cycles
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AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Locked Write Cycle
Locked Read Cycle
ADDR DATA DATA DATA IDLE IDLE ADDR DATA DATA DATA IDLE IDLE ADDR
CLK
A[31:3]
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
SCYC
D[63:0]
BRDY#
Figure 74. Basic Locked Operation
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Locked Operation
with BOFF#
Intervention
23542A/0—September 2000
Figure 75 on page 187 shows BOFF# asserted within a locked
read-write pair of bus cycles. In this example, the processor
asserts LOCK# with ADS# to drive a locked memory read cycle
followed by a locked memory write cycle. During the locked
memory write cycle in this example, the processor samples
BOFF# asserted. The processor immediately aborts the locked
memory write cycle and floats all its bus-driving signals,
including LOCK#. The system logic or another bus master can
initiate an inquire cycle or drive a new bus cycle one clock edge
after the clock edge on which BOFF# is sampled asserted. If the
system logic drives a BOFF#-initiated inquire cycle and hits a
modified line, the processor performs a writeback cycle before
it restarts the locked cycle (the processor asserts LOCK# during
the writeback cycle).
In Figure 75, the processor immediately restarts the aborted
locked write cycle by driving the bus off the clock edge on
which BOFF# is sampled negated. The system logic must ensure
the processor results for interrupted and uninterrupted locked
cycles are consistent. That is, the system logic must guarantee
the memory accessed by the processor is not modified during
the time another bus master controls the bus.
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Locked Read Cycle
Aborted Write Cycle
Restart Write Cycle
CLK
A[31:3]
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
BOFF#
D[63:0]
BRDY#
Figure 75. Locked Operation with BOFF# Intervention
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Interrupt
Acknowledge
23542A/0—September 2000
In response to recognizing the system’s maskable interrupt
(INTR), the processor drives an interrupt acknowledge cycle at
t h e n e x t i n s t r u c t i o n b o u n d a ry. D u r i n g a n i n t e r r u p t
acknowledge cycle, the processor drives a locked pair of read
cycles as shown in Figure 76 on page 189. The first read cycle is
not functional, and the second read cycle returns the interrupt
number on D[7:0] (00h–FFh). Table 32 shows the state of the
signals during an interrupt acknowledge cycle.
Table 32. Interrupt Acknowledge Operation Definition
Processor Outputs
First Bus Cycle
Second Bus Cycle
D/C#
Low
Low
M/IO#
Low
Low
W/R#
Low
Low
BE[7:0]#
EFh
FEh (low byte enabled)
A[31:3]
0000_0000h
0000_0000h
D[63:0]
(ignored)
Interrupt number expected from interrupt controller on D[7:0]
The system logic can drive INTR either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks. To ensure it
is recognized, INTR must remain asserted until an interrupt
acknowledge sequence is complete.
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Interrupt Acknowledge Cycles
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
LOCK#
INTR
D[63:0]
Interrupt Number
KEN#
BRDY#
Figure 76. Interrupt Acknowledge Operation
Chapter 7
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
7.6
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Special Bus Cycles
The AMD-K6-2E+ processor drives special bus cycles that
include the following:
■
■
■
■
■
■
■
Stop grant
Enhanced power management
Flush acknowledge
Cache writeback invalidation
Halt
Cache invalidation
Shutdown
During all special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1.
BE[7:0]# and A[31:3] are driven to differentiate among the
special cycles, as shown in Table 33.
Note that the system logic must return BRDY# in response to all
processor special cycles.
Table 33. Encodings for Special Bus Cycles
BE[7:0]#
A[4:3]1
FBh
Special Bus Cycle
Cause
10b
Stop Grant
STPCLK# sampled asserted
BFh
00b
EPM Stop Grant2
A dword access is made to the EPM 16-byte I/O block and the GSBC bit of the
EPMR register is set to 1
EFh
00b
Flush Acknowledge
FLUSH# sampled asserted
F7h
00b
Writeback
WBINVD instruction
FBh
00b
Halt
HLT instruction
FDh
00b
Flush
INVD,WBINVD instruction
FEh
00b
Shutdown
Triple fault
Notes:
1. A[31:5] = 0
2. Supported on the low-power versions only.
Basic Special Bus
Cycle
Figure 77 on page 191 shows a basic special bus cycle.
The processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the
same clock edge that it asserts ADS#.
In this example, BE[7:0]# = FBh and A[31:3] = 0000_0000h,
which indicates that the special cycle is a halt special cycle (See
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AMD-K6™-2E+ Embedded Processor Data Sheet
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Table 33). A halt special cycle is generated after the processor
executes the HLT instruction.
If the processor samples FLUSH# asserted, it writes back any
L1 data cache and L2 cache lines that are in the modified state
and invalidates all lines in all caches. The processor then drives
a flush acknowledge special cycle.
If the processor executes a WBINVD instruction, it drives a
writeback special cycle after the processor completes
invalidating and writing back the cache lines.
Halt Cycle
CLK
A[31:3]
BE[7:0]#
A[4:3] = 00b
FBh
ADS#
M/IO#
D/C#
W/R#
BRDY#
Figure 77. Basic Special Bus Cycle (Halt Cycle)
Chapter 7
Bus Cycles
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Shutdown Cycle
23542A/0—September 2000
In Figure 78 on page 192, a shutdown (triple fault) occurs in the
first half of the waveform, and a shutdown special cycle follows
in the second half. The processor enters shutdown when an
interrupt or exception occurs during the handling of a double
fault (INT 8), which amounts to a triple fault. When the
processor encounters a triple fault, it stops its activity on the
bus and generates the shutdown special bus cycle (BE[7:0]# =
FEh).
The system logic must assert NMI, INIT, RESET, or SMI# to get
the processor out of the shutdown state.
Shutdown Occurs
(Triple Fault)
Shutdown Special Cycle
CLK
A[4:3] = 00b
A[31:3]
FEh
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
Figure 78. Shutdown Cycle
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AMD-K6™-2E+ Embedded Processor Data Sheet
Stop Grant and Stop
Clock States
Figure 79 on page 194 and Figure 80 on page 195 show the
processor transition from normal execution to the Stop Grant
state, then to the Stop Clock state, back to the Stop Grant state,
and finally back to normal execution. The series of transitions
begins when the processor samples STPCLK# asserted. On
recognizing a STPCLK# interrupt at the next instruction
retirement boundary, the processor performs the following
actions, in the order shown:
1. Its instruction pipelines are flushed.
2. All pending and in-progress bus cycles are completed.
3. The STPCLK# assertion is acknowledged by executing a
Stop Grant special bus cycle.
4. Its internal clock is stopped after BRDY# of the Stop Grant
special bus cycle is sampled asserted (if EWBE# is masked
off, then entry into the Stop Grant state is not affected by
EWBE#) and after EWBE# is sampled asserted.
5. The Stop Clock state is entered if the system logic stops the
bus clock CLK (optional).
STPCLK# is sampled as a level-sensitive input on every clock
edge but is not recognized until the next instruction boundary.
The system logic drives the signal either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks. STPCLK#
must remain asserted until recognized, which is indicated by
the completion of the Stop Grant special cycle.
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STPCLK# Sampled Asserted
Stop Grant Special Cycle
Stop Clock
CLK
A[4:3] = 10b
A[31:3]
FBh
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
CACHE#
STPCLK#
D[63:0]
KEN#
BRDY#
Figure 79. Stop Grant and Stop Clock Modes, Part 1
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Stop Clock
STPCLK# Sampled Negated Normal
Stop Grant State
(Re-entered after PLL stabilization)
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
CACHE#
STPCLK#
D[63:0]
KEN#
BRDY#
Figure 80. Stop Grant and Stop Clock Modes, Part 2
Chapter 7
Bus Cycles
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INIT-Initiated
Transition from
Protected Mode to
Real Mode
23542A/0—September 2000
INIT is typically asserted in response to a BIOS interrupt that
writes to an I/O port. This interrupt is often in response to a
Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar
to port 64h in the keyboard controller) that asserts INIT. INIT is
also used to support 80286 software that must return to Real
mode after accessing extended memory in Protected mode.
The assertion of INIT causes the processor to empty its
pipelines, initialize most of its internal state, and branch to
address FFFF_FFF0h—the same instruction execution starting
point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the floating-point state, the
MMX state, Model-Specific Registers (MSRs), the CD and NW
bits of the CR0 register, the time stamp counter, and other
specific internal resources.
Figure 81 on page 197 shows an example in which the operating
system writes to an I/O port, causing the system logic to assert
INIT. The sampling of INIT asserted starts an extended
microcode sequence that terminates with a code fetch from
FFFF_FFF0h, the reset location. INIT is sampled on every clock
edge but is not recognized until the next instruction boundary.
During an I/O write cycle, it must be sampled asserted a
minimum of three clock edges before BRDY# is sampled
asserted if it is to be recognized on the boundary between the
I/O write instruction and the following instruction. If INIT is
asserted synchronously, it can be asserted for a minimum of one
clock. If it is asserted asynchronously, it must have been
negated for a minimum of two clocks, followed by an assertion
of a minimum of two clocks.
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INIT Sampled Asserted
CLK
Code Fetch
FFFF_FFF0h
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
INIT
Figure 81. INIT-Initiated Transition from Protected Mode to Real Mode
Chapter 7
Bus Cycles
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Chapter 7
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8
Power-on Configuration and Initialization
On power-on the system logic must reset the AMD-K6-2E+
processor by asserting the RESET signal. When the processor
samples RESET asserted, it immediately flushes and initializes
all internal resources and its internal state, including its
pipelines and caches, the floating-point state, the MMX and
3DNow! states, and all registers. Then the processor jumps to
address FFFF_FFF0h to start instruction execution.
8.1
FLUSH#
Signals Sampled During the Falling Transition of RESET
FLUSH# is sampled on the falling transition of RESET to
determine if the processor begins normal instruction execution
or enters Three-State Test mode.
■
■
BF[2:0]
Chapter 8
If FLUSH# is High during the falling transition of RESET,
the processor unconditionally runs its Built-In Self Test
(BIST), performs the normal reset functions, then jumps to
address FFFF_FFF0h to start instruction execution. (See
“Built-In Self-Test (BIST)” on page 251 for more details.)
If FLUSH# is Low during the falling transition of RESET,
the processor enters Three-State Test mode. (See
“Three-State Test Mode” on page 252 and “FLUSH# (Cache
Flush)” on page 112 for more details.)
The in t er n a l op erat i n g f re q u e n cy o f t h e p roce s so r is
determined by the state of the bus frequency signals BF[2:0]
when they are sampled during the falling transition of RESET.
The frequency of the CLK input signal is multiplied internally
by a ratio defined by BF[2:0]. (See “BF[2:0] (Bus Frequency)”
on page 101 for the processor-clock to bus-clock ratios.)
Power-on Configuration and Initialization
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RESET Requirements
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and VCC
reach specification. (See “CLK Switching Characteristics” on
page 296 for clock specifications. “Electrical Data” beginning
on page 285 for VCC specifications.)
D u r i n g a wa r m re s e t w h i l e C L K a n d V C C a re w i t h i n
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
8.3
State of Processor After RESET
Output Signals
Table 34 show s the state of all processor outputs and
bidirectional signals immediately after RESET is sampled
asserted.
Table 34. Output Signal State After RESET
Signal
State
Signal
State
Floating
LOCK#
High
ADS#, ADSC#
High
M/IO#
Low
APCHK#
High
PCD
Low
BE[7:0]#
Floating
PCHK#
High
A[31:3], AP
BREQ
Low
PWT
Low
CACHE#
High
SCYC
Low
D/C#
Low
SMIACT#
High
D[63:0], DP[7:0]
Floating
TDO
Floating
FERR#
High
VCC2DET
Low
HIT#
High
VCC2H/L#
Low
HITM#
High
VID[4:0]1
01010b
HLDA
Low
W/R#
Low
Notes:
1. Supported on low-power versions only.
Registers
200
Table 35 on page 201 shows the state of all architecture
registers and Model-Specific Registers (MSRs) after the
processor has completed its initialization due to the recognition
of the assertion of RESET.
Power-on Configuration and Initialization
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
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Table 35. Register State After RESET
Register
State (hex)
GDTR
base:0000_0000h limit:0FFFFh
IDTR
base:0000_0000h limit:0FFFFh
TR
0000h
LDTR
0000h
EIP
FFFF_FFF0h
EFLAGS
0000_0002h
EAX1
0000_0000h
EBX
0000_0000h
ECX
EDX
0000_0000h
2
0000_059Xh
ESI
0000_0000h
EDI
0000_0000h
EBP
0000_0000h
ESP
0000_0000h
CS
F000h
SS
0000h
DS
0000h
ES
0000h
FS
0000h
GS
0000h
3
FPU Stack R7–R0
Chapter 8
0000_0000_0000_0000_0000h
FPU Control Word3
0040h
FPU Status Word3
0000h
FPU Tag Word3
5555h
FPU Instruction Pointer3
0000_0000_0000h
FPU Data Pointer3
0000_0000_0000h
FPU Opcode Register3
000_0000_0000b
CR04
6000_0010h
CR2
0000_0000h
CR3
0000_0000h
CR4
0000_0000h
DR7
0000_0400h
DR6
FFFF_0FF0h
DR3
0000_0000h
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Table 35. Register State After RESET (continued)
Register
State (hex)
DR2
0000_0000h
DR1
0000_0000h
DR0
0000_0000h
MCAR3
0000_0000_0000_0000h
MCTR3
0000_0000_0000_0000h
TR123
0000_0000_0000_0000h
TSC3
0000_0000_0000_0000h
EFER3
0000_0000_0000_0002h
STAR3
0000_0000_0000_0000h
WHCR3
0000_0000_0000_0000h
UWCCR3
0000_0000_0000_0000h
PSOR5
0000_0000_0000_01SBh
PFIR3,5
0000_0000_0000_0000h
EPMR3,6
0000_0000_0000_0000h
Notes:
1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful.
If EAX is non-zero, BIST failed.
2. EDX contains the AMD-K6-2E+ processor signature, where X indicates the processor Stepping ID.
3. The contents of these registers are preserved following the recognition of INIT.
4. The CD and NW bits of CR0 are preserved following the recognition of INIT.
5. “S” represents the Stepping. “B” represents PSOR[3:0], where PSOR[3] equals 0, and PSOR[2:0] is
equal to the value of the BF[2:0] signals sampled during the falling transition of RESET.
6. Supported on low-power versions only.
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8.4
State of Processor After INIT
The recognition of the assertion of INIT causes the processor to
empty its pipelines, to initialize most of its internal state, and to
branch to address FFFF_FFF0h—the same instruction
execution starting point used after RESET.
Unlike RESET, the processor preserves the contents of its
caches, the floating-point state, the MMX and 3DNow! states,
MSRs, and the CD and NW bits of the CR0 register.
The edge-sensitive interrupts FLUSH# and SMI# are sampled
and preserved during the INIT process and are handled
accordingly after the initialization is complete. However, the
processor resets any pending NMI interrupt upon sampling
INIT asserted.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from Protected mode back to Real mode.
Chapter 8
Power-on Configuration and Initialization
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Chapter 8
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
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9
Cache Organization
The following sections describe the basic architecture and
resources of the AMD-K6-2E+ processor internal caches.
The performance of the AMD-K6-2E+ processor is enhanced by
writeback level-one (L1) and level-two (L2) caches.
■
The L1 cache is organized as separate 32-Kbyte instruction
and data caches, each with two-way set associativity.
■
The L2 cache is 128 Kbytes, and is organized as a unified,
four-way set-associative cache (See Figure 82 on page 206).
The cache line size is 32 bytes, and lines are fetched from
external memory using an efficient pipelined burst transaction.
As the L1 instruction cache is filled from the L2 cache or from
external memory, each instruction byte is analyzed for
instruction boundaries using predecode logic. Predecoding
annotates each instruction byte in the L1 instruction cache with
information that later enables the decoders to efficiently
decode multiple instructions simultaneously.
Translation lookaside buffers (TLB) are used in conjunction
with the L1 cache to translate linear addresses to physical
addresses. The L1 instruction cache is associated with a
64-entry TLB, while the L1 data cache is associated with a
128-entry TLB.
Chapter 9
Cache Organization
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32-Kbyte L1 Instruction Cache
Tag
RAM
Way 0
State Tag
Bit RAM
Way 1
State
Bit
64-Entry TLB
System Bus
Interface Unit
Processor
Core
Pre-Decode Instruction Cache
128-Entry TLB
Tag
RAM
Way 0
MESI Tag
Bits RAM
Way 1
MESI
Bits
32-Kbyte L1 Data Cache
Tag
RAM
Way 0
MESI Tag
Bits RAM
Way 1
MESI Tag
Bits RAM
Way 2
MESI Tag
Bits RAM
Way 3
MESI
Bits
128-Kbyte L2 Cache
Figure 82. L1 and L2 Cache Organization for the AMD-K6™-2E+ Processor
The processor cache design takes advantage of a sectored
organization (See Figure 83). Each sector consists of 64 bytes
configured as two 32-byte cache lines. The two cache lines of a
sector share a common tag but have separate MESI (modified,
exclusive, shared, invalid) bits that track the state of each cache
line.
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AMD-K6™-2E+ Embedded Processor Data Sheet
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L1 Instruction Cache Line
Tag
Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits
Address Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits
........
........ Byte 0 Predecode Bits 1 MESI Bit
........
........ Byte 0 Predecode Bits 1 MESI Bit
L1 Data Cache Line and L2 Cache Line
Tag
Address
Cache Line 0
Byte 31
Byte 30
........
........
Byte 0
2 MESI Bits
Cache Line 1
Byte 31
Byte 30
........
........
Byte 0
2 MESI Bits
Note: L1 instruction-cache lines have only two coherency states
(valid or invalid) rather than the four MESI coherency
states of L1 data-cache and L2 cache lines. Only two states
are needed for the L1 instruction cache because these lines
are read-only.
Figure 83. L1 Cache Sector Organization
9.1
MESI States in the L1 Data Cache and L2 Cache
The state of each line in the caches is tracked by the MESI bits.
The coherency of these states or MESI bits is maintained by
internal processor snoops and external inquire cycles by the
system logic. The following four states are defined for the L1
data cache and the L2 cache:
■
■
■
■
Chapter 9
Modified—This line has been modified and is different from
external memory.
Exclusive—In general, an exclusive line in the L1 data cache
or the L2 cache is not modified and is the same as external
memory. The exception is the case where a line exists in the
modified state in the L1 data cache and also resides in the
L2 cache. By design, the line in the L2 cache must be in the
exclusive state.
Shared—If a cache line is in the shared state it means that
the same line can exist in more than one cache system.
Invalid—The information in this line is not valid.
Cache Organization
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9.2
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Predecode Bits
Decoding x86 instructions is particularly difficult because the
instructions vary in length, ranging from 1 to 15 bytes long.
Predecode logic supplies the predecode bits associated with
each instruction byte.
Predecode bits indicate the number of bytes to the start of the
next x86 instruction. The predecode bits are passed with the
instruction bytes to the decoders where they assist with parallel
x86 instruction decoding. The predecode bits use memory
separate from the 32-K byte L1 instruction cache. The
predecode bits are stored in an extended L1 instruction cache
alongside each x86 instruction byte as shown in Figure 83 on
page 207.
The L2 cache does not store predecode bits. As an instruction
cache line is fetched from the L2 cache, the predecode bits are
generated and stored alongside the cache line in the L1
instruction cache in the same manner as if the cache line were
fetched from the processor’s system bus.
9.3
Cache Operation
The operating modes for the caches are configured by software
using the not writethrough (NW) and cache disable (CD) bits of
control register 0 (CR0 bits 29 and 30, respectively). These bits
are used in all operating modes.
When the CD and NW bits are both set to 0, the cache is fully
enabled. This is the standard operating mode for the cache.
If a L1 cache read miss occurs, the processor determines if
the read hits the L2 cache, in which case the cache line is
supplied from the L2 cache to the L1 cache. If a read misses
both the L1 and the L2 caches, a line fill (32-byte burst read)
on the system bus occurs in order to fetch the cache line. The
cache line is then filled in both the L1 and the L2 caches.
Write hits to the L1 and L2 caches are updated, while write
misses and writes to shared lines cause external memory
updates. Refer to Table 39 on page 221 for a summary of
cache read and write cycles and the effect of these
operations on the cache MESI state.
Note: A write allocate operation can modify the behavior of write
misses to the caches. See “Write Allocate” on page 215.
■
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■
■
■
The AMD-K6-2E+ processor does not enforce any rules of
inclusion or exclusion as part of the protocol defined for the
L1 and L2 caches. However, there are certain restrictions
imposed by design on the allowable MESI states of a cache
line that exists in both the L1 cache and the L2 cache. Refer
to Table 40 on page 225 for a list of the valid cache-line
states allowed.
When CD is set to 0 and NW is set to 1, an invalid mode of
operation exists that causes a general protection fault to
occur.
When CD is set to 1 (disabled) and NW is set to 0, the cache
fill mechanism is disabled but the contents of the cache are
still valid. The processor reads from the caches if the read
hits the L1 or the L2 cache. If a read misses both the L1 and
the L2 caches, a line fill does not occur on the system bus.
Write hits to the L1 or L2 cache are updated, while write
misses and writes to shared lines cause external memory
updates. If PWT is driven Low and WB/WT# is sampled
High, a write hit to a shared line changes the cache-line state
to exclusive.
When the CD and NW bits are both set to 1, the cache is fully
disabled. Even though the cache is disabled, the contents
are not necessarily invalid. The processor reads from the
caches if the read hits the L1 or the L2 cache. If a read
misses both the L1 and the L2 caches, a line fill does not
occur on the system bus. If a write hits the L1 or the L2
cache, the cache is updated but an external memory update
does not occur. If a cache line is in the exclusive state during
a write hit, the cache-line state is changed to modified.
Cache lines in the shared state remain in the shared state
after a write hit. Write misses access external memory
directly.
The operating system can control the cacheability of a page.
The paging mechanism is controlled by CR3, the Page Directory
Entry (PDE), and the Page Table Entry (PTE). Within CR3,
PDE, and PTE are Page Cache Disable (PCD) and Page
Writethrough (PWT) bits. The values of the PCD and PWT bits
used in Table 36 on page 210 and Table 37 on page 210 are
taken from either the PTE or PDE. For more information on
PCD and PWT, see “PCD (Page Cache Disable)” on page 124
and “PWT (Page Writethrough)” on page 126, respectively.
Chapter 9
Cache Organization
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Table 36 describes how the PWT signal is driven based on the
values of the PWT bits and the PG bit of CR0.
Table 36. PWT Signal Generation
PWT Bit1
PG Bit of CR0
PWT Signal
1
1
High
0
1
Low
1
0
Low
0
0
Low
Notes:
1. PWT is taken from PTE or PDE.
Table 37 describes how the PCD signal is driven based on the
values of the CD bit of CR0, the PCD bits, and the PG bit of
CR0.
Table 37. PCD Signal Generation
CD Bit of CR0
PCD Bit1
PG Bit of CR0
PCD Signal
1
X
X
High
0
1
1
High
0
0
1
Low
0
1
0
Low
0
0
0
Low
Notes:
1. PCD is taken from PTE or PDE.
Table 38 describes how the CACHE# signal is driven based on
the cycle type, the CI bit of TR12, the PCD signal, and the
UWCCR model-specific register.
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Table 38. CACHE# Signal Generation
Cycle Type
CI Bit of TR12
PCD Signal
Access Within WC/UC Range1
CACHE#
Writebacks
X
X
X
Low
Unlocked Reads
0
0
0
Low
Locked Reads
X
X
X
High
Single Writes
X
X
X
High
Any Cycle Except Writebacks
1
X
X
High
Any Cycle Except Writebacks
X
1
X
High
Any Cycle Except Writebacks
X
X
1
High
Notes:
1. WC and UC refer to Write-Combining and Uncacheable Memory Ranges as defined in the UWCCR.
Cache-Related Signals
Complete descriptions of the signals that control cacheability
and cache coherency are given on the following pages:
■
■
■
■
■
■
■
■
■
■
9.4
Cache Disabling and Flushing
L1 and L2 Cache
Disabling
To completely disable all accesses to the L1 and the L2 caches,
the CD bit must be set to 1 and the caches must be completely
flushed. There are three different methods for flushing the
caches. The first method relies on the system logic and the
other two methods rely on software.
■
Chapter 9
CACHE#—page 105
EADS#—page 109
FLUSH#—page 112
HIT#—page 113
HITM#—page 113
INV—page 118
KEN#—page 119
PCD—page 124
PWT—page 126
WB/WT#—page 139
For the system logic to flush the caches, the processor must
sample FLUSH# asserted. In this method, the processor
writes back any L1 data cache and L2 cache lines that are in
Cache Organization
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the modified state, invalidates all lines in all caches, and
then executes a flush acknowledge special cycle (See
Table 24 on page 142).
■
■
L2 Cache Disabling
The second method for flushing the caches is for software to
execute the WBINVD instruction, which causes all modified
lines to first be written back to memory, then marks all
cache lines as invalid. Alternatively, if writing modified lines
back to memory is not necessary, the INVD instruction can
be used to invalidate all cache lines.
The third method for flushing the caches is to make use of
the Page Flush/Invalidate Register (PFIR), which allows
cache invalidation and optional flushing of a specific 4Kbyte page from the linear address space (see “Page
Flush/Invalidate Register (PFIR)” on page 223). Unlike the
previous two methods of flushing the caches, this particular
method requires the software to be aware of which specific
pages must be flushed and invalidated.
The L2 cache in the AMD-K6-2E+ processor can be completely
disabled by setting the L2 Disable (L2D) bit (EFER[4]) to 1 (see
“Extended Feature Enable Register (EFER)” on page 47). If
disabled in this manner, the processor does not access the L2
cache for any purpose, including allocations, read hits, write
hits, snoops, inquire cycles, flushing, and read/write attempts
by means of the L2AAR. (See “L2 Cache Testing” on page 213.)
The L1 cache operation is not affected by disabling the L2
cache.
The L2D bit is provided for debug and testing purposes only. For
normal operation and maximum performance, this bit must be
set to 0, which is the default setting following reset.
The AMD-K6-2E+ processor does not provide a method for
disabling the L1 cache while the L2 cache remains enabled.
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9.5
L2 Cache Testing
The AMD-K6-2E+ processor provides the L2AAR MSR that
allows for direct access to the L2 cache and L2 tag arrays. For
more detailed information, refer to “L2 Cache and Tag Array
Testing” on page 264.
9.6
Cache-Line Fills
The processor performs a cache-line fill for any area of system
memory defined as cacheable. If an area of system memory is
not explicitly defined as uncacheable by the software or system
logic, or implicitly treated as uncacheable by the processor,
then the memory access is assumed to be cacheable.
Software can prevent caching of certain pages by setting the
PCD bit in the PDE or PTE. Additionally, software can define
regions of memory as uncacheable or write combinable by
programming the MTRRs in the UWCCR MSR (see “Memory
Type Range Registers” on page 231). Write-combinable
memory is defined as uncacheable.
The system logic also has control of the cacheability of bus
cycles. If it determines the address is not cacheable, system
logic negates the KEN# signal when asserting the first BRDY#
or NA# of a cycle.
The processor does not cache certain memory accesses such as
locked operations. In addition, the processor does not cache
PDE or PTE memory reads in the L1 cache (referred to as page
table walks). However, page table walks are cached in the L2
cache if the PDE or PTE is determined to be cacheable.
When the processor needs to read memory, the processor drives
a read cycle onto the bus. If the cycle is cacheable, the
processor asserts CACHE#. If the cycle is not cacheable, a
non-burst, single-transfer read takes place. The processor waits
for the system logic to return the data and assert a single
BRDY# (See Figure 60 on page 159). If the cycle is cacheable,
the processor executes a 32-byte burst read cycle. The processor
expects a total of four BRDY# signals for a burst read cycle to
take place (See Figure 62 on page 163).
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Cache-line fills initiate 32-byte burst read cycles from memory
on the system bus for the L1 instruction cache and the L1 data
cache. All L1 cache-line fills supplied from the system bus are
also filled in the L2 cache.
9.7
Cache-Line Replacements
As programs execute and task switches occur, some cache lines
eventually require replacement.
When a cache miss occurs in the L1 cache, the required cache
line is filled from either the L2 cache, if the cache line is
present (L2 cache hit), or from external memory, if the cache
line is not present (L2 cache miss). If the cache line is filled
from external memory, the cache line is filled in both the L1
and the L2 caches.
Two forms of cache misses and associated cache fills can take
place—a tag-miss cache fill and a tag-hit cache fill.
■
■
In the case of a tag-miss cache fill, the level-one cache miss is
due to a tag mismatch, in which case the required cache line
is filled either from the level-two cache or from external
memory, and the level-one cache line within the sector that
was not required is marked as invalid.
In the case of a tag-hit cache fill, the address matches the
tag, but the requested cache line is marked as invalid. The
required level-one cache line is filled from the level-two
cache or from external memory, and the level-one cache line
within the sector that is not required remains in the same
cache state.
If a L1 data-cache line being filled replaces a modified line, the
modified line is written back to the L2 cache if the cache line is
present (L2 cache hit). By design, if a cache line is in the
modified state in the L1 cache, this cache line can only exist in
the L2 cache in the exclusive state. During the writeback, the
L2 cache-line state is changed from exclusive to modified, and
the writeback does not occur on the system bus. If the
replacement writeback does not hit the L2 cache (L2 cache
miss), then the modified L1 cache line is written back on the
system bus, and the L2 cache is not updated. If the other cache
line in this sector is in the modified state, it is also written back
in the same manner.
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L1 instruction-cache lines and L2 cache lines are replaced using
a Least Recently Used (LRU) algorithm. If a line replacement is
required, lines are replaced when read cache misses occur.
The L1 data cache uses a slightly different approach to line
replacement. If a miss occurs, and a replacement is required,
lines are replaced by using a Least Recently Allocated (LRA)
algorithm.
9.8
Write Allocate
Write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the L1 data cache. If the line does
not exist in the L2 cache, the processor performs a 32-byte burst
read cycle on the system bus to fetch the data-cache line
addressed by the pending write cycle. If the line does exist in
the L2 cache, the data is supplied directly from the L2 cache, in
which case a system bus cycle is not executed. The data
associated with the pending write cycle is merged with the
recently-allocated data-cache line and stored in the processor’s
L1 data cache. If the data-cache line was fetched from memory
(because of a L2 cache miss), the data is stored, without
modification, in the L2 cache. The final MESI state of the cache
lines depends on the state of the WB/WT# and PWT signals
during the burst read cycle and the subsequent L1 data cache
write hit (See Table 39 on page 221 to determine the cache-line
states and the access types following a cache write miss). If the
L1 data cache line is stored in the modified state, then the same
cache line is stored in the L2 cache in the exclusive state. If the
L1 data cache line is stored in the shared state, then the same
cache line is stored in the L2 cache in the shared state.
If a data-cache line fetch from memory is attempted because
the write allocate misses the L2 cache, and KEN# is sampled
negated, the processor does not perform an allocation. In this
case, the pending write cycle is executed as a single write cycle
on the system bus.
During write allocates that miss the L2 cache, a 32-byte burst
read cycle is executed in place of a non-burst write cycle. While
the burst read cycle generally takes longer to execute than the
non-burst write cycle, performance gains are realized on
subsequent write cycle hits to the write-allocated cache line.
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Due to the nature of software, memory accesses tend to occur in
proximity of each other (principle of locality). The likelihood of
additional write hits to the write-allocated cache line is high.
Write allocates that hit the L2 cache increase performance by
avoiding accesses to the system bus.
The following is a description of three mechanisms by which the
AMD-K6-2E+ processor performs write allocations. A write
al lo c at e is p e r fo rm e d wh en a ny o n e o r m o re of t h e se
mechanisms indicates that a pending write is to a cacheable
area of memory.
Write to a Cacheable
Page
Every time the processor completes a L1 cache line fill, the
address of the page in which the cache line resides is saved in
the Cacheability Control Register (CCR). The page address of
subsequent write cycles is compared with the page address
stored in the CCR. If the two addresses are equal, then the
processor performs a write allocate because the page has
already been determined to be cacheable.
When the processor performs a L1 cache line fill from a
different page than the address saved in the CCR, the CCR is
updated with the new page address.
Write to a Sector
If the address of a pending write cycle matches the tag address
of a valid L1 cache sector, but the addressed cache line within
the sector is marked invalid (a sector hit but a cache line miss),
then the processor performs a write allocate. The pending write
cycle is determined to be cacheable because the sector hit
indicates the presence of at least one valid cache line in the
sector. The two cache lines within a sector are guaranteed by
design to be within the same page.
Write Allocate Limit
The AMD-K6-2E+ processor uses two mechanisms that are
programmable within the Write Handling Control Register
(WHCR) to enable write allocations for write cycles that
address a definable area, or a special 1-Mbyte memory area.
The WHCR contains two fields —the Write Allocate Enable
Limit (WAELIM) field, and the Write Allocate Enable
15-to-16-Mbyte (WAE15M) bit (see Figure 84).
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63
32 31
22 21
WAELIM
17 16 15
0
W
A
E
1
5
M
Reserved
Symbol
WAELIM
WAE15M
Description
Bits
Write Allocate Enable Limit
31-22
Write Allocate Enable 15-to-16-Mbyte 16
Notes: Hardware RESET initializes this MSR to all zeros.
Figure 84. Write Handling Control Register (WHCR)
Write Allocate Enable Limit Field. The WAELIM field is 10 bits wide.
This field, multiplied by 4 Mbytes, defines an upper memory
limit. Any pending write cycle that misses the L1 cache and that
addresses memory below this limit causes the processor to
perform a write allocate (assuming the address is not within a
range where write allocates are disallowed). Write allocate is
disabled for memory accesses at and above this limit unless the
processor determines a pending write cycle is cacheable by
means of one of the other write allocate mechanisms—“Write
to a Cacheable Page” and “Write to a Sector.” The maximum
value of this limit is ((210 –1) · 4 Mbytes) = 4092 Mbytes. When
all the bits in this field are set to 0, all memory is above this
limit and write allocates due to this mechanism is disabled
(even if all bits in the WAELIM field are set to 0, write allocates
can still occur due to the “Write to a Cacheable Page” and
“Write to a Sector” mechanisms).
Write Allocate Enable 15-to-16-Mbyte Bit. The Write Allocate Enable
1 5-t o -1 6 -M by t e ( WA E1 5 M) b it i s u se d t o e n able w r it e
allocations for memory write cycles that address the 1 Mbyte of
memory between 15 Mbytes and 16 Mbytes. This bit must be set
to 1 to allow write allocate in this memory area. This bit is
provided t o account for a small number of uncommon
memory-mapped I/O adapters that use this particular memory
address space. If the system contains one of these peripherals,
the bit should be set to 0 (even if the WAE15M bit is set to 0,
write allocates can still occur between 15 Mbytes and 16
Mbytes due to the “Write to a Cacheable Page” and “Write to a
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Sector” mechanisms). The WAE15M bit is ignored if the value
in the WAELIM field is set to less than 16 Mbytes.
By definition a write allocate is not performed in the memory
area between 640 Kbytes and 1 Mbyte unless the processor
determines a pending write cycle is cacheable by means of one
of the other write allocate mechanisms—“Write to a Cacheable
Page” and “Write to a Sector.” It is not considered safe to
perform write allocations between 640 Kbytes and 1 Mbyte
(000A_0000h to 000F_FFFFh) because it is considered a
noncacheable region of memory.
If a memory region is defined as w rite combinable or
uncacheable by a MTRR, write allocates are not performed in
that region.
Write Allocate Logic
Mechanisms and
Conditions
Figure 85 shows the logic flow for all the mechanisms involved
with write allocate for memory bus cycles. The left side of the
diagram (the text) describes the conditions that need to be true
in order for the value of that line to be a 1. Items 1 to 4 of the
diagram are related to general cache operation and items 5 to
10 are related to the write allocate mechanisms.
Fo r m o re i n f o r m a t i o n a b o u t w r i t e a l l o c a t e , s e e t h e
Implementation of Write Allocate in the K86™ Processors
Application Note, order# 21326.
Perform
Write Allocate
1) CD Bit of CR0
2) PCD Signal
3) CI Bit of TR12
4) UC or WC
5) Write to Cacheable Page (CCR)
6) Write to a Sector
7) Less Than Limit (WAELIM)
8) Between 640 Kbytes and 1 Mbyte
9) Between 15–16 Mbytes
10) Write Allocate Enable 15–16 Mbyte (WAE15M)
Figure 85. Write Allocate Logic Mechanisms and Conditions
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The following list describes the corresponding items in Figure
85:
1. CD Bit of CR0—When the cache disable (CD) bit within control register 0 (CR0) is set to 1, the cache fill mechanism for
both reads and writes is disabled and write allocate does
not occur.
2. PCD Signal—When the PCD (page cache disable) signal is
driven High, caching for that page is disabled, even if KEN#
is sampled asserted, and write allocate does not occur.
3. CI Bit of TR12—When the cache inhibit bit of Test Register
12 is set to 1, L1 and L2 cache fills are disabled and write
allocate does not occur.
4. UC or WC—If a pending write cycle addresses a region of
memory defined as write combinable or uncacheable by an
MTRR, write allocates are not performed in that region.
5. Write to a Cacheable Page (CCR)—A write allocate is
performed if the processor knows that a page is cacheable.
The CCR is used to store the page address of the last L1
cache fill for a read miss. See “Write to a Cacheable Page”
on page 216 for a detailed description of this condition.
6. Write to a Sector—A write allocate is performed if the
address of a pending write cycle matches the tag address of
a valid L1 cache sector but the addressed cache line within
the sector is invalid. See “Write to a Sector” on page 216 for
a detailed description of this condition.
7. Less Than Limit (WAELIM)—The write allocate limit
mechanism determines if the memory area being addressed
is less than the limit set in the WAELIM field of WHCR. If
the address is less than the limit, write allocate for that
memory address is performed as long as conditions 8
through 10 do not prevent write allocate (even if conditions
8 and 10 attempt to prevent write allocate, condition 5 or 6
allows write allocate to occur).
8. Between 640 Kbytes and 1 Mbyte —Write allocate is not
performed in the memory area between 640 Kbytes and 1
Mbyte. It is not considered safe to perform write allocations
between 640 Kbytes and 1 Mbyte (000A_0000h to
000F_FFFFh) because this area of memory is considered a
noncacheable region of memory (even if condition 8
attempts to prevent write allocate, condition 5 or 6 allows
write allocate to occur).
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9. Between 15–16 Mbytes—If the address of a pending write
cycle is in the 1 Mbyte of memory between 15 Mbytes and
16 Mbytes, and the WAE15M bit is set to 1, write allocate
for this cycle is enabled.
10. Write Allocate Enable 15–16 Mbytes (WAE15M)—This
condition is associated with the Write Allocate Limit
mechanism and affects write allocate only if the limit
specified by the WAELIM field is greater than or equal to
16 Mbytes. If the memory address is between 15 Mbytes and
16 Mbytes, and the WAE15M bit in the WHCR is set to 0,
write allocate for this cycle is disabled (even if condition 10
attempts to prevent write allocate, condition 5 or 6 allows
write allocate to occur).
9.9
Prefetching
Hardware
Prefetching
The AMD-K6-2E+ processor conditionally performs cache
prefetching, which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
burst read cycles occurring back-to-back or, if allowed, as
p i p e l in e d cy c le s . The b u rst re a d cy c l e s d o n o t o c c u r
back-to-back (wait states occur) if the processor is not ready to
start a new cycle, if higher priority data read or write requests
exist, or if NA# (next address) was sampled negated. Wait states
can also exist between burst cycles if the processor samples
AHOLD or BOFF# asserted.
Software Prefetching
The 3DNow! technology includes an instruction called
PREFETCH that allows a cache line to be prefetched into the
L1 data cache and the L2 cache. Unlike prefetching under
hardware control, software prefetching only fetches the cache
line specified by the operand of the PREFETCH instruction,
and does not attempt to fetch the other cache line in the sector.
The PREFETCH instruction format is defined in Table 15,
“3DNow!™ Instructions,” on page 89. For more detailed
information, see the 3DNow!™ Technology Manual, order#
21928.
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9.10
Cache States
Table 39 shows all the possible cache-line states before and
after program-generated accesses to individual cache lines.
Table 39. L1 and L2 Cache States for Read and Write Accesses
Type
Read Miss L1,
Read Miss L2
Cache
Read
Read Hit L1
Read Miss L1,
Read Hit L2
Write Miss L1
Write Miss L2
Write Hit L1
Cache
Write
Write Miss L1
Write Hit L2
Cache State Before Access1
L1
L2
I
I
Cache State After Access
MESI State2
Access Type
L1
Single read from bus
L2
I
3
I
S or E
E
S
M
E
S
M
S or E4
–
–
–
E
S
E
Fill L1
E5
M5
I
Single write to bus6
I
I
I
I
M8
E8
I
I
S9
S9
S
I
S or E4
I
S
S
S or E4
S or E4
E or M
–
Burst read from bus, fill L1 and L2, write to L17
Burst read from bus, fill L1 and L2, write to
L1 and L2, single write to bus7
Write to L1,
single write to bus
Write to L1 and L2,
single write to bus
Write to L1
M
–
I
E
Write to L26
I
M
I
S
Write to L2, single write to bus6
I
S or E4
I
M
Write to L26
I
M
I
I
E
S
M
I
I
I
–
–
–
E
S
M
Burst read from bus, fill L1 and L2
–
–
–
Fill L1
Fill L1
Fill L1
I
M
I
I
E
7
4
M
Fill L1, write to L1
7
I
S
Write to L2, single write to bus
I
M
Fill L1, write to L17
E
4
S or E
S or E4
M
E
Notes:
1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and
are treated as “valid” states.
2. The final MESI state assumes that the state of the WB/WT# signal remains the same for all accesses to a particular cache line.
3. If CACHE# is driven Low and KEN# is sampled asserted.
4. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. If PWT is driven High or
WB/WT# is sampled Low, the line is cached in the shared (writethrough) state.
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5. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in
the modified state in the L2 cache.
6. Assumes the write allocate conditions as specified in “Write Allocate” on page 215 are not met.
7. Assumes the write allocate conditions as specified in “Write Allocate” on page 215 are met.
8. Assumes PWT is driven Low and WB/WT# is sampled High.
9. Assumes PWT is driven High or WB/WT# is sampled Low.
— Not applicable or none.
9.11
Cache Coherency
Different ways exist to maintain coherency between the system
memory and cache memories. Inquire cycles, internal snoops,
FLUSH#, WBINVD, INVD, and line replacements all prevent
inconsistencies between memories.
Inquire Cycles
Inquire cycles are bus cycles initiated by system logic that
ensure coherency between the caches and main memory. In
systems with multiple bus masters, system logic maintains
cache coherency by driving inquire cycles to the processor.
System logic initiates inquire cycles by asserting AHOLD,
BOFF#, or HOLD to obtain control of the address bus and then
driving EADS#, INV (optional), and an inquire address
(A[31:5]).
This type of bus cycle causes the processor to compare the tags
for its L1 instruction and L1 data caches, and L2 cache, with the
inquire address.
■
■
■
■
If there is a hit to a shared or exclusive line in the L1 data
cache or the L2 cache, or a valid line in the L1 instruction
cache, the processor asserts HIT#.
If the compare hits a modified line in the L1 data cache or
the L2 cache, the processor asserts HIT# and HITM#. If
HITM# is asserted, the processor writes the modified line
back to memory.
If INV was sampled asserted with EADS#, a hit invalidates
the line.
If INV was sampled negated with EADS#, a hit leaves the
line in the shared state or transitions it from the exclusive or
modified state to the shared state.
Table 40 on page 225 lists valid combinations of MESI states
permitted for a cache line in the L1 and L2 caches, and shows
the effects of inquire cycles performed with INV equal to 0
(non-invalidating) and INV equal to 1 (invalidating).
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Internal Snooping
Internal snooping is initiated by the processor (rather than
system logic) during certain cache accesses. It is used to
maintain coherency between the L1 instruction cache and the
L1 data cache.
The processor automatically snoops its L1 instruction cache
during read or write misses to its L1 data cache, and it snoops
its L1 data cache during read misses to its L1 instruction cache.
The L2 cache is not snooped during misses to either of the L1
caches. Table 41 on page 226 summarizes the actions taken
during this internal snooping.
If an internal snoop hits its target, the processor does the
following:
■
■
L1 Data Cache Snoop During an L1 Instruction-cache Read
Miss—If modified, the line in the L1 data cache is written
back. If the writeback hits the L2 cache, the cache line is
stored in the L2 cache in the modified state and no
writeback occurs on the system bus. If the writeback misses
the L2 cache, the cache line is written back on the system
bus to external memory. Regardless of its state, the L1
data-cache line is invalidated and the L1 instruction cache
performs a read from either the L2 cache (if a L2 hit occurs)
or external memory (if a L2 miss occurs).
L1 Instruction Cache Snoop During an L1 Data Cache
Miss—The line in the instruction cache is marked invalid,
and the L1 data-cache read or write is performed as defined
in Table 39 on page 221.
FLUSH#
In response to sampling FLUSH# asserted, the processor writes
back any L1 data cache lines and L2 cache lines that are in the
modified state and then marks all lines in the L1 instruction
cache, the L1 data cache, and the L2 cache as invalid.
Page Flush/Invalidate
Register (PFIR)
The AMD-K6-2E+ processor contains the Page Flush/Invalidate
Register (PFIR) that allows cache invalidation and optional
flushing of a specific 4-Kbyte page from the linear address
space (see Figure 86 on page 224). When the PFIR is written to
(using the WRMSR instruction), the invalidation and,
optionally, the flushing begins. The total amount of cache in the
AMD-K6-2E+ processor is 128 Kbytes. Using this register can
result in a much lower cycle count for flushing particular pages
versus flushing the entire cache.
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32 31
63
12 11
LINPAGE
9 8 7
P
F
1 0
F
/
I
Reserved
Symbol
LINPAGE
PF
F/I
Description
20-bit Linear Page Address
Page Fault Occurred
Flush/Invalidate Command
Bit
31-12
8
0
Figure 86. Page Flush/Invalidate Register (PFIR)
LINPAGE Field. This 20-bit field must be written with bits 31:12 of
the linear address of the 4-Kbyte page that is to be invalidated
and optionally flushed from the L1 or the L2 cache.
PF Bit. If an attempt to invalidate or flush a page results in a
page fault, the processor sets the PF bit to 1, and the invalidate
or flush operation is not performed (even though invalidate
operations do not normally generate page faults). In this case,
an actual page fault exception is not generated. If the PF bit
equals 0 after an invalidate or flush operation, then the
operation executed successfully. The PF bit must be read after
every write to the PFIR register to determine if the invalidate
or flush operation executed successfully.
F/I Bit. This bit is used to control the type of action that occurs to
the specified linear page. If a 0 is written to this bit, the
operation is a flush, in which case all cache lines in the
modified state within the specified page are written back to
memory, after which the entire page is invalidated. If a 1 is
written to this bit, the operation is an invalidation, in which
case the entire page is invalidated without the occurrence of
any writebacks.
WBINVD and INVD
These x86 instructions cause all cache lines to be marked as
invalid. WBINVD writes back modified lines before marking all
cache lines invalid. INVD does not write back modified lines.
Cache-Line
Replacement
Replacing lines in the L1 cache and the L2 cache, according to
the line replacement algorithms described in “Cache-Line
Fills” on page 213, ensures coherency between external
memory and the caches.
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Table 40 shows all possible cache-line states before and after
inquire cycles.
Table 40. Valid L1 and L2 Cache States and Effect of Inquire Cycles
Cache State Before Inquire1
L1
L2
I
M
I
Cache State After Inquire
Memory Access2
INV = 0
INV = 1
L1
L2
L1
L2
Writeback L2 to bus
I
S
I
I
E
–
I
S
I
I
I
S
–
I
S
I
I
I
I
–
I
I
I
I
E3
M3
Writeback L2 to bus
S
S
I
I
E
E
–
S
S
I
I
E
I
–
S
I
I
I
M
E
Writeback L1 to bus
S
I
I
I
M
I
Writeback L1 to bus
S
I
I
I
S
S
–
S
S
I
I
S
I
–
S
I
I
I
Notes:
1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and
are treated as “valid” states.
2. Writeback cycles to the bus are 32-byte burst writes.
3. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in
the modified state in the L2 cache.
Chapter 9
Cache Organization
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Table 41 shows all possible cache-line states before and after
various cache-related operations.
Table 41. L1 and L2 Cache States for Snoops, Flushes, and Invalidation
Operation Type
Internal Snoop
Cache State Before Operation1
L1
L2
I
M
I
L2
–
I
M
E
–
I
E
I
S
–
I
S
I
I
–
I
I
E3
M3
–
I
M
E
E
–
I
E
E
I
–
I
I
M
E
Writeback L1 to L2
I
M
M
I
Writeback L1 to bus
I
I
S
S
–
I
S
S
I
–
I
I
–
I
I
M
–
Writeback L1 to bus
I
I
–
M
Writeback L2 to bus
I
I
–
I
I
S or E
PFIR (F/I = 0)
PFIR (F/I = 1)
M
–
Writeback L1 to bus
I
I
–
M
Writeback L2 to bus
I
I
–
–
–
I
I
–
I
I
S or E
WBINVD Instruction
INVD Instruction
Cache State After Operation
L1
S or E
FLUSH# Signal
Access Type2
M
–
Writeback L1 to bus
I
I
–
M
Writeback L2 to bus
I
I
–
–
–
I
I
Notes:
1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache
and are treated as “valid” states.
2. Writeback cycles to the bus are 32-byte burst writes.
3. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in
the modified state in the L2 cache.
— Not applicable or none.
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Chapter 9
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AMD-K6™-2E+ Embedded Processor Data Sheet
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9.12
Writethrough and Writeback Coherency States
The terms writethrough and writeback apply to two related
concepts in a read-write cache like the AMD-K6-2E+ processor
L1 data cache and the L2 cache. The following conditions apply
to both the writethrough and writeback modes:
■
Memory Writes—A relationship exists between external
memory writes and their concurrence with cache updates:
•
An external memory write that occurs concurrently with
a cache update to the same location is a writethrough.
Writethroughs are driven as single cycles on the bus.
An external memory write that occurs after the processor
has modified a cache line is a writeback. Writebacks are
driven as burst cycles on the bus.
Coherency State—A relationship exists between MESI
coherency states and writethrough-writeback coherency
states of lines in the cache as follows:
•
■
9.13
•
Shared and invalid MESI lines are in the writethrough
state.
•
Modified and exclusive MESI lines are in the writeback
state.
A20M# Masking of Cache Accesses
Although the processor samples A20M# as a level-sensitive
input on every clock edge, it should only be asserted in Real
mode. The processor applies the A20M# masking to its tags,
through which all programs access the caches. Therefore,
assertion of A20M# affects all addresses (cache and external
memory), including the following:
■
■
Cache-line fills (caused by read misses or write allocates)
Cache writethroughs (caused by write misses or write hits to
lines in the shared state)
However, A20M# does not mask writebacks or invalidations
caused by the following actions:
■
■
■
Chapter 9
Internal snoops
Inquire cycles
The FLUSH# signal
Cache Organization
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AMD-K6™-2E+ Embedded Processor Data Sheet
■
■
228
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Writing to the Page Flush/Invalidate Register (PFIR)
The WBINVD instruction
Cache Organization
Chapter 9
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
10
Write Merge Buffer
The AMD-K6-2E+ processor contains an 8-byte write merge
buffer that allows the processor to conditionally combine data
from multiple noncacheable write cycles into this merge buffer.
The merge buffer operates in conjunction with the Memory
Type Range Registers (MTRRs). Refer to “Memory Type Range
Registers” on page 231 for a description of the MTRRs.
Merging multiple write cycles into a single write cycle reduces
processor bus utilization and processor stalls, thereby
increasing the overall system performance.
10.1
EWBE# Control
The presence of the merge buffer creates the potential to
perform out-of-order write cycles relative to the processor’s
caches. In general, the ordering of write cycles that are driven
externally on the system bus and those that hit the processor’s
cache can be controlled by the EWBE# signal. See “EWBE#
(External Write Buffer Empty)” on page 110 for more
information.
If EWBE# is sampled negated, the processor delays the
commitment of write cycles to cache lines in the modified state
or exclusive state in the processor’s caches. Therefore, the
system logic can enforce strong ordering by negating EWBE#
until the external write cycle is complete, thereby ensuring that
a subsequent write cycle that hits a cache does not complete
ahead of the external write cycle.
However, the addition of the write merge buffer introduces the
potential for out-of-order write cycles to occur between writes
to the merge buffer and writes to the processor’s caches.
Because these writes occur entirely within the processor and
are not sent out to the processor bus, the system logic is not able
to enforce strong ordering with the EWBE# signal.
The EWBE# control (EWBEC) bits in the EFER register provide
a mechanism for enforcing three different levels of write
ordering in the presence of the write merge buffer:
Chapter 10
Write Merge Buffer
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■
EFER[3] is defined as the Global EWBE# Disable
(GEWBED). When GEWBED equals 1, the processor does
not attempt to enforce any write ordering internally or
externally (the EWBE# signal is ignored). This is the
maximum performance setting.
■
EFER[2] is defined as the Speculative EWBE# Disable
(SEWBED). SEWBED only affects the processor when
GEWBED equals 0. If GEWBED equals 0 and SEWBED
equals 1, the processor enforces strong ordering for all
internal write cycles with the exception of write cycles
addressed to a range of memory defined as uncacheable
(UC) or write-combining (WC) by the MTRRs. In addition,
the processor samples the EWBE# signal. If EWBE# is
sampled negated, the processor delays the commitment of
write cycles to processor cache lines in the modified state or
exclusive state until EWBE# is sampled asserted.
This setting provides performance comparable to, but
slightly less than, the performance obtained when
GEWBED equals 1 because some degree of write ordering is
maintained.
If GEWBED equals 0 and SEWBED equals 0, the processor
enforces strong ordering for all internal and external write
cycles. In this setting, the processor assumes, or speculates,
that strong order must be maintained between writes to the
merge buffer and writes that hit the processor’s caches.
Once the merge buffer is written out to the processor’s bus,
the EWBE# signal is sampled. If EWBE# is sampled negated,
the processor delays the commitment of write cycles to
processor cache lines in the modified state or exclusive state
until EWBE# is sampled asserted.
This setting is the default after RESET and provides the
lowest performance of the three settings because full write
ordering is maintained.
■
230
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Write Merge Buffer
Chapter 10
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 42 summarizes the three settings of the EWBEC field for
the EFER register, along with the effect of write ordering and
performance. For more information on the EFER register, see
“Extended Feature Enable Register (EFER)” on page 47.
Table 42. EWBEC Settings and Performance
10.2
EFER[3]
(GEWBED)
EFER[2]
(SEWBED)
Write
Ordering
Performance
1
0 or 1
None
Best
0
1
All except UC/WC
Close-to-Best
0
0
All
Slowest
Memory Type Range Registers
The AMD-K6-2E+ processor provides two variable-range
Memory Type Range Registers (MTRRs)—MTRR0 and
MTRR1—that each specify a range of memory. Each range can
be defined as one of the following memory types:
■
■
Chapter 10
Uncacheable (UC) Memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. Memory write
cycles are targeted at the specified memory address and a
write allocation does not occur.
Write-Combining (WC) Memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. The processor
conditionally combines data from multiple noncacheable
write cycles that are addressed within this range into a
merge buffer. Merging multiple write cycles into a single
write cycle reduces processor bus utilization and processor
stalls, thereby increasing the overall system performance.
This memory type is applicable for linear video frame
buffers.
Write Merge Buffer
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UC/WC Cacheability
Control Register
(UWCCR)
23542A/0—September 2000
The MTRRs are accessed by addressing the 64-bit MSR known
as the UC/WC Cacheability Control Register (UWCCR). The
MSR address of the UWCCR is C000_0085h. Following reset, all
bits in the UWCCR register are set to 0. MTRR0 (lower 32 bits
of the UWCCR register) defines the size and memory type of
range 0 and MTRR1 (upper 32 bits) defines the size and
memory type of range 1 (see Figure 87).
.
Symbol
UC1
WC1
63
Description
Uncacheable Memory Type
Write-Combining Memory Type
49
Physical Base Address 1
48
Bits
32
33
Symbol
UC0
WC0
Description
Uncacheable Memory Type
Write-Combining Memory Type
34 33 32 31
W U
Physical Address Mask 1 C C
1 1
17 16
Physical Base Address 0
MTRR1
Bits
0
1
2
1
0
W
Physical Address Mask 0 C
0
U
C
0
MTRR0
Figure 87. UC/WC Cacheability Control Register (UWCCR)
Physical Base Address n (n=0, 1). T h i s a d d re s s i s t h e 1 5 m o s t significant bits of the physical base address of the memory
range. The least-significant 17 bits of the base address are not
needed because the base address is by definition always aligned
on a 128-Kbyte boundary.
Physical Address Mask n (n=0, 1). T h i s v a l u e i s t h e 1 5 m o s t significant bits of a physical address mask that is used to define
the size of the memory range. This mask is logically ANDed
with both the physical base address field of the UWCCR
register and the physical address generated by the processor. If
the results of the two AND operations are equal, then the
generated physical address is considered within the range.
That is, if:
Mask & Physical Base Address = Mask & Physical Address Generated
then, the physical address generated by the processor is in the
range.
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Write Merge Buffer
Chapter 10
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WCn (n=0, 1). When set to 1, this memory range is defined as
write combinable (see Table 43). Write-combinable memory is
uncacheable.
UCn (n=0, 1). When set to 1, this memory range is defined as
uncacheable (see Table 43).
Table 43. WC/UC Memory Type
10.3
WCn
UCn
Memory Type
0
0
No effect on cacheability or write combining
1
0
Write-combining memory range (uncacheable)
0 or 1
1
Uncacheable memory range
Memory-Range Restrictions
The following rules regarding the address alignment and size of
each range must be adhered to when programming the physical
base address and physical address mask fields of the UWCCR
register:
■
■
■
■
Chapter 10
The minimum size of each range is 128 Kbytes.
The physical base address must be aligned on a 128-Kbyte
boundary.
The physical base address must be range-size aligned. For
example, if the size of the range is 1 Mbyte, then the
physical base address must be aligned on a 1-Mbyte
boundary.
All bits set to 1 in the physical address mask must be
contiguous. Likewise, all bits set to 0 in the physical address
mask must be contiguous. For example:
111_1111_1100_0000b is a valid physical address mask.
111_1111_1101_0000b is invalid.
Write Merge Buffer
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Table 44 lists the valid physical address masks and the resulting
range sizes that can be programmed in the UWCCR register.
Table 44. Valid Masks and Range Sizes for UWCCR Register
234
Masks
Size
111_1111_1111_1111b
128 Kbytes
111_1111_1111_1110b
256 Kbytes
111_1111_1111_1100b
512 Kbytes
111_1111_1111_1000b
1 Mbyte
111_1111_1111_0000b
2 Mbytes
111_1111_1110_0000b
4 Mbytes
111_1111_1100_0000b
8 Mbytes
111_1111_1000_0000b
16 Mbytes
111_1111_0000_0000b
32 Mbytes
111_1110_0000_0000b
64 Mbytes
111_1100_0000_0000b
128 Mbytes
111_1000_0000_0000b
256 Mbytes
111_0000_0000_0000b
512 Mbytes
110_0000_0000_0000b
1 Gbyte
100_0000_0000_0000b
2 Gbytes
000_0000_0000_0000b
4 Gbytes
Write Merge Buffer
Chapter 10
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
10.4
Examples
Suppose that the range of memory from 16 Mbytes to 32 Mbytes
is uncacheable, and the 8-Mbyte range of memory on top of 1
Gbyte is writ e-com binable . Range 0 is def ined as t he
uncacheable range, and range 1 is defined as the writecombining range.
■
■
Chapter 10
Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 16 Mbytes (0100_0000h)
yields
a
physical
base
address
0
field
of
000_0000_1000_0000b. Because the uncacheable range size
is 16 Mbytes, the physical mask value 0 field is
111_1111_1000_0000b, according to Table 44 on page 234.
Bit 1 of the UWCCR register (WC0) is set to 0 and bit 0 of the
UWCCR register is set to 1 (UC0).
Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 1 Gbyte (4000_0000h)
yields
a
physical
base
address
1
field
of
010_0000_0000_0000b. Because the write-combining range
size is 8 Mbytes, the physical mask value 1 field is
111_1111_1100_0000b, according to Table 44 on page 234.
Bit 33 of the UWCCR register (WC1) is set to 1 and bit 32 of
the UWCCR register is set to 0 (UC1).
Write Merge Buffer
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236
Write Merge Buffer
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Chapter 10
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
11
Floating-Point and Multimedia Execution Units
11.1
Floating-Point Execution Unit
The AMD-K6-2E+ processor contains an IEEE 754-compatible
and 854-compatible floating-point execution unit designed to
accelerate the performance of software that utilizes the x86
floating-point instruction set.
Floating-point software is typically written to manipulate
numbers that are very large or very small, that require a high
degree of precision, or that result from complex mathematical
operations such as transcendentals. Applications that take
advantage of floating-point operations include geometric
calculations for graphics acceleration, scientific, statistical, and
engineering applications, and business applications that use
large amounts of high-precision data.
The high-performance floating-point execution unit contains an
adder unit, a multiplier unit, and a divide/square root unit.
These low-latency units can execute floating-point instructions
in as few as two processor clocks. To increase performance, the
proce sso r is de sig ned to simul ta neo usly de code mo st
floating-point instructions with most short-decodeable
instructions.
See “Software Environment” on page 27 for a description of the
floating-point data types, registers, and instructions.
Handling
Floating-Point
Exceptions
The AMD-K6-2E+ processor provides the following two types of
exception handling for floating-point exceptions:
■
■
Chapter 11
If the numeric error (NE) bit in CR0 is set to 1, the processor
invokes the interrupt 10h handler. In this manner, the
floating-point exception is completely handled by software.
If the NE bit in CR0 is set to 0, the processor requires
external logic to generate an interrupt on the INTR signal in
order to handle the exception.
Floating-Point and Multimedia Execution Units
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AMD-K6™-2E+ Embedded Processor Data Sheet
External Logic
Support of
Floating-Point
Exceptions
23542A/0—September 2000
The processor provides the FERR# (Floating-Point Error) and
IGNNE# (Ignore Numeric Error) signals to allow the external
logic to generate the interrupt in a manner consistent with
IBM-compatible PC/AT systems. The assertion of FERR#
indicates the occurrence of an unmasked floating-point
exception resulting from the execution of a floating-point
instruction. IGNNE# is used by the external hardware to control
the effect of an unmasked floating-point exception. Under
certain circumstances, if IGNNE# is sampled asserted, the
processor ignores the floating-point exception.
Figure 88 on page 239 illustrates an implementation of external
logic for supporting floating-point exceptions. The following
example explains the operation of the external logic in Figure
88:
1. As the result of a floating-point exception, the processor
asserts FERR#.
2. The assertion of FERR# and the sampling of IGNNE#
negated indicates the processor has stopped instruction
execution and is waiting for an interrupt.
3. The assertion of FERR# leads to the assertion of INTR by
the interrupt controller.
4. The processor acknowledges the interrupt and jumps to the
corresponding interrupt service routine in which an I/O
write cycle to address port F0h leads to the assertion of
IGNNE#.
5. When IGNNE# is sampled asserted, the processor ignores
the floating-point exception and continues instruction
execution.
6. When the processor negates FERR#, the external logic
negates IGNNE#.
See “FERR# (Floating-Point Error)” on page 111 and “IGNNE#
(Ignore Numeric Exception)” on page 116 for more details.
238
Floating-Point and Multimedia Execution Units
Chapter 11
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
AMD-K6-2E+
Processor
I/O Address
Port F0h
IGNNE#
Flip-Flop
CLOCK Q
RESET
“1”
FERR#
DATA
Q
CLEAR
FERR#
Flip-Flop
CLOCK Q
DATA
Interrupt
Controller
IRQ13
Q
CLEAR
INTR
IGNNE#
Figure 88. External Logic for Supporting Floating-Point Exceptions
11.2
Multimedia and 3DNow!™ Execution Units
Th e m u l t i m e d i a a n d 3 D N ow ! e x e c u t i o n u n i t s o f t h e
AMD-K6-2E+ processor are designed to accelerate the
performance of software written using the industry-standard
MMX instr uctions a nd the new 3 DN ow ! instruct ions.
Applications that can take advantage of the MMX and 3DNow!
instructions include graphics, video and audio compression and
d e c o m p re s s i o n , s p e e ch re c o g n i t i o n , a n d t e l e p h o ny
applications.
3DNow! technology enables fast frame rates on high-resolution
3D-rendered scenes, realistic physical modeling of real-world
environments, sharp and detailed 3D imaging, smooth video
playback, and theater-quality audio.
The AMD-K6-2E+ processor supports five new digital signal
processing (DSP) instructions, developed to enhance the
performance of communications applications, including soft
xDSL modems, MP3 recording, and Dolby Digital and Surround
Sound processing.
For more information on MMX instructions, see the AMD-K6®
Processor Multimedia Technology Manual, order# 20726. For
Chapter 11
Floating-Point and Multimedia Execution Units
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
more information on 3DNow! instructions, see the 3DNow!™
Technology Manual, order# 21928. For more information on the
3DNow! technology DSP extensions, see the AMD Extensions to
the 3DNow!™ and MMX™ Instructions Sets Manual, order#
22466.
The multimedia execution unit can execute MMX instructions
in a single processor clock. All MMX and 3DNow! arithmetic
instructions are pipelined for higher performance. To increase
performance, the processor is designed to simultaneously
decode all MMX and 3DNow! instructions with most other
instructions.
11.3
Floating-Point and MMX™/3DNow!™ Instruction Compatibility
Registers
The eight 64-bit MMX registers (which are also utilized by
3DNow! instructions) are mapped on the floating-point stack.
This enables backward compatibility with all existing software.
For example, the register saving event that is performed by
operating systems during task switching requires no changes to
the operating system. The same support provided in an
operating system’s interrupt 7 handler (Device Not Available)
for saving and restoring the floating-point registers also
supports saving and restoring the MMX registers.
Exceptions
There are no new exceptions defined for supporting the MMX
and 3DNow! instructions. All exceptions that occur while
decoding or executing an MMX or 3DNow! instruction are
handled in existing exception handlers without modification.
FERR# and IGNNE#
MMX instructions and 3DNow! instructions do not generate
f l o a t i n g -p o i n t e x c e p t i o n s . H oweve r, i f a n u n m a s ke d
floating-point exception is pending, the processor asserts
FERR# at the instruction boundary of the next floating-point
instruction, MMX instruction, 3DNow! instruction or WAIT
instruction.
The sampling of IGNNE# asserted only affects processor
o p e ra t i o n d u r i n g t h e ex e c u t i o n o f a n e r ro r -s e n s i t ive
f l oa t i n g -po i n t i n st r u c ti on , MMX i n st r u c t i on , 3D N ow !
instruction or WAIT instruction when the NE bit in CR0 is set
to 0.
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Floating-Point and Multimedia Execution Units
Chapter 11
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
12
System Management Mode (SMM)
SMM is an alternate operating mode entered by way of a system
management interrupt (SMI#) and handled by an interrupt
service routine. SMM is designed for system control activities
s u ch a s p owe r m a n a g e m e n t . Th e s e a c t iv i t i e s a p p e a r
transparent to conventional operating systems like DOS and
Windows. SMM is targeted for use by the Basic Input Output
System (BIOS), specialized low-level device drivers, and the
operating system. The code and data for SMM are stored in the
SMM memory area, which is isolated from main memory.
The processor enters SMM by the assertion of the SMI#
interrupt and the processor’s acknowledgment by the assertion
of SMIACT#. At this point the processor saves its state into the
SMM memory state-save area and jumps to the SMM service
routine. The processor returns from SMM when it executes the
resume (RSM) instruction from within the SMM service
routine. Subsequently, the processor restores its state from the
SMM save area, negates SMIACT#, and resumes execution with
the instruction following the point where it entered SMM.
The following sections summarize the SMM state-save area,
entry into and exit from SMM, exceptions and interrupts in
SMM, memory allocation and addressing in SMM, and the SMI#
and SMIACT# signals.
12.1
SMM Operating Mode and Default Register Values
The software environment within SMM has the following
characteristics:
■
■
■
■
■
Chapter 12
Addressing and operation in real mode
4-Gbyte segment limits
Default 16-bit operand, address, and stack sizes, although
instruction prefixes can override these defaults
Control transfers that do not override the default operand
size truncate the EIP to 16 bits
Far jumps or calls cannot transfer control to a segment with
a base address requiring more than 20 bits, as in real mode
segment-base addressing
System Management Mode (SMM)
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AMD-K6™-2E+ Embedded Processor Data Sheet
■
■
■
■
■
■
23542A/0—September 2000
A20M# is masked
Interrupt vectors use the real-mode interrupt vector table
The IF flag in EFLAGS is cleared (INTR not recognized)
The TF flag in EFLAGS is cleared
The NMI and INIT interrupts are disabled
Debug register DR7 is cleared (debug traps disabled)
Figure 89 shows the default map of the SMM memory area. It
c on si st s of a 64 -Kbyt e a re a, b et we en 00 03 _ 00 00 h a n d
0003_FFFFh, of which the top 32 Kbytes (0003_8000h to
0003_FFFFh) must be populated with RAM. The default
code-segment (CS) base address for the area—called the SMM
b a s e a d d re s s — i s a t 0 0 0 3 _ 0 0 0 0 h . Th e t o p 5 1 2 by t e s
(0003_FE00h to 0003_FFFFh) contain a fill-down SMM
state-save area. The default entry point for the SMM service
routine is 0003_8000h.
Fill Down
SMM
State-Save
Area
0003_FFFFh
0003_FE00h
32-Kbyte
Minimum RAM
SMM
Service Routine
Service Routine Entry Point
0003_8000h
SMM Base Address (CS)
0003_0000h
Figure 89. SMM Memory
242
System Management Mode (SMM)
Chapter 12
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AMD-K6™-2E+ Embedded Processor Data Sheet
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Table 45 shows the initial state of registers when entering SMM.
Table 45. Initial State of Registers in SMM
12.2
Registers
SMM Initial State
General Purpose Registers
unmodified
EFLAGS
0000_0002h
CR0
PE, EM, TS, and PG are cleared (bits 0, 2, 3, and
31). The other bits are unmodified.
DR7
0000_0400h
GDTR, LDTR, IDTR, TSSR, DR6
unmodified
EIP
0000_8000h
CS
0003_0000h
DS, ES, FS, GS, SS
0000_0000h
SMM State-Save Area
When the processor acknowledges an SMI# interrupt by
asserting SMIACT#, it saves its state in a 512-byte SMM
state-save area shown in Table 46. The save begins at the top of
the SMM memory area (SMM base address + FFFFh) and fills
down to SMM base address + FE00h.
Table 46 shows the offsets in the SMM state-save area relative
to the SMM base address. The SMM service routine can alter
any of the read/write values in the state-save area.
Table 46. SMM State-Save Area Map
Chapter 12
Address Offset
Contents Saved
FFFCh
CR0
FFF8h
CR3
FFF4h
EFLAGS
FFF0h
EIP
FFECh
EDI
FFE8h
ESI
FFE4h
EBP
FFE0h
ESP
FFDCh
EBX
FFD8h
EDX
FFD4h
ECX
FFD0h
EAX
System Management Mode (SMM)
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Table 46. SMM State-Save Area Map (continued)
244
Address Offset
Contents Saved
FFCCh
DR6
FFC8h
DR7
FFC4h
TR
FFC0h
LDTR Base
FFBCh
GS
FFB8h
FS
FFB4h
DS
FFB0h
SS
FFACh
CS
FFA8h
ES
FFA4h
I/O Trap Doubleword
FFA0h
No data dump at this address
FF9Ch
I/O Trap EIP1
FF98h
No data dump at this address
FF94h
No data dump at this address
FF90h
IDT Base
FF8Ch
IDT Limit
FF88h
GDT Base
FF84h
GDT Limit
FF80h
TSS Attr
FF7Ch
TSS Base
FF78h
TSS Limit
FF74h
No data dump at this address
FF70h
LDT High
FF6Ch
LDT Low
FF68h
GS Attr
FF64h
GS Base
FF60h
GS Limit
FF5Ch
FS Attr
FF58h
FS Base
FF54h
FS Limit
FF50h
DS Attr
FF4Ch
DS Base
FF48h
DS Limit
FF44h
SS Attr
FF40h
SS Base
System Management Mode (SMM)
Chapter 12
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 46. SMM State-Save Area Map (continued)
Address Offset
Contents Saved
FF3Ch
SS Limit
FF38h
CS Attr
FF34h
CS Base
FF30h
CS Limit
FF2Ch
ES Attr
FF28h
ES Base
FF24h
ES Limit
FF20h
No data dump at this address
FF1Ch
No data dump at this address
FF18h
No data dump at this address
FF14h
CR2
FF10h
CR4
FF0Ch
I/O Restart ESI1
FF08h
I/O Restart ECX1
FF04h
I/O Restart EDI1
FF02h
HALT Restart Slot
FF00h
I/O Trap Restart Slot
FEFCh
SMM RevID
FEF8h
SMM Base
FEF7h–FE00h
No data dump at this address
Notes:
1. Only contains information if SMI# is asserted during a valid I/O bus cycle.
12.3
SMM Revision Identifier
The SMM revision identifier at offset FEFCh in the SMM
state-save area specifies the version of SMM and the extensions
that are available on the processor. The SMM revision identifier
fields are as follows:
■
■
■
■
Chapter 12
Bits 31–18—Reserved
Bit 17—SMM base address relocation (1 = enabled)
Bit 16—I/O trap restart (1 = enabled)
Bits 15–0—SMM revision level for the AMD-K6-2E+ processor= 0002h
System Management Mode (SMM)
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Table 47 shows the format of the SMM Revision Identifier.
Table 47. SMM Revision Identifier
12.4
31–18
17
16
15–0
Reserved
SMM Base Relocation
I/O Trap Extension
SMM Revision Level
0
1
1
0002h
SMM Base Address
During RESET, the processor sets the base address of the
code-segment (CS) for the SMM memory area—the SMM base
address—to its default, 0003_0000h. The SMM base address at
offset FEF8h in the SMM state-save area can be changed by the
SMM service routine to any address that is aligned to a
32-Kbyte boundary. (Locations not aligned to a 32-Kbyte
boundary cause the processor to enter the Shutdown state when
executing the RSM instruction.)
In some operating environments it may be desirable to relocate
the 64-Kbyte SMM memory area to a high memory area in order
to provide more low memory for legacy software. During system
initialization, the base of the 64-Kbyte SMM memory area is
relocated by the BIOS. To relocate the SMM base address, the
system enters the SMM handler at the default address. This
handler changes the SMM base address location in the SMM
state-save area, copies the SMM handler to the new location,
and exits SMM.
The next time SMM is entered, the processor saves its state at
the new base address. This new address is used for every SMM
entry until the SMM base address in the SMM state-save area is
changed or a hardware reset occurs.
12.5
Halt Restart Slot
During entry into SMM, the halt restart slot at offset FF02h in
the SMM state-save area indicates if SMM was entered from the
Halt state. Before returning from SMM, the halt restart slot
(offset FF02h) can be written to by the SMM service routine to
specify whether the return from SMM takes the processor back
to the Halt state or to the next instruction after the HLT
instruction.
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Upon entry into SMM, the halt restart slot is defined as follows:
■
■
Bits 15–1—Reserved
Bit 0—Point of entry to SMM:
1 = entered from Halt state
0 = not entered from Halt state
After entry into the SMI handler and before returning from
SMM, the halt restart slot can be written using the following
definition:
■
■
Bits 15–1—Reserved
Bit 0—Point of return when exiting from SMM:
1 = return to Halt state
0 = return to next instruction after the HLT instruction
If the return from SMM takes the processor back to the Halt
state, the HLT instruction is not re-executed, but the Halt
special bus cycle is driven on the bus after the return.
12.6
I/O Trap Doubleword
If the assertion of SMI# is recognized during the execution of an
I/O instruction, the I/O trap doubleword at offset FFA4h in the
S M M s t a t e -s ave a re a c o n t a i n s i n fo r m a t i o n ab o ut t h e
instruction. The fields of the I/O trap doubleword are
configured as follows:
■
■
■
■
■
■
Chapter 12
Bits 31–16—I/O port address
Bits 15–4—Reserved
Bit 3—REP (repeat) string operation
(1 = REP string, 0 = not a REP string)
Bit 2—I/O string operation
(1 = I/O string, 0 = not an I/O string)
Bit 1—Valid I/O instruction (1 = valid, 0 = invalid)
Bit 0—Input or output instruction (1 = INx, 0 = OUTx)
System Management Mode (SMM)
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Table 48 shows the format of the I/O trap doubleword.
Table 48. I/O Trap Doubleword Configuration
31—16
15—4
3
2
1
0
I/O Port
Address
Reserved
REP String
Operation
I/O String
Operation
Valid I/O
Instruction
Input or
Output
The I/O trap doubleword is related to the I/O trap restart slot
(see “I/O Trap Restart Slot”). If bit 1 of the I/O trap doubleword
is set by the processor, it means that SMI# was asserted during
the execution of an I/O instruction. The SMI handler tests bit 1
to see if there is a valid I/O instruction trapped. If the I/O
instruction is valid, the SMI handler is required to ensure the
I/O trap restart slot is set properly. The I/O trap restart slot
informs the processor whether it should re-execute the I/O
instruction after the RSM or execute the instruction following
the trapped I/O instruction.
Note: If SMI# is sampled asserted during an I/O bus cycle a
minimum of three clock edges before BRDY# is sampled
asserted, the associated I/O instruction is guaranteed to be
trapped by the SMI handler.
12.7
I/O Trap Restart Slot
The I/O trap restart slot at offset FF00h in the SMM state-save
area specifies whether the trapped I/O instruction should be
re-executed on return from SMM. This slot in the state-save area
is called the I/O instruction restart function. Re-executing a
trapped I/O instruction is useful, for example, if an I/O write
occurs to a disk that is powered down. The system logic
monitoring such an access can assert SMI#. Then the SMM
service routine would query the system logic, detect a failed I/O
write, take action to power-up the I/O device, enable the I/O
trap restart slot feature, and return from SMM.
The fields of the I/O trap restart slot are defined as follows:
■
■
248
Bits 31–16—Reserved
Bits 15–0—I/O instruction restart on return from SMM:
0000h = execute the next instruction after the trapped
I/O instruction
00FFh = re-execute the trapped I/O instruction
System Management Mode (SMM)
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Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 49 shows the format of the I/O trap restart slot.
Table 49. I/O Trap Restart Slot
31–16
15–0
Reserved
I/O Instruction restart on return from SMM:
0000h = execute the next instruction after the trapped I/O
00FFh = re-execute the trapped I/O instruction
The processor initializes the I/O trap restart slot to 0000h upon
entry into SMM. If SMM was entered due to a trapped I/O
instruction, the processor indicates the validity of the I/O
instruction by setting or clearing bit 1 of the I/O trap
doubleword at offset FFA4h in the SMM state-save area. The
S MM se rvice ro u tine should t es t b it 1 of the I/ O t ra p
doubleword to determine if a valid I/O instruction was being
executed when entering SMM and before writing the I/O trap
restart slot. If the I/O instruction is valid, the SMM service
routine can safely rewrite the I/O trap restart slot with the value
00FFh, which causes the processor to re-execute the trapped I/O
instruction when the RSM instruction is executed. If the I/O
instruction is invalid, writing the I/O trap restart slot has
undefined results.
If a second SMI# is asserted and a valid I/O instruction was
trapped by the first SMM handler, the processor services the
second SMI# prior to re-executing the trapped I/O instruction.
The second entry into SMM never has bit 1 of the I/O trap
doubleword set, and the second SMM service routine must not
rewrite the I/O trap restart slot.
During a simultaneous SMI# I/O instruction trap and debug
breakpoint trap, the AMD-K6-2E+ processor first responds to
the SMI# and postpones recognizing the debug exception until
after returning from SMM via the RSM instruction. If the debug
registers DR3–DR0 are used while in SMM, they must be saved
and restored by the SMM handler. The processor automatically
saves and restores DR7–DR6. If the I/O trap restart slot in the
SMM state-save area contains the value 00FFh when the RSM
instruction is executed, the debug trap does not occur until
after the I/O instruction is re-executed.
Chapter 12
System Management Mode (SMM)
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AMD-K6™-2E+ Embedded Processor Data Sheet
12.8
23542A/0—September 2000
Exceptions, Interrupts, and Debug in SMM
During an SMI# I/O trap, the exception/interrupt priority of the
AMD-K6-2E+ processor changes from its normal priority. The
normal priority places the debug traps at a priority higher than
the sampling of the FLUSH# or SMI# signals. However, during
an SMI# I/O trap, the sampling of the FLUSH# or SMI# signals
takes precedence over debug traps.
The processor recognizes the assertion of NMI within SMM
immediately after the completion of an IRET instruction. Once
NMI is recognized within SMM, NMI recognition remains
enabled until SMM is exited, at which point NMI masking is
restored to the state it was in before entering SMM.
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AMD-K6™-2E+ Embedded Processor Data Sheet
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13
Test and Debug
The AMD-K6-2E+ processor implements various test and debug
modes to enable the functional and manufacturing testing of
systems and boards that use the processor. In addition, the
debug features of the processor allow designers to debug the
instruction execution of software components. This chapter
describes the following test and debug features:
■
■
■
■
■
■
13.1
Built-In Self-Test (BIST)—The BIST, which is invoked after
the falling transition of RESET, runs internal tests that
exercise most on-chip RAM structures.
Three-State Test Mode—A test mode that causes the
processor to float its output and bidirectional pins.
Boundary-Scan Test Access Port (TAP) —The Joint Test
Action Group (JTAG) test access function defined by the
IEEE Standard Test Access Port and Boundary-Scan
Architecture (IEEE 1149.1-1990) specification.
Cache Inhibit—A feature that disables the processor’s
internal L1 and L2 caches.
Level-2 Cache Array Access Register (L2AAR)—The
AMD-K6-2E+ processor provides the L2AAR that allows for
direct access to the L2 cache and L2 tag arrays.
Debug Support—Consists of all x86-compatible software
debug features, including the debug extensions.
Built-In Self-Test (BIST)
Following the falling transition of RESET, the processor
unconditionally runs its built-in self test (BIST). The internal
resources tested during BIST include the following:
■
■
■
Chapter 13
L1 instruction and data caches
L2 cache
Instruction and Data Translation Lookaside Buffers (TLBs)
Test and Debug
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The contents of the EAX general-purpose register after the
completion of reset indicate if the BIST was successful.
■
■
If EAX contains 0000_0000h, then BIST was successful.
If EAX is non-zero, the BIST failed.
Following the completion of the BIST, the processor jumps to
address FFFF_FFF0h to start instruction execution, regardless
of the outcome of the BIST.
The BIST takes approximately 5,000,000 processor clocks to
complete.
13.2
Three-State Test Mode
The Three-State Test mode causes the processor to float its
output and bidirectional pins, which is useful for board-level
manufac turing t esting . I n t his m ode, t he processo r is
electrically isolated from other components on a system board,
allowing automated test equipment (ATE) to test components
that drive the same signals as those the processor floats.
If the FLUSH# signal is sampled Low during the falling
transition of RESET, the processor enters the Three-State Test
mode. (See “FLUSH# (Cache Flush)” on page 112 for the
specific sampling requirements.) The signals floated in the
Three-State Test mode are as follows:
■
■
■
■
■
■
■
■
A[31:3]
ADS#
ADSC#
AP
APCHK#
BE[7:0]#
BREQ
CACHE#
■
■
■
■
■
■
■
■
D/C#
D[63:0]
DP[7:0]
FERR#
HIT#
HITM#
HLDA
LOCK#
■
■
■
■
■
■
■
■
M/IO#
PCD
PCHK#
PWT
SCYC
SMIACT#
VID[4:0]
W/R#
The VCC2DET, VCC2H/L#, and TDO signals are the only
outputs not floated in the Three-State Test mode.
■
252
VCC2DET and VCC2H/L# must remain Low to ensure the
system continues to supply the specified processor core
voltage to the VCC2 pins.
Test and Debug
Chapter 13
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AMD-K6™-2E+ Embedded Processor Data Sheet
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■
TDO is never floated because the Boundary-Scan Test
Access Port must remain enabled at all times, including
during the Three-State Test mode.
The Three-State Test mode is exited when the processor
samples RESET asserted.
13.3
Boundary-Scan Test Access Port (TAP)
The boundary-scan Test Access Port (TAP) is an IEEE standard
that defines synchronous scanning test methods for complex
logic circuits, such as boards containing a processor. The
AMD-K6-2E+ processor supports the TAP standard defined in
the I EEE Standard Test Acces s Port and Boundary-Scan
Architecture (IEEE 1149.1-1990) specification.
Boundary scan testing uses a shift register consisting of the
serial interconnection of boundary-scan cells that correspond to
each I/O buffer of the processor. This non-inverting register
chain, called a Boundary Scan Register (BSR), can be used to
capture the state of every processor pin and to drive every
processor output and bidirectional pin to a known state.
Each BSR of every component on a board that implements the
boundary-scan architecture can be serially interconnected to
enable component interconnect testing.
Test Access Port
The TAP consists of the following:
■
■
■
Chapter 13
Test Access Port (TAP) Controller—The TAP controller is a
synchronous, finite state machine that uses the TMS and
TDI input signals to control a sequence of test operations.
See “TAP Controller State Machine” on page 260 for a list of
TAP states and their definition.
Instruction Register (IR)—The IR contains the instructions
that select the test operation to be performed and the Test
Data Register (TDR) to be selected. See “TAP Registers” on
page 255 for more details on the IR.
Test Data Registers (TDR)—The three TDRs are used to
process the test data. Each TDR is selected by an instruction
in the Instruction Register (IR). See “TAP Registers” on
page 255 for a list of these registers and their functions.
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TAP Signals
23542A/0—September 2000
The test signals associated with the TAP controller are as
follows:
■
■
■
■
■
TCK—The Test Clock for all TAP operations. The rising
edge of TCK is used for sampling TAP signals, and the
falling edge of TCK is used for asserting TAP signals. The
state of the TMS signal sampled on the rising edge of TCK
causes the state transitions of the TAP controller to occur.
TCK can be stopped in the logic 0 or 1 state.
TDI—The Test Data Input represents the input to the most
significant bit of all TAP registers, including the IR and all
test data registers. Test data and instructions are serially
shifted by one bit into their respective registers on the rising
edge of TCK.
TDO—The Test Data Output represents the output of the
least significant bit of all TAP registers, including the IR and
all test data registers. Test data and instructions are serially
shifted by one bit out of their respective registers on the
falling edge of TCK.
TMS—The Test Mode Select input specifies the test
function and sequence of state changes for boundary-scan
testing. If TMS is sampled High for five or more consecutive
clocks, the TAP controller enters its reset state.
TRST#—The Test Reset signal is an asynchronous reset that
unconditionally causes the TAP controller to enter its reset
state.
Refer to “Electrical Data” on page 285 and “Signal Switching
Charac t er ist ics” o n pa ge 29 5 t o obt a in t he e lect ric a l
specifications of the test signals.
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TAP Registers
The AMD-K6-2E+ processor provides an Instruction Register
(IR) and three Test Data Registers (TDR) to support the
boundary-scan architecture. The IR and one of the TDRs—the
Boundary-Scan Register (BSR)—consist of a shift register and
an output register. The shift register is loaded in parallel in the
Capture states. (See “TAP Controller State Machine” on
page 260 for a description of the TAP controller states.) In
addition, the shift register is loaded and shifted serially in the
Shift states. The output register is loaded in parallel from its
corresponding shift register in the Update states.
Instruction Register (IR). The IR is a 5-bit register, without parity,
that determines which instruction to run and which test data
register to select. When the TAP controller enters the
Capture-IR state, the processor loads the following bits into the
IR shift register:
■
■
01b—Loaded into the two least significant bits, as specified
by the IEEE 1149.1 standard
000b—Loaded into the three most significant bits
Loading 00001b into the IR shift register during the Capture-IR
state results in loading the SAMPLE/PRELOAD instruction.
For each entry into the Shift-IR state, the IR shift register is
serially shifted by one bit toward the TDO pin. During the shift,
the most significant bit of the IR shift register is loaded from
the TDI pin.
The IR output register is loaded from the IR shift register in the
Update-IR state, and the current instruction is defined by the
IR output register. See “TAP Instructions” on page 259 for a list
a n d d e f i n i t i o n o f t h e i n s t r u c t i o n s s u p p o r t e d by t h e
AMD-K6-2E+ processor.
Boundary Scan Register (BSR). The Boundary Scan Register is a Test
Data Register consisting of the interconnection of 152
boundary-scan cells. Each output and bidirectional pin of the
processor requires a two-bit cell, where one bit corresponds to
the pin and the other bit is the output enable for the pin. When
a 0 is shifted into the enable bit of a cell, the corresponding pin
is floated, and when a 1 is shifted into the enable bit, the pin is
driven valid. Each input pin requires a one-bit cell that
corresponds to the pin. The last cell of the BSR is reserved and
does not correspond to any processor pin.
Chapter 13
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The total number of bits that comprise the BSR is 297. Table 50
on page 257 lists the order of these bits, where TDI is the input
to bit 296, and TDO is driven from the output of bit 0. The
entries listed as pin_E (where pin is an output or bidirectional
signal) are the enable bits.
If the BSR is the register selected by the current instruction
and the TAP controller is in the Capture-DR state, the processor
loads the BSR shift register as follows:
■
■
If the current instruction is SAMPLE/PRELOAD, then the
current state of each input, output, and bidirectional pin is
loaded. A bidirectional pin is treated as an output if its
enable bit equals 1, and it is treated as an input if its enable
bit equals 0.
If the current instruction is EXTEST, then the current state
of each input pin is loaded. A bidirectional pin is treated as
an input, regardless of the state of its enable.
While in the Shift-DR state, the BSR shift register is serially
shifted toward the TDO pin. During the shift, bit 280 of the BSR
is loaded from the TDI pin.
The BSR output register is loaded with the contents of the BSR
shift register in the Update-DR state. If the current instruction
is EXTEST, the processor’s output pins, as well as those
bidirectional pins that are enabled as outputs, are driven with
their corresponding values from the BSR output register.
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Table 50. Boundary Scan Bit Definitions1
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable
296 A6_E
263 A28_E
230 HIT#
197 AP
164 RSVD
131
295 A6
262 A28
229 A27_E
196 A20_E
163 RSVD
130 D40
294 VID1_E2
261 ADS_E
228 A27
195 A20
162 RSVD
129 D59_E
293 VID12
260 ADS#
227 A4_E
194 BREQ_E
161
128 D59
292 A22_E
259 A17_E
226 A4
193 BREQ
160 AHOLD
127 D9_E
291 A22
258 A17
225 A7_E
192 A11_E
159 INV
126 D9
290 PCHK_E
257 A25_E
224 A7
191 A11
158 CLK
125 D28_E
289 PCHK#
256 A25
223 A8_E
190 A10_E
157 VID2_E2
124 D28
288 A14_E
255 PWT_E
222 A8
189 A10
156 VID22
123 D56_E
287 A14
254 PWT
221 A15_E
188 APCHK_E
155 CACHE_E
122 D56
286 A13_E
253 A12_E
220 A15
187 APCHK#
154 CACHE#
121
285 A13
252 A12
219
186 SMIACT_E
153 MIO_E
120 D44
284 A24_E
251 A9_E
218 D/C#
185 SMIACT#
152 M/IO#
119 D11_E
283 A24
250 A9
217
A16_E
184 RSVD
151 FERR_E
118 D11
282 RESET
249 A26_E
216
A16
183 A5_E
150 FERR#
117
281 A18_E
248 A26
215
A19_E
182 A5
149 D0_E
116 DP3
280 A18
247 A30_E
214
A19
181 INTR
148 D0
115 D39_E
279 A21_E
246 A30
213
SCYC_E
180 NMI
147 D1_E
114 D39
278 A21
245 VID0_E2
212
SCYC
179 INIT
146 D1
113 DP6_E
277 PCD_E
244 VID02
211
ADSC_E
178 HOLD
145 D61_E
112 DP6
276 PCD
243 HITM_E
210
ADSC#
177 IGNNE#
144 D61
111 D8_E
275 BE4_E
242 HITM#
209 BE6_E
176 SMI#
143 D62_E
110 D8
274 BE4#
241 A20M#
208 BE6
175 WB/WT#
142 D62
109 D32_E
273 BE7_E
240 FLUSH#
207 BE3_E
174
141
108 D32
272 BE7#
239 A3_E
206 BE3
173 BOFF#
140 DP0
107 D36_E
271 A23_E
238 A3
205 HLDA_E
172 NA#
139 D21_E
106 D36
270 A23
237 A31_E
204 HLDA
171
138 D21
105 D51_E
269 LOCK_E
236 A31
203 BE1_E
170 BRDYC#
137 D57_E
104 D51
268 LOCK#
235 A29_E
202 BE1#
169 BRDY#
136 D57
103 D15_E
267 BE0_E
234 A29
201 EADS#
168 STPCLK#
135 D5_E
102 D15
266 BE0#
233 WR_E
200 BE2_E
167 BF2
134 D5
101 D37_E
265 BE5_E
232 W/R#
199 BE2#
166 KEN#
133 D24_E
100 D37
264 BE5#
231 HIT_E
198 AP_E
165 EWBE#
132 D24
99
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BF1
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DP0_E
D40_E
D44_E
DP3_E
D41_E
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Table 50. Boundary Scan Bit Definitions1 (continued)
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable
98
D41
81
D49
64
D20_E
47
D35
30
D43_E
13
D45
97
D52_E
80
D17_E
63
D20
46
D10_E
29
D43
12
D60_E
96
D52
79
D17
62
D13_E
45
D10
28
D58_E
11
D60
95
D14_E
78
D19_E
61
D13
44
D53_E
27
D58
10
D22_E
94
D14
77
D19
60
DP5_E
43
D53
26
D26_E
9
D22
93
D29_E
76
D48_E
59
DP5
42
D34_E
25
D26
8
D63_E
92
D29
75
D48
58
D31_E
41
D34
24
D3_E
7
D63
91
D33_E
74
D47_E
57
D31
40
VID4_E2
23
D3
6
DP7_E
90
D33
73
D47
56
D27_E
39
VID42
22
D55_E
5
DP7
89
RSVD
72
D16_E
55
D27
38
D7_E
21
D55
4
D4_E
88
D18_E
71
D16
54
D12_E
37
D7
20
D42_E
3
D4
87
D18
70
DP1_E
53
D12
36
DP4_E
19
D42
2
D2_E
86
D23_E
69
DP1
52
D50_E
35
DP4
18
VID3_E2
1
D2
85
D23
68
D46_E
51
D50
34
D54_E
17
VID32
0
Reserved
84
D25_E
67
D46
50
D38_E
33
D54
16
D6_E
83
D25
66
DP2_E
49
D38
32
D30_E
15
D6
82
D49_E
65
DP2
48
D35_E
31
D30
14
D45_E
Notes:
1. TDI is the input to bit 296, and TDO is driven from the output of bit 0. The entries listed as pin_E (where pin is an output or
bidirectional signal) are the enable bits.
2. Supported on low-power versions only.
Device Identification Register (DIR). The DIR is a 32-bit Test Data
Register selected during the execution of the IDCODE
instruction. The fields of the DIR and their values are shown in
Table 51 on page 259 and are defined as follows:
■
■
■
258
Version Code—This 4-bit field is incremented by AMD
manufacturing for each major revision of silicon.
Part Number—This 16-bit field identifies the specific
processor model.
Manufacturer—This 11-bit field identifies the manufacturer
of the component (AMD).
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LSB—The least significant bit (LSB) of the DIR is always set
to 1, as specified by the IEEE 1149.1 standard.
■
Table 51. Device Identification Register
Version Code
(Bits 31–28)
Part Number
(Bits 27–12)
Manufacturer
(Bits 11–1)
LSB
(Bit 0)
Xh
05D0h
00000000001b
1b
Bypass Register (BR). The BR is a Test Data Register consisting of
a 1-bit shift register that provides the shortest path between
TDI and TDO. When the processor is not involved in a test
operation, the BR can be selected by an instruction to allow the
transfer of test data through the processor without having to
serially scan the test data through the BSR. This functionality
preserves the state of the BSR and significantly reduces test
time.
The BR register is selected by the BYPASS and HIGHZ
instructions as well as by any instructions not supported by the
AMD-K6-2E+ processor.
TAP Instructions
The processor supports the three instructions required by the
IEEE 1149.1 standard — EXTEST, SAMPLE/PRELOAD, and
BYPASS — as well as two additional optional instructions —
IDCODE and HIGHZ.
Table 52 shows the complete set of TAP instructions supported
by the processor along with the 5-bit Instruction Register
encoding and the register selected by each instruction.
Table 52. Supported TAP Instructions
Instruction
Encoding
Register
EXTEST1
Description
00000b
BSR
Sample inputs and drive outputs
SAMPLE / PRELOAD
00001b
BSR
Sample inputs and outputs, then load the BSR
IDCODE
00010b
DIR
Read DIR
HIGHZ
00011b
BR
Float outputs and bidirectional pins
2
00100b–11110b
BR
Undefined instruction, execute the BYPASS instruction
3
11111b
BR
Connect TDI to TDO to bypass the BSR
BYPASS
BYPASS
Notes:
1. Following the execution of the EXTEST instruction, the processor must be reset in order to return to normal, non-test operation.
2. These instruction encodings are undefined on the AMD-K6-2E+ processor and default to the BYPASS instruction.
3. Because the TDI input contains an internal pullup, the BYPASS instruction is executed if the TDI input is not connected or open during
an instruction scan operation. The BYPASS instruction does not affect the normal operational state of the processor.
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EXTEST Instruction. When the EXTEST instruction is executed,
the processor loads the BSR shift register with the current state
of the input and bidirectional pins in the Capture-DR state and
drives the output and bidirectional pins with the corresponding
values from the BSR output register in the Update-DR state.
SAMPLE/PRELOAD Instruction. The SAMPLE/PRELOAD instruction
performs two functions. These functions are as follows:
■
■
During the Capture-DR state, the processor loads the BSR
shift register with the current state of every input, output,
and bidirectional pin.
During the Update-DR state, the BSR output register is
loaded from the BSR shift register in preparation for the
next EXTEST instruction.
The SAMPLE/PRELOAD instruction does not affect the normal
operational state of the processor.
BYPASS Instruction. The BYPASS instruction selects the BR
register, which reduces the boundary-scan length through the
processor from 297 to one (TDI to BR to TDO). The BYPASS
instruction does not affect the normal operational state of the
processor.
IDCODE Instruction. The IDCODE instruction selects the DIR
register, allowing the device identification code to be shifted
out of the processor. This instruction is loaded into the IR when
the TAP controller is reset. The IDCODE instruction does not
affect the normal operational state of the processor.
HIGHZ Instruction. The HIGHZ instruction forces all output and
bidirectional pins to be floated. During this instruction, the BR
is selected and the normal operational state of the processor is
not affected.
TAP Controller State
Machine
260
The TAP controller state diagram is shown in Figure 90 on page
261. State transitions occur on the rising edge of TCK. The logic
0 or 1 next to the states represents the value of the TMS signal
sampled by the processor on the rising edge of TCK.
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Test-Logic-Reset
1
0
Run-Test/Idle
1
1
Select-DR-Scan
1
Select-IR-Scan
0
0
0
1
Capture-DR
1
Capture-IR
0
0
Shift-DR
Shift-IR
0
0
1
1
1
Exit1-DR
Exit1-IR
0
0
Pause-DR
1
Pause-IR
0
0
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-IR
Update-DR
0
1
1
0
IEEE Std 1149.1-1990, Copyright © 1990. IEEE. All rights reserved
Figure 90. TAP State Diagram
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The states of the TAP controller are described as follows:
Test-Logic-Reset. This state represents the initial reset state of the
TAP controller and is entered when the processor samples
RESET asserted, when TRST# is asynchronously asserted, and
when TMS is sampled High for five or more consecutive clocks.
In addition, this state can be entered from the Select-IR-Scan
state. The IR is initialized with the IDCODE instruction, and
the processor’s normal operation is not affected in this state.
Capture-DR. During the SAMPLE/PRELOAD instruction, the
processor loads the BSR shift register with the current state of
every input, output, and bidirectional pin. During the EXTEST
instruction, the processor loads the BSR shift register with the
current state of every input and bidirectional pin.
Capture-IR. When the TAP controller enters the Capture-IR state,
the processor loads 01b into the two least significant bits of the
IR shift register and loads 000b into the three most significant
bits of the IR shift register.
Shift-DR. While in the Shift-DR state, the selected TDR shift
register is serially shifted toward the TDO pin. During the shift,
the most significant bit of the TDR is loaded from the TDI pin.
Shift-IR. While in the Shift-IR state, the IR shift register is
serially shifted toward the TDO pin. During the shift, the most
significant bit of the IR is loaded from the TDI pin.
Update-DR. During the SAMPLE/PRELOAD instruction, the BSR
output register is loaded with the contents of the BSR shift
register. During the EXTEST instruction, the output pins, as
well as those bidirectional pins defined as outputs, are driven
with their corresponding values from the BSR output register.
Update-IR. In this state, the IR output register is loaded from the
IR shift register, and the current instruction is defined by the
IR output register.
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The following states have no effect on the normal or test
operation of the processor other than as shown in Figure 90 on
page 261:
■
Run-Test/Idle—This state is an idle state between scan
operations.
■
Select-DR-Scan—This is the initial state of the test data
register state transitions.
Select-IR-Scan—This is the initial state of the Instruction
Register state transitions.
Exit1-DR—This state is entered to terminate the shifting
process and enter the Update-DR state.
■
■
■
Exit1-IR—This state is entered to terminate the shifting
process and enter the Update-IR state.
■
Pause-DR—This state is entered to temporarily stop the
shifting process of a Test Data Register.
Pause-IR—This state is entered to temporarily stop the
shifting process of the Instruction Register.
Exit2-DR—This state is entered in order to either terminate
the shifting process and enter the Update-DR state or to
resume shifting following the exit from the Pause-DR state.
Exit2-IR—This state is entered in order to either terminate
the shifting process and enter the Update-IR state or to
resume shifting following the exit from the Pause-IR state.
■
■
■
13.4
Cache Inhibit
The AMD-K6-2E+ processor provides a means for inhibiting the
normal operation of its internal L1 and L2 caches while still
supporting an external cache. This capability allows system
designers to disable the L1 and L2 caches during the testing
and debug of an L3 cache.
If the Cache Inhibit bit (bit 3) of Test Register 12 (TR12) is set
to 0, the processor’s L1 and L2 caches are enabled and operate
as described in “Cache Organization” on page 205. If the Cache
Inhibit bit is set to 1, the L1 and L2 caches are disabled and no
new cache lines are allocated. Even though new allocations do
not occur, valid L1 and L2 cache lines remain valid and are read
by the processor when a requested address hits a cache line. In
addition, the processor continues to support inquire cycles
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initiated by the system logic, including the execution of
writeback cycles when a modified cache line is hit.
While the L1 and L2 are inhibited, the processor continues to
drive the PCD output signal appropriately, which system logic
can use to control external L3 caching.
In order to completely disable the L1 and L2 caches so that no
valid lines exist in the cache, the Cache Inhibit bit must be set
to 1 and the cache must be flushed in one of the following ways:
■
■
■
■
13.5
Asserting the FLUSH# input signal
Executing the WBINVD instruction
Executing the INVD instruction (modified cache lines are
not written back to memory)
Using the Page Flush/Invalidate Register (PFIR) (see “Page
Flush/Invalidate Register (PFIR)” on page 223)
L2 Cache and Tag Array Testing
Level-2 Cache Array
Access Register
(L2AAR)
The AMD-K6-2E+ processor provides the Level-2 Cache Array
Access Register (L2AAR) that allows for direct access to the L2
cache and L2 tag arrays. The 128-Kbyte L2 cache in the
AMD-K6-2E+ is organized as shown in Figure 91 on page 265:
■
■
■
■
■
■
Four 32-Kbyte ways
Each way contains 512sets
Each set contains four 64-byte sectors (one sector in each
way)
Each sector contains two 32-byte cache lines
Each cache line contains four 8-byte octets
Each octet contains an upper and lower dword (4 bytes)
Each line within a sector contains its own MESI state bits, and
associated with each sector is a tag and LRU (least recently
used) information.
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64 bytes
Line1/MESI
512 sets
Set 0
64 bytes
Line0/MESI
Tag/LRU
Line1/MESI
Way 0
Line0/MESI
64 bytes
64 bytes
Tag/LRU
Line1/MESI
Way 1
Line0/MESI
Tag/LRU
Line1/MESI
Way 2
Line0/MESI
Tag/LRU
Way 3
Set 511
Figure 91. L2 Cache Organization for AMD-K6™-2E+ Processor
Figure 92 shows the L2 cache sector and line organization. If bit
5 of the address of a cache line equals 1, then this cache line is
stored in Line 1 of a sector. Similarly, if bit 5 of the address of a
cache line equals 0, then this cache line is stored in Line 0 of a
sector.
Octet 0
Upper Dword
Lower Dword
Upper Dword
Lower Dword
Octet 1
Octet 2
Octet 3
Line 1
Line 0
Sector
Figure 92. L2 Cache Sector and Line Organization
The L2AAR register is MSR C000_0089h. The operation that is
performed on the L2 cache is a function of the instruction
executed—RDMSR or WRMSR—and the contents of the EDX
register. The EDX register specifies the location of the access,
and whether the access is to the L2 cache data or tags (refer to
Figure 93 on page 266). Bit 20 of EDX (T/D) determines
whether the access is to the L2 cache data or tag. Table 53 on
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page 266 describes the operation that is performed based on
the instruction and the T/D bit.
Symbol
T/D
Way
Description
Selects Tag (1) or Data (0) access
Selects desired cache way
21 20 19 18 17 16 15 14
31
T
/
D
Way
Set
Bit
20
17-16
6 5 4
3 2 1
L
i
n
e
D
w
o
r
d
Octet
0
Reserved
Symbol
Set
Line
Octet
Dword
Description
Selects the desired cache set
Selects Line1 (1) or Line0 (0)
Selects one of four octets
Selects upper (1) or lower (0) dword
Bit
14-6
5
4-3
2
Figure 93. L2 Tag or Data Location for the AMD-K6™-2E+ Processor—EDX
Table 53. Tag versus Data Selector
Instruction
T/D
(EDX[20])
RDMSR
0
Read dword from L2 data array into EAX. Dword location
is specified by EDX.
RDMSR
1
Read tag, line state and LRU information from L2 tag array
into EAX. Location of tag is specified by EDX.
WRMSR
0
Write dword to the L2 data array using data in EAX. Dword
location is specified by EDX.
WRMSR
1
Write tag, line state and LRU information into L2 tag array
from EAX. Location of tag is specified by EDX.
Operation
When the L2AAR is read or written, EDX is left unchanged.
This facilitates multiple accesses when testing the entire
cache/tag array.
L2 Cache Data Reads
266
If the L2 cache data is read (as opposed to reading the tag
information), the result (dword) is placed in EAX in the format
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as illustrated in Figure 94. Similarly, if the L2 cache data is
written, the write data is taken from EAX.
31
0
Data
Figure 94. L2 Data - EAX
L2 Tag Reads
If the L2 tag is read (as opposed to reading the cache data), the
result is placed in EAX in the format as illustrated in Figure 95
on page 267. Similarly, if the L2 tag is written, the write data is
taken from EAX. When accessing the L2 tag, the Line, Octet,
and Dword fields of the EDX register are ignored.
.
14 13 12 11 10 9
31
Line1ST Line0ST
Tag
0
8 7
LRU
C
M
D
Reserved
Symbol
Tag
Line1ST
Line0ST
LRU
Description
Tag data read or written
Line 1 state (M=11, E=10, S=01, I=00)
Line 0 state (M=11, E=10, S=01, I=00)
Two bits of LRU for each way
Bit
31-14
11-10
9-8
7-0
Figure 95. L2 Tag Information for the AMD-K6™-2E+ Processor—EAX
LRU (Least Recently Used). For the 4-way set associative L2 cache,
each way has a 2-bit LRU field for each sector. Values for the
LRU field are 00b, 01b, 10b, and 11b, where 00b indicates that
the sector is “most recently used,” and 11b indicates that the
sector is “least recently used” (see Figure 96 on page 268).
EAX[7:6] indicate LRU information for Way 0, EAX[5:4] for
Way 1, EAX[3:2] for Way 2, and EAX[1:0] for Way 3.
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7
6
Way 0
23542A/0—September 2000
5
4
3
Way 1
2
Way 2
1
0
Way 3
LRU Values
00b Most Recently Used
01b Used More Recent Than 10b, But Less Recent Than 00b
10b Used More Recent Than 11b, But Less Recent Than 01b
11b Least Recently Used
Figure 96. LRU Byte
13.6
Debug
The AMD-K6-2E+ processor implements the standard x86
debug functions, registers, and exceptions. In addition, the
processor supports the I/O breakpoint debug extension. The
debug feature assists programmers and system designers
during software execution tracing by generating exceptions
when one or more events occur during processor execution. The
exception handler, or debugger, can be written to perform
various tasks, such as displaying the conditions that caused the
breakpoint to occur, displaying and modifying register or
memory contents, or single-stepping through program
execution.
The following sections describe the debug registers and the
various types of breakpoints and exceptions that the processor
supports.
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Debug Registers
Figures 97 through 100 show the 32-bit debug registers
supported by the processor.
Symbol
LEN 3
R/W 3
LEN 2
R/W 2
LEN 1
R/W 1
LEN 0
R/W 0
Description
Length of Breakpoint #3
Type of Transaction(s) to Trap
Length of Breakpoint #2
Type of Transaction(s) to Trap
Length of Breakpoint #1
Type of Transaction(s) to Trap
Length of Breakpoint #0
Type of Transaction(s) to Trap
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
LEN
3
R/W
3
LEN
2
R/W
2
LEN
1
R/W
1
LEN
0
R/W
0
G
D
G
E
8
7
6
5
L G L G
E 3 3 2
4
3
L G
2 1
2
Bits
31–30
29–28
27–26
25–24
23–22
21–20
19–18
17–16
1
0
L G
1 0
L
0
Reserved
Symbol
GD
GE
LE
G3
L3
G2
L2
G1
L1
G0
L0
Description
General Detect Enabled
Global Exact Breakpoint Enabled
Local Exact Breakpoint Enabled
Global Exact Breakpoint # 3 Enabled
Local Exact Breakpoint # 3 Enabled
Global Exact Breakpoint # 2 Enabled
Local Exact Breakpoint # 2 Enabled
Global Exact Breakpoint # 1 Enabled
Local Exact Breakpoint # 1 Enabled
Global Exact Breakpoint # 0 Enabled
Local Exact Breakpoint # 0 Enabled
Bit
13
9
8
7
6
5
4
3
2
1
0
Figure 97. Debug Register DR7
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
B B B
T S D
3
2
1
0
B
3
B
2
B
1
B
0
Reserved
Symbol
BT
BS
BD
B3
B2
B1
B0
Description
Breakpoint Task Switch
Breakpoint Single Step
Breakpoint Debug Access Detected
Breakpoint #3 Condition Detected
Breakpoint #2 Condition Detected
Breakpoint #1 Condition Detected
Breakpoint #0 Condition Detected
Bit
15
14
13
3
2
1
0
Figure 98. Debug Register DR6
DR5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Reserved
DR4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved
Figure 99. Debug Registers DR5 and DR4
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DR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
4
3
2
1
0
8
7
6
4
3
2
1
0
Breakpoint 3 32-bit Linear Address
DR2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Breakpoint 2 32-bit Linear Address
DR1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
5
Breakpoint 1 32-bit Linear Address
DR0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
5
Breakpoint 0 32-bit Linear Address
Figure 100. Debug Registers DR3, DR2, DR1, and DR0
DR3–DR0. The processor allows the setting of up to four
breakpoints. DR3–DR0 contain the linear addresses for
breakpoint 3 through breakpoint 0, respectively, and are
compared to the linear addresses of processor cycles to
determine if a breakpoint occurs. Debug register DR7 defines
the specific type of cycle that must occur in order for the
breakpoint to occur.
DR5–DR4. When debugging extensions are disabled (bit 3 of CR4
is set to 0), the DR5 and DR4 registers are mapped to DR7 and
DR6, respectively, in order to be software compatible with
previous generations of x86 processors. When debugging
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extensions are enabled (bit 3 of CR4 is set to 1), any attempt to
load DR5 or DR4 results in an undefined opcode exception.
Likewise, any attempt to store DR5 or DR4 also results in an
undefined opcode exception.
DR6. If a breakpoint is enabled in DR7, and the breakpoint
conditions as defined in DR7 occur, then the corresponding B
bit (B3–B0) in DR6 is set to 1. In addition, any other breakpoints
defined using these particular breakpoint conditions are
reported by the processor by setting the appropriate B-bits in
DR6, regardless of whether these breakpoints are enabled or
disabled. However, if a breakpoint is not enabled, a debug
exception does not occur for that breakpoint.
If the processor decodes an instruction that writes or reads DR7
through DR0, the BD bit (bit 13) in DR6 is set to 1 (if enabled in
DR7) and the processor generates a debug exception. This
operation allows control to pass to the debugger prior to debug
register access by software.
If the Trap Flag (bit 8) of the EFLAGS register is set to 1, the
processor generates a debug exception after the successful
execution of every instruction (single-step operation) and sets
the BS bit (bit 14) in DR6 to indicate the source of the
exception.
When the processor switches to a new task and the debug trap
bit (T bit) in the corresponding Task State Segment (TSS) is set
to 1, the processor sets the BT bit (bit 15) in DR6 and generates
a debug exception.
DR7. When set to 1, L3–L0 locally enable breakpoints 3 through
0, respectively. L3–L0 are set to 0 whenever the processor
executes a task switch. Setting L3–L0 to 0 disables the
breakpoints and ensures that these particular debug exceptions
are only generated for a specific task.
When set to 1, G3–G0 globally enable breakpoints 3 through 0,
respectively. Unlike L3–L0, G3–G0 are not set to 0 whenever the
processor executes a task switch. Not setting G3–G0 to 0 allows
breakpoints to remain enabled across all tasks. If a breakpoint
is enabled globally but disabled locally, the global enable
overrides the local enable.
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The LE (bit 8) and GE (bit 9) bits in DR7 have no effect on the
operation of the processor and are provided in order to be
software-compatible with previous generations of x86
processors.
When set to 1, the GD bit in DR7 (bit 13) enables the debug
exception associated with the BD bit (bit 13) in DR6. This bit is
set to 0 when a debug exception is generated.
LEN3–LEN0 and RW3–RW0 are two-bit fields in DR7 that
specify the length and type of each breakpoint as defined in
Table 54.
Table 54. DR7 LEN and RW Definitions
LEN Bits1
RW Bits
00b
00b2
00b
Breakpoint
Instruction Execution
One-byte Data Write
01b
01b
11b
Two-byte Data Write
Four-byte Data Write
00b
One-byte I/O Read or Write
01b
10b
3
Two-byte I/O Read or Write
11b
Four-byte I/O Read or Write
00b
One-byte Data Read or Write
01b
11b
11b
Two-byte Data Read or Write
Four-byte Data Read or Write
Notes:
1. LEN bits equal to 10b is undefined.
2. When RW equals 00b, LEN must be equal to 00b.
3. When RW equals 10b, debugging extensions (DE) must be enabled (bit 3 of CR4 must be set to 1).
If DE is set to 0, then RW equal to 10b is undefined.
Debug Exceptions
A debug exception is categorized as either a debug trap or a
debug fault.
■
■
A debug trap calls the debugger following the execution of
the instruction that caused the trap.
A debug fault calls the debugger prior to the execution of the
instruction that caused the fault.
All debug traps and faults generate either an Interrupt 01h or
an Interrupt 03h exception.
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Interrupt 01h. The following events are considered debug traps
that cause the processor to generate an Interrupt 01h
exception:
■
■
■
Enabled breakpoints for data and I/O cycles
Single Step Trap
Task Switch Trap
The following events are considered debug faults that cause the
processor to generate an Interrupt 01h exception:
■
■
Enabled breakpoints for instruction execution
BD bit in DR6 set to 1
Interrupt 03h. The INT 3 instruction is defined in the x86
architecture as a breakpoint instruction. This instruction
causes the processor to generate an Interrupt 03h exception.
This exception is a debug trap because the debugger is called
following the execution of the INT 3 instruction.
The INT 3 instruction is a one-byte instruction (opcode CCh)
typically used to insert a breakpoint in software by writing CCh
to the address of the first byte of the instruction to be trapped
(the target instruction). Following the trap, if the target
instruction is to be executed, the debugger must replace the
INT 3 instruction with the first byte of the target instruction.
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14
14.1
Clock Control
Clock Control States
The standard-power versions of the AMD-K6-2E+ processor
support five modes of clock control. The low-power versions of
the AMD-K6-2E+ processor support six modes of clock control.
The processor can transition between these modes to maximize
performance, to minimize power dissipation, or to provide a
balance between performance and power. (See “Power
Dissipation” on page 289 for the maximum power dissipation of
t h e A M D -K 6 -2 E + p ro c e s s o r w i t h i n t h e n o r m a l a n d
reduced-power states.) The clock-control states supported are:
■
■
■
■
■
■
Chapter 14
Normal State—The processor is running in Real Mode,
Virtual-8086 Mode, Protected Mode, or System Management
Mode (SMM). In this state, all clocks are running—including
the external bus clock CLK and the internal processor
clock—and the full features and functions of the processor
are available.
Halt State—This low-power state is entered following the
successful execution of the HLT instruction. During this
state, the internal processor clock is stopped.
Stop Grant State—This low-power state is entered following
the recognition of the assertion of the STPCLK# signal.
During this state, the internal processor clock is stopped.
Stop Grant Inquire State—This state is entered from the
Halt state and the Stop Grant state as the result of a
system-initiated inquire cycle.
Enhanced Power Management (EPM) Stop Grant State: This
low-power state is available on low--power versions of the
processor. It is entered following the write of a non-zero
value to the SGTC field of the EPM 16-byte I/O block for the
purpose of performing dynamic processor core frequency
and voltage ID state transitions using AMD PowerNow!
technology. During this state, the internal processor clock is
stopped.
Stop Clock State—This low-power state is entered from the
Stop Grant state when the CLK signal is stopped.
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Figure 101 and Figure 102 illustrate the clock control state
transitions on the standard-power and low-power versions,
respectively, of the AMD-K6-2E+ processor. Each of the
reduced-power states are described in the following sections.
HLT Instruction
RESET, SMI#, INIT,
or INTR Asserted
Halt
State
EADS# Asserted
Writeback
Completed
Normal Mode
- Real
- Virtual-8086
- Protected
- SMM
Stop Grant
Inquire
State
STPCLK# Asserted
STPCLK# Negated,
or RESET Asserted
EADS# Asserted
Stop Grant
State
Writeback
Completed
CLK
Started
CLK
Stopped
Stop Clock
State
Figure 101. Clock Control State Transitions for Standard-Power Versions of the AMD-K6™-2E+
Processor
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HLT Instruction
RESET, SMI#, INIT,
or INTR Asserted
Non-zero value written to SGTC
Normal Mode
– Real
– Virtual-8086
– Protected
– SMM
SGTC timer expires
STPCLK# Negated,
or RESET Asserted
STPCLK# Asserted
EPM Stop Grant
State
Stop Grant
State
CLK
Stopped
EADS# Asserted
Writeback
Completed
EADS# Asserted
Halt
State
Stop Grant
Inquire
State
CLK
Started
CLK
Started
CLK
Stopped
Stop Clock
State
Writeback
Completed
Figure 102. Clock Control State Transitions for Low-Power Versions of the AMD-K6™-2E+ Processor
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Halt State
Enter Halt State
During the execution of the HLT instruction, the AMD-K6-2E+
processor executes a Halt special cycle. After BRDY# is
sampled asserted during this cycle, and then EWBE# is also
sampled asserted (if not masked off), the processor enters the
Halt state in which the processor disables most of its internal
clock distribution. In order to support the following operations,
the internal phase-lock loop (PLL) still runs, and some internal
resources are still clocked in the Halt state:
■
■
■
■
Inquire Cycles—The processor continues to sample AHOLD,
BOFF#, and HOLD in order to support inquire cycles that
are initiated by the system logic. The processor transitions to
the Stop Grant Inquire state during the inquire cycle. After
returning to the Halt state following the inquire cycle, the
processor does not execute another Halt special cycle.
Flush Cycles—The processor continues to sample FLUSH#.
If FLUSH# is sampled asserted, the processor performs the
flush operation in the same manner as it is performed in the
Normal state. Upon completing the flush operation, the
processor executes the Halt special cycle, which indicates
the processor is in the Halt state.
Time Stamp Counter (TSC)—The TSC continues to count in
the Halt state.
Signal Sampling—The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
After entering the Halt state, all signals driven by the processor
retain their state as they existed following the completion of
the Halt special cycle.
Exit Halt State
14.3
The AMD-K6-2E+ processor remains in the Halt state until it
samples INIT, INTR (if interrupts are enabled), NMI, RESET, or
SMI# asserted. If any of these signals is sampled asserted, the
processor returns to the Normal state and performs the
corresponding operation. All of the normal requirements for
recognition of these input signals apply within the Halt state.
Stop Grant State
Enter Stop Grant
State
278
After recognizing the assertion of STPCLK#, the AMD-K6-2E+
processor flushes its instruction pipelines, completes all
pending and in-progress bus cycles, and acknowledges the
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STPCLK# assertion by executing a Stop Grant special bus cycle.
After BRDY# is sampled asserted during this cycle, and then
EWBE# is also sampled asserted (if not masked off), the
processor enters the Stop Grant state.
The Stop Grant state is like the Halt state in that the processor
disables most of its internal clock distribution in the Stop Grant
state.
In order to support the following operations, the internal PLL
still runs, and some internal resources are still clocked in the
Stop Grant state:
■
Inquire cycles—The processor transitions to the Stop Grant
Inquire state during an inquire cycle. After returning to the
Stop Grant state following the inquire cycle, the processor
does not execute another Stop Grant special cycle.
■
Time Stamp Counter (TSC)—The TSC continues to count in
the Stop Grant state.
Signal Sampling—The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
■
FLUSH# is not recognized in the Stop Grant state (unlike while
in the Halt state).
Upon entering the Stop Grant state, all signals driven by the
processor retain their state as they existed following the
completion of the Stop Grant special cycle.
Exit Stop Grant State
The AMD-K6-2E+ processor remains in the Stop Grant state
until it samples STPCLK# negated or RESET asserted. If
STPCLK# is sampled negated, the processor returns to the
Normal state in less than 10 bus clock (CLK) periods. After the
transition to the Normal state, the processor resumes execution
at the instruction boundary on which STPCLK# was initially
recognized.
If STPCLK# is recognized as negated in the Stop Grant state
and subsequently sampled asserted prior to returning to the
Normal state, the AMD-K6-2E+ processor guarantees that a
minimum of one instruction is executed prior to re-entering the
Stop Grant state.
If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or
SMI# are sampled asserted in the Stop Grant state, the
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processor latches the edge-sensitive signals (INIT, FLUSH#,
NMI, and SMI#), but otherwise does not exit the Stop Grant
state to service the interrupt. When the processor returns to the
Normal state due to sampling STPCLK# negated, any pending
interrupts are recognized after returning to the Normal state.
To ensure their recognition, all of the normal requirements for
these input signals apply within the Stop Grant state.
If RESET is sampled asserted in the Stop Grant state, the
processor immediately returns to the Normal state and the
reset process begins.
14.4
Stop Grant Inquire State
Enter Stop Grant
Inquire State
The Stop Grant Inquire state is entered from the Stop Grant
state or the Halt state when EADS# is sampled asserted during
an inquire cycle initiated by the system logic. The AMD-K6-2E+
processor responds to an inquire cycle in the same manner as in
the Normal state by driving HIT# and HITM#. If the inquire
cycle hits a modified cache line, the processor performs a
writeback cycle.
Exit Stop Grant
Inquire State
Following the completion of any writeback, the processor
returns to the state from which it entered the Stop Grant
Inquire state.
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14.5
EPM Stop Grant State
Enter EPM Stop Grant
State
This state is supported on the low-power versions of the
AMD-K6-2E+ processor. After receiving a write of a non-zero
value to the SGTC (Stop Grant Time-out Counter) field located
within the EPM 16-byte I/O block, the processor flushes its
instruction pipelines, completes all pending and in-progress
bus cycles, and performs the following:
■
■
Drives the processor VID[4:0] output pins to the value stored
in the VIDO field of the EPM 16-byte I/O block (see “EPM
16-Byte I/O Block” on page 146) if the VIDC bit is set to 1.
Forwards the processor-to-bus clock ratio stored in the
IBF[2:0] field of the EPM 16-byte I/O block to the internal
PLL if the BDC[1:0] value is set to 1xb.
The EPM Stop Grant state is like the Halt state in that the
processor disables most of its internal clock distribution in the
EPM Stop Grant state. In order to support the following
operations, the internal PLL still runs, and some internal
resources are still clocked in the EPM Stop Grant state.
■
■
Time Stamp Counter (TSC): The TSC continues to count in
the EPM Stop Grant state.
Signal Sampling: The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
Unlike the Halt and Stop Grant states, system-initiated inquire
cycles are not supported and must be prevented during the
EPM Stop Grant state.
FLUSH# is not recognized in the EPM Stop Grant state (unlike
while in the Halt state).
Upon entering the EPM Stop Grant state, all signals driven by
the processor retain their state as they existed following the
completion of the EPM Stop Grant special cycle.
Exit EPM Stop Grant
State
Chapter 14
The processor remains in the EPM Stop Grant state until the
allotted time expires, as determined by the value written to the
SGTC field, or until RESET is sampled asserted. Once the
allotted time expires, the processor returns to the Normal state.
After the transition to the Normal state, the processor resumes
execution at the instruction boundary on which the EPM Stop
Grant state was entered.
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If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or
SMI# are sampled asserted in the EPM Stop Grant state, the
processor latches the edge-sensitive signals (INIT, FLUSH#,
NMI, and SMI#), but otherwise does not exit the EPM Stop
Grant state to service the interrupt. When the processor returns
to the Normal state, any pending interrupts are recognized. To
ensure their recognition, all of the normal requirements for
these input signals apply within the EPM Stop Grant state.
If RESET is sampled asserted in the EPM Stop Grant state, the
processor immediately returns to the Normal state and the
reset process begins.
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14.6
Stop Clock State
Enter Stop Clock
State
If the CLK signal is stopped while the AMD-K6-2E+ processor is
in the Stop Grant state, the processor enters the Stop Clock
state. Because all internal clocks and the PLL are not running
in the Stop Clock state, the Stop Clock state represents the
minimum-power state of all clock control states. The CLK signal
must be held Low while it is stopped.
The Stop Clock state cannot be entered from the Halt state.
INTR is the only input signal that is allowed to change states
while the processor is in the Stop Clock state. However, INTR is
not sampled until the processor returns to the Stop Grant state.
All other input signals must remain unchanged in the Stop
Clock state.
Exit Stop Clock State
The AMD-K6-2E+ processor returns to the Stop Grant state
from the Stop Clock state after the CLK signal is started and
the internal PLL has stabilized. PLL stabilization is achieved
after the CLK signal has been running within its specification
for a minimum of 1.0 ms.
The frequency of CLK when exiting the Stop Clock state can be
different than the frequency of CLK when entering the Stop
Clock state.
The state of the BF[2:0] signals when exiting the Stop Clock
state is ignored because the BF[2:0] signals are only sampled
during the falling transition of RESET.
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15
Electrical Data
This chapter includes specifications for the operating ranges,
absolute ratings, and DC characteristics of the AMD-K6-2E+
embedded processor. Nominal and maximum power dissipation
values for the AMD-K6-2E+ processor during normal and
reduced power states are listed. The chapter concludes with a
discussion of power and grounding requirements.
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Operating Ranges
The AMD-K6-2E+ processor is designed to provide functional
operation if the voltage and temperature parameters are within
the limits defined in Table 55 and Table 56.
Table 55. Operating Ranges for Low-Power AMD-K6™-2E+ Devices
Parameter Parameter Description
350 MHz
400 MHz
450 MHz
Core Supply Voltage (Minimum)
1.4 V2
1.5 V3
1.6 V4
VCC21
Core Supply Voltage (Nominal)
1.5 V2
1.6 V3
1.7 V4
VCC21
Core Supply Voltage (Maximum)
1.6 V2
1.7 V3
1.8 V4
VCC31
I/O Supply Voltage (Minimum)
3.135 V
VCC31
I/O Supply Voltage (Nominal)
3.30 V
VCC31
I/O Supply Voltage (Maximum)
3.6 V
TCASE
Case Temperature (Minimum)5
0•C
TCASE
Case Temperature (Maximum)5
85•C
VCC21
Notes:
1.
2.
3.
4.
5.
VCC2 and VCC3 are referenced from VSS.
VCC2 specification for 1.5-V component.
VCC2 specification for 1.6-V component.
VCC2 specification for 1.7-V component.
Case temperature range required for AMD-K6-2E+/350xUZ, AMD-K6-2E+/400xTZ, and AMD-K6-2E+/450xPZ valid ordering part number combinations, where x represents the package type. See Table 79 on page 334 for a complete list of valid OPNs.
Table 56. Operating Ranges for Standard-Power AMD-K6™-2E+ Devices
Parameter Parameter Description
VCC21
400 MHz
Core Supply Voltage (Minimum)2
450 MHz
500 MHz
1.9 V
VCC21
Core Supply Voltage (Nominal)
VCC21
Core Supply Voltage (Maximum)2
VCC31
I/O Supply Voltage (Minimum)
3.135 V
VCC31
I/O Supply Voltage (Nominal)
3.30 V
VCC31
I/O Supply Voltage (Maximum)
3.6 V
TCASE
Case Temperature (Minimum)3
0•C
TCASE
Case Temperature (Maximum)5
70•C
2
2.0 V
2.1 V
Notes:
1. VCC2 and VCC3 are referenced from VSS.
2. VCC2 specification for 2.0-V component
3. Case temperature range required for AMD-K6-2E+/xxxyACR valid ordering part number combinations, where xxx represents the processor core frequency and y represents the package type, as defined in Table 79 on page 334.
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15.2
Absolute Ratings
The AMD-K6-2E+ processor is not designed to be operated
beyond the operating ranges listed in Table 55 and Table 56.
Exposure to conditions outside these operating ranges for
extended periods of time can affect long-term reliability.
Permanent damage can occur if the absolute ratings listed in
Table 57 are exceeded.
Table 57. Absolute Ratings
Parameter
Description
Minimum
Maximum
VCC2
Core Supply Voltage
–0.5 V
2.2 V
VCC3
I/O Supply Voltage
–0.5 V
3.6 V
VPIN1
Voltage on Any I/O Pin
–0.5 V
VCC3 + 0.4 V and ˆ 3.8 V
Case Temperature
–65•C
+110•C
Storage Temperature
–65•C
+150•C
TCASE (under bias)
TSTORAGE
Notes:
1. VPIN (the voltage on any I/O pin) must not be greater than 0.4 V above the voltage being applied to VCC3. In addition, the VPIN voltage
must never exceed 3.8 V.
15.3
DC Characteristics
The DC characteristics of the AMD-K6-2E+ processor are shown
in Table 58.
Table 58. DC Characteristics for the AMD-K6™-2E+ Processor
Symbol
Preliminary Data
Parameter Description
Min
Max
VIL
Input Low Voltage
–0.3 V
+0.8 V
VIH1
Input High Voltage
2.0 V
VCC3+0.3 V
VOL
Output Low Voltage
VOH
Output High Voltage
0.4 V
Chapter 15
Electrical Data
IOL = 4.0-mA load
IOH = 3.0-mA load
2.4 V
1.5-V Power Supply Current
ICC2
1.6-V Power Supply Current
Low Power
1.7-V Power Supply Current
Comments
5.30 A
350 MHz2,3
6.15 A
400 MHz2,3,4
7.60 A
450 MHz2,3
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Table 58. DC Characteristics for the AMD-K6™-2E+ Processor (continued)
Symbol
ICC2
Standard
Power
ICC3
Standard
and Low
Power
Preliminary Data
Parameter Description
Min
2.0 V Power Supply Current
3.3 V Power Supply Current
Max
8.70 A
400 MHz3,4,5
9.25 A
450 MHz3,5
9.75 A
500 MHz3,5
0.64 A
350 MHz3,6
0.65 A
400 MHz3,4,6
0.66 A
450 MHz3,6
0.68 A
500 MHz3,6
ILI7
Input Leakage Current
–15 mA
ILO7
Output Leakage Current
–15 mA
Input Leakage Current Bias with Pullup
–500 mA
IIL
8
Comments
IIH9
Input Leakage Current Bias with Pulldown
CIN
Input Capacitance
10 pF
COUT
Output Capacitance
15 pF
COUT
I/O Capacitance
20 pF
CCLK
CLK Capacitance
10 pF
CTIN
Test Input Capacitance (TDI, TMS, TRST#)
10 pF
CTOUT
Test Output Capacitance (TDO)
15 pF
CTCK
TCK Capacitance
10 pF
500 mA
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = Maximum VCC2 as listed in Table 55 on page 286— The maximum power supply current must be taken into account when
designing a power supply.
3. This specification applies to components using a CLK frequency of 100 MHz.
4. This specification applies to components using a CLK frequency of 66 MHz (66-MHz bus applies to 400-MHz part only).
5. VCC2 = 2.1 V — The maximum power supply current must be taken into account when designing a power supply.
6. VCC3 = 3.6 V—The maximum power supply current must be taken into account when designing a power supply.
7. Refers to inputs and I/O without an internal pullup resistor and 0 ˆ VIN ˆ VCC3.
8. Refers to inputs with an internal pullup and VIL = 0.4 V.
9. Refers to inputs with an internal pulldown and VIH = 2.4 V.
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15.4
Power Dissipation
Table 59 and Table 60 contain the application power dissipation
of the low-power and standard-power AMD-K6-2E+ processor
during normal and reduced power states. Table 61 on page 290
shows the supported voltages and operating frequencies for
low-power versions of AMD-K6-2E+ processors enabled with
AMD PowerNow! technology.
Table 59. Power Dissipation for Low-Power AMD-K6™-2E+ Devices
Power Dissipation
Application Power
Active3
AMD PowerNow! Technology
Power Saving Mode4
Thermal Design Power (Maximum)5,6
Stop Grant/Halt (Maximum)6,7
Stop Clock (Maximum)6,8
350 MHz1
400 MHz1,2
450 MHz1
5.60 W
6.90 W
8.70 W
2.95 W
7.50 W
9.50 W
VCC Nominal
12.00 W
2.50 W
VCC Nominal
1.60 W
Lowest Operating VCC9
1.90 W
1.30 W
Notes:
1. This specification applies to components using a CLK frequency of 100 MHz.
2. This specification applies to components using a CLK frequency of 66 MHz.
3. The active application power measurements were taken by running a suite of embedded benchmarks covering four major
embedded market segments: automotive, office automation, networking, and telecommunications.
4. AMD PowerNow! technology Power Saving Mode represents averaged values measured while running the processor in the lowest
settings supported by AMD PowerNow! technology.
5. The maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal
dissipation for the AMD-K6-2E+ processor.
6. Maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with
VCC2 = Nominal VCC2 as listed in Table 55 on page 286 and VCC3 = 3.3 V.
7. The CLK signal and the internal PLL are still running, but most internal clocking has stopped.
8. The CLK signal, the internal PLL, and all internal clocking has stopped.
9. The lowest operating VCC is 1.4 V.
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Table 60. Power Dissipation for Standard-Power AMD-K6™-2E+ Devices
Power Dissipation
Active3
Application Power
Thermal Design Power (Maximum)4,5
400 MHz1,2
450 MHz1
500 MHz1
11.40 W
12.65 W
13.90 W
16.50 W
17.50 W
18.50 W
Stop Grant/Halt (Maximum)5,6
4.50 W
Stop Clock (Maximum)5,7
4.00 W
Notes:
1. This specification applies to components using a CLK frequency of 100 MHz.
2. This specification applies to components using a CLK frequency of 66 MHz.
3. The active application power measurements were taken by running a suite of embedded benchmarks covering four major
embedded market segments: automotive, office automation, networking, and telecommunications.
4. The maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal
dissipation for the AMD-K6-2E+ processor.
5. Maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with
VCC2 = 2.0 V and VCC3 = 3.3 V.
6. The CLK signal and the internal PLL are still running, but most internal clocking has stopped.
7. The CLK signal, the internal PLL, and all internal clocking has stopped.
Table 61. Supported Voltages and Operating Frequencies for Low-Power AMD-K6™-2E+ Processors
Enabled with AMD PowerNow!™ Technology
Ordering Part Number1
AMD-K6-2E+/450APZ
AMD-K6-2E+/400xTZ
AMD-K6-2E+/350xUZ
Core Voltage
Range of Supported
Operating Frequencies2
Active Power3
1.7 V
450–200 MHz
8.70–4.90 W
1.6 V
400–200 MHz
6.90–4.20 W
1.5 V
350–200 MHz
5.60–3.70 W
1.4 V
300–200 MHz
4.30–2.95 W
1.6 V
400–200 MHz
6.90–4.20 W
1.5 V
350–200 MHz
5.60–3.70 W
1.4 V
300–200 MHz
4.30–2.95 W
1.5 V
350–200 MHz
5.60–3.70 W
1.4 V
300–200 MHz
4.30–2.95 W
Notes:
1. An x in this column represents the package type. See Table 79, “AMD-K6™-2E+ Embedded Processor Valid Ordering Part Number Combinations,” on page 334.
2. AMD PowerNow! technology enables the operating frequency to step down in increments corresponding to the available bus frequency
multipliers. Note that 250-MHz operation is not supported due to exclusion of 2.5 bus frequency multiplier.
3. Active application power dissipation for highest and lowest supported frequency at specified voltage.
290
Electrical Data
Chapter 15
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
15.5
Power and Grounding
Power Connections
The AMD-K6-2E+ processor is a dual voltage device. Two
separate supply voltages are required: VCC2 and VCC3.
■
■
VCC2 provides the core voltage for the processor.
VCC3 provides the I/O voltage.
See “Operating Ranges” on page 286 for the value and range of
VCC2 and VCC3.
The power and ground pins for each package are listed in
Table 76 on page 325 and Table 78 on page 329. Table 74 on
page 321 lists the pin differences between the two packages.
The large number of power and ground pins are provided to
ensure that the processor and package maintain a clean and
stable power distribution network.
For proper operation and functionality, all VCC2, VCC3, and VSS
pins must be connected to the appropriate planes in the circuit
board. The power planes have been arranged in a pattern to
simplify routing and minimize crosstalk on the circuit board.
The isolation region between two voltage planes must be at
least 0.254mm if they are in the same layer of the circuit board.
( S ee Figure 1 03 o n p a ge 2 92 .) In ord er t o ma int ain a
low-impedance current sink and reference, the ground plane
must never be split.
Although the AMD-K6-2E+ processor has two separate supply
voltages, there are no special power sequencing requirements.
The best procedure is to minimize the time between which VCC2
and VCC3 are either both on or both off.
Chapter 15
Electrical Data
291
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
C19
C21
C2
C11
CC4
+
+
CC5
CC6
C12
C13
VCC3 (I/O) Plane
C26
CC10
C22
C23
C24
CC8
C1
+
+
+
C25
C29
C27
C30
C28
C31
CC7
CC3
C15
C7
C9
C20
C16
C6
C10
C17
C18
C5
CC9
C8
C14
0.254mm (min.) for
isolation region
VCC2 (Core) Plane
CC1
CC2
Figure 103. Suggested Component Placement for CPGA Package
Decoupling
Recommendations
In addition to the isolation region mentioned in “Power
Connections” on page 291, adequate decoupling capacitance is
required between the two system power planes and the ground
plane to minimize ringing and to provide a low-impedance path
for return currents. Suggested decoupling capacitor placement
is shown in Figure 103.
Surface-mounted capacitors should be used under the
processor’s ZIF socket to minimize resistance and inductance in
the lead lengths while maintaining minimal height. For
information and recommendations about the specific value,
quantity, and location of the capacitors, see the AMD-K6 ®
Processor Power Supply Design Application Note, order# 21103.
292
Electrical Data
Chapter 15
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Pin Connection
Requirements
For proper operation, the following requirements for signal pin
connections must be met:
■
■
■
Do not drive address and data signals into large capacitive
loads at high frequencies. If necessary, use buffer chips to
drive large capacitive loads.
Leave all NC (no-connect) pins unconnected.
Unused inputs should always be connected to an
appropriate signal level.
•
Active Low inputs that are not being used should be
connected to VCC3 through a 20-kW pullup resistor.
Active High inputs that are not being used should be
connected to GND through a pulldown resistor.
Reserved signals can be treated in one of the following ways:
•
■
•
As no-connect (NC) pins, in which case these pins are left
unconnected
•
As pins connected to the system logic as defined by the
industry-standard Super7 and Socket 7 interface
Any combination of NC and Socket 7 pins
Keep trace lengths to a minimum.
•
■
Chapter 15
Electrical Data
293
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
294
Electrical Data
23542A/0—September 2000
Chapter 15
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
16
Signal Switching Characteristics
The AMD-K6-2E+ processor signal switching characteristics are
presented in Table 62 through Table 71 on the following pages.
Valid delay, float, setup, and hold timing specifications are
listed. These specifications are provided for the system
designer to determine if the timings necessary for the processor
to interface with the system logic are met.
■
■
■
■
Table 62 on page 296 and Table 63 on page 297 contain the
switching characteristics of the CLK input.
Table 64 on page 298 through Table 67 on page 304 contain
the timings for the normal operation signals.
Table 68 on page 306 and Table 69 on page 307 contain the
timings for RESET and the configuration signals.
Table 70 on page 308 and Table 71 on page 308 contain the
timings for the test operation signals.
All signal timings provided are:
■
■
■
■
Chapter 16
Measured between CLK, TCK, or RESET at 1.5 V and the
corresponding signal at 1.5 V—this applies to input and
output signals that are switching from Low to High, or from
High to Low
Based on input signals applied at a slew rate of 1 V/ns
between 0 V and 3 V (rising) and 3 V to 0 V (falling)
Valid within the operating ranges given in “Operating
Ranges” on page 286
Based on a load capacitance (CL) of 0 pF
Signal Switching Characteristics
295
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
16.1
23542A/0—September 2000
CLK Switching Characteristics
Table 62 and Table 63 on page 297 contain the switching
characteristics of the CLK input to the AMD-K6-2E+ processor
for 100-MHz and 66-MHz bus operation, respectively, as
measured at the voltage levels indicated by Figure 104 on page
297.
The CLK Period Stability parameter specifies the variance
(jitter) allowed between successive periods of the CLK input
measured at 1.5 V. This parameter must be considered as one of
the elements of clock skew between the AMD-K6-2E+ processor
and the system logic.
16.2
Clock Switching Characteristics for 100-MHz Bus Operation
Table 62. CLK Switching Characteristics for 100-MHz Bus Operation
Symbol
Parameter Description
Preliminary Data
Figure
Min
Max
Frequency
33.3 MHz
100 MHz
t1
CLK Period
10.0 ns
104
t2
CLK High Time
3.0 ns
104
t3
CLK Low Time
3.0 ns
104
t4
CLK Fall Time
0.15 ns
1.5 ns
104
t5
CLK Rise Time
0.15 ns
1.5 ns
104
CLK Period Stability1
Comments
In Normal Mode
In Normal Mode
– 250 ps
Notes:
1. The jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz.
296
Signal Switching Characteristics
Chapter 16
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
16.3
Clock Switching Characteristics for 66-MHz Bus Operation
Table 63. CLK Switching Characteristics for 66-MHz Bus Operation
Symbol
Preliminary Data
Parameter Description
Figure
Min
Max
Frequency
33.3 MHz
66.6 MHz
t1
CLK Period
15.0 ns
30.0 ns
t2
CLK High Time
4.0 ns
104
t3
CLK Low Time
4.0 ns
104
t4
CLK Fall Time
0.15 ns
1.5 ns
104
t5
CLK Rise Time
0.15 ns
1.5 ns
104
Comments
In Normal Mode
104
In Normal Mode
– 250 ps
CLK Period Stability1
Notes:
1. The jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz.
t2
2.0 V
1.5 V
t3
0.8 V
t4
t5
t1
Figure 104. CLK Waveform
Chapter 16
Signal Switching Characteristics
297
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
16.4
Valid Delay, Float, Setup, and Hold Timings
Valid Delay and Float
Timing
Setup and Hold
Timing
The maximum valid delay timings are provided to allow a
system designer to determine if setup times to the system logic
can be met. Likewise, the minimum valid delay timings are used
to analyze hold times to the system logic.
■
Valid delay and float timings are given for output signals
during functional operation and are given relative to the
rising edge of CLK.
■
During boundary-scan testing, valid delay and float timings
for output signals are with respect to the falling edge of
TCK.
The setup and hold time requirements for the AMD-K6-2E+
processor input signals must be met by the system logic to
assure the proper operation of the AMD-K6-2E+ processor.
■
16.5
23542A/0—September 2000
The setup and hold timings during functional and
boundary-scan test mode are given relative to the rising
edge of CLK and TCK, respectively.
Output Delay Timings for 100-MHz Bus Operation
Table 64. Output Delay Timings for 100-MHz Bus Operation
Symbol
298
Parameter Description
Preliminary Data
Figure
Min
Max
1.1 ns
4.0 ns
106
7.0 ns
107
4.0 ns
106
7.0 ns
107
4.0 ns
106
7.0 ns
107
5.5 ns
106
7.0 ns
107
t6
A[31:3] Valid Delay
t7
A[31:3] Float Delay
t8
ADS# Valid Delay
t9
ADS# Float Delay
t10
ADSC# Valid Delay
t11
ADSC# Float Delay
t12
AP Valid Delay
t13
AP Float Delay
t14
APCHK# Valid Delay
1.0 ns
4.5 ns
106
t15
BE[7:0]# Valid Delay
1.0 ns
4.0 ns
106
t16
BE[7:0]# Float Delay
7.0 ns
107
t17
BREQ Valid Delay
1.0 ns
4.0 ns
106
t18
CACHE# Valid Delay
1.0 ns
4.0 ns
106
1.0 ns
1.0 ns
1.0 ns
Signal Switching Characteristics
Chapter 16
Preliminary Information
23542A/0—September 2000
AMD-K6™-2E+ Embedded Processor Data Sheet
Table 64. Output Delay Timings for 100-MHz Bus Operation (continued)
Symbol
Parameter Description
t19
CACHE# Float Delay
t20
D/C# Valid Delay
t21
D/C# Float Delay
t22
D[63:0] Write Data Valid Delay
t23
D[63:0] Write Data Float Delay
t24
DP[7:0] Write Data Valid Delay
t25
DP[7:0] Write Data Float Delay
t26
FERR# Valid Delay
t27
Preliminary Data
Min
Max
Figure
7.0 ns
107
4.0 ns
106
7.0 ns
107
4.5 ns
106
7.0 ns
107
4.5 ns
106
7.0 ns
107
1.0 ns
4.5 ns
106
HIT# Valid Delay
1.0 ns
4.0 ns
106
t28
HITM# Valid Delay
1.1 ns
4.0 ns
106
t29
HLDA Valid Delay
1.0 ns
4.0 ns
106
t30
LOCK# Valid Delay
1.1 ns
4.0 ns
106
t31
LOCK# Float Delay
7.0 ns
107
t32
M/IO# Valid Delay
4.0 ns
106
t33
M/IO# Float Delay
7.0 ns
107
t34
PCD Valid Delay
4.0 ns
106
t35
PCD Float Delay
7.0 ns
107
t36
PCHK# Valid Delay
1.0 ns
4.5 ns
106
t37
PWT Valid Delay
1.0 ns
4.0 ns
106
t38
PWT Float Delay
7.0 ns
107
t39
SCYC Valid Delay
4.0 ns
106
t40
SCYC Float Delay
7.0 ns
107
t41
SMIACT# Valid Delay
1.0 ns
4.0 ns
106
t42
W/R# Valid Delay
1.0 ns
4.0 ns
106
t43
W/R# Float Delay
7.0 ns
107
Chapter 16
1.0 ns
1.3 ns
1.3 ns
1.0 ns
1.0 ns
1.0 ns
Signal Switching Characteristics
299
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
16.6
23542A/0—September 2000
Input Setup and Hold Timings for 100-MHz Bus Operation
Table 65. Input Setup and Hold Timings for 100-MHz Bus Operation
Symbol
Preliminary Data
Min
Max
Figure
t44
A[31:5] Setup Time
3.0 ns
108
t45
A[31:5] Hold Time
1.0 ns
108
t461
A20M# Setup Time
3.0 ns
108
t471
A20M# Hold Time
1.0 ns
108
t48
AHOLD Setup Time
3.5 ns
108
t49
AHOLD Hold Time
1.0 ns
108
t50
AP Setup Time
1.7 ns
108
t51
AP Hold Time
1.0 ns
108
t52
BOFF# Setup Time
3.5 ns
108
t53
BOFF# Hold Time
1.0 ns
108
t54
BRDY# Setup Time
3.0 ns
108
t55
BRDY# Hold Time
1.0 ns
108
t56
BRDYC# Setup Time
3.0 ns
108
t57
BRDYC# Hold Time
1.0 ns
108
t58
D[63:0] Read Data Setup Time
1.7 ns
108
t59
D[63:0] Read Data Hold Time
1.5 ns
108
t60
DP[7:0] Read Data Setup Time
1.7 ns
108
t61
DP[7:0] Read Data Hold Time
1.5 ns
108
t62
EADS# Setup Time
3.0 ns
108
t63
EADS# Hold Time
1.0 ns
108
t64
EWBE# Setup Time
1.7 ns
108
t65
EWBE# Hold Time
1.0 ns
108
t662
FLUSH# Setup Time
1.7 ns
108
t672
FLUSH# Hold Time
1.0 ns
108
t68
HOLD Setup Time
1.7 ns
108
t69
HOLD Hold Time
1.5 ns
108
IGNNE# Setup Time
1.7 ns
108
t711
IGNNE# Hold Time
1.0 ns
108
t722
INIT Setup Time
1.7 ns
108
t70
300
Parameter Description
1
Signal Switching Characteristics
Chapter 16
Preliminary Information
23542A/0—September 2000
AMD-K6™-2E+ Embedded Processor Data Sheet
Table 65. Input Setup and Hold Timings for 100-MHz Bus Operation (continued)
Symbol
Parameter Description
Preliminary Data
Min
Max
Figure
t732
INIT Hold Time
1.0 ns
108
t741
INTR Setup Time
1.7 ns
108
t751
INTR Hold Time
1.0 ns
108
t76
INV Setup Time
1.7 ns
108
t77
INV Hold Time
1.0 ns
108
t78
KEN# Setup Time
3.0 ns
108
t79
KEN# Hold Time
1.0 ns
108
t80
NA# Setup Time
1.7 ns
108
t81
NA# Hold Time
1.0 ns
108
t822
NMI Setup Time
1.7 ns
108
t832
NMI Hold Time
1.0 ns
108
t842
SMI# Setup Time
1.7 ns
108
t852
SMI# Hold Time
1.0 ns
108
t861
STPCLK# Setup Time
1.7 ns
108
t871
STPCLK# Hold Time
1.0 ns
108
t88
WB/WT# Setup Time
1.7 ns
108
t89
WB/WT# Hold Time
1.0 ns
108
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold
times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold
times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain
asserted at least two clocks.
Chapter 16
Signal Switching Characteristics
301
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
16.7
23542A/0—September 2000
Output Delay Timings for 66-MHz Bus Operation
Table 66. Output Delay Timings for 66-MHz Bus Operation
Symbol
302
Parameter Description
Preliminary Data
Figure
Min
Max
1.1 ns
6.3 ns
106
10.0 ns
107
6.0 ns
106
10.0 ns
107
7.0 ns
106
10.0 ns
107
8.5 ns
106
10.0 ns
107
t6
A[31:3] Valid Delay
t7
A[31:3] Float Delay
t8
ADS# Valid Delay
t9
ADS# Float Delay
t10
ADSC# Valid Delay
t11
ADSC# Float Delay
t12
AP Valid Delay
t13
AP Float Delay
t14
APCHK# Valid Delay
1.0 ns
8.3 ns
106
t15
BE[7:0]# Valid Delay
1.0 ns
7.0 ns
106
t16
BE[7:0]# Float Delay
10.0 ns
107
t17
BREQ Valid Delay
1.0 ns
8.0 ns
106
t18
CACHE# Valid Delay
1.0 ns
7.0 ns
106
t19
CACHE# Float Delay
10.0 ns
107
t20
D/C# Valid Delay
7.0 ns
106
t21
D/C# Float Delay
10.0 ns
107
t22
D[63:0] Write Data Valid Delay
7.5 ns
106
t23
D[63:0] Write Data Float Delay
10.0 ns
107
t24
DP[7:0] Write Data Valid Delay
7.5 ns
106
t25
DP[7:0] Write Data Float Delay
10.0 ns
107
t26
FERR# Valid Delay
1.0 ns
8.3 ns
106
t27
HIT# Valid Delay
1.0 ns
6.8 ns
106
t28
HITM# Valid Delay
1.1 ns
6.0 ns
106
t29
HLDA Valid Delay
1.0 ns
6.8 ns
106
t30
LOCK# Valid Delay
1.1 ns
7.0 ns
106
t31
LOCK# Float Delay
10.0 ns
107
t32
M/IO# Valid Delay
5.9 ns
106
t33
M/IO# Float Delay
10.0 ns
107
t34
PCD Valid Delay
7.0 ns
106
t35
PCD Float Delay
10.0 ns
107
1.0 ns
1.0 ns
1.0 ns
1.0 ns
1.3 ns
1.3 ns
1.0 ns
1.0 ns
Signal Switching Characteristics
Chapter 16
Preliminary Information
23542A/0—September 2000
AMD-K6™-2E+ Embedded Processor Data Sheet
Table 66. Output Delay Timings for 66-MHz Bus Operation (continued)
Symbol
Parameter Description
Preliminary Data
Min
Max
Figure
t36
PCHK# Valid Delay
1.0 ns
7.0 ns
106
t37
PWT Valid Delay
1.0 ns
7.0 ns
106
t38
PWT Float Delay
10.0 ns
107
t39
SCYC Valid Delay
7.0 ns
106
t40
SCYC Float Delay
10.0 ns
107
t41
SMIACT# Valid Delay
1.0 ns
7.3 ns
106
t42
W/R# Valid Delay
1.0 ns
7.0 ns
106
t43
W/R# Float Delay
10.0 ns
107
Chapter 16
1.0 ns
Signal Switching Characteristics
303
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
16.8
23542A/0—September 2000
Input Setup and Hold Timings for 66-MHz Bus Operation
Table 67. Input Setup and Hold Timings for 66-MHz Bus Operation
Symbol
Preliminary Data
Min
Max
Figure
t44
A[31:5] Setup Time
6.0 ns
108
t45
A[31:5] Hold Time
1.0 ns
108
t461
A20M# Setup Time
5.0 ns
108
t471
A20M# Hold Time
1.0 ns
108
t48
AHOLD Setup Time
5.5 ns
108
t49
AHOLD Hold Time
1.0 ns
108
t50
AP Setup Time
5.0 ns
108
t51
AP Hold Time
1.0 ns
108
t52
BOFF# Setup Time
5.5 ns
108
t53
BOFF# Hold Time
1.0 ns
108
t54
BRDY# Setup Time
5.0 ns
108
t55
BRDY# Hold Time
1.0 ns
108
t56
BRDYC# Setup Time
5.0 ns
108
t57
BRDYC# Hold Time
1.0 ns
108
t58
D[63:0] Read Data Setup Time
2.8 ns
108
t59
D[63:0] Read Data Hold Time
1.5 ns
108
t60
DP[7:0] Read Data Setup Time
2.8 ns
108
t61
DP[7:0] Read Data Hold Time
1.5 ns
108
t62
EADS# Setup Time
5.0 ns
108
t63
EADS# Hold Time
1.0 ns
108
t64
EWBE# Setup Time
5.0 ns
108
t65
EWBE# Hold Time
1.0 ns
108
t662
FLUSH# Setup Time
5.0 ns
108
t672
FLUSH# Hold Time
1.0 ns
108
t68
HOLD Setup Time
5.0 ns
108
t69
HOLD Hold Time
1.5 ns
108
IGNNE# Setup Time
5.0 ns
108
t711
IGNNE# Hold Time
1.0 ns
108
t722
INIT Setup Time
5.0 ns
108
t70
304
Parameter Description
1
Signal Switching Characteristics
Chapter 16
Preliminary Information
23542A/0—September 2000
AMD-K6™-2E+ Embedded Processor Data Sheet
Table 67. Input Setup and Hold Timings for 66-MHz Bus Operation (continued)
Symbol
Parameter Description
Preliminary Data
Min
Max
Figure
t732
INIT Hold Time
1.0 ns
108
t741
INTR Setup Time
5.0 ns
108
t751
INTR Hold Time
1.0 ns
108
t76
INV Setup Time
5.0 ns
108
t77
INV Hold Time
1.0 ns
108
t78
KEN# Setup Time
5.0 ns
108
t79
KEN# Hold Time
1.0 ns
108
t80
NA# Setup Time
4.5 ns
108
t81
NA# Hold Time
1.0 ns
108
t822
NMI Setup Time
5.0 ns
108
t832
NMI Hold Time
1.0 ns
108
t842
SMI# Setup Time
5.0 ns
108
t852
SMI# Hold Time
1.0 ns
108
t861
STPCLK# Setup Time
5.0 ns
108
t871
STPCLK# Hold Time
1.0 ns
108
t88
WB/WT# Setup Time
4.5 ns
108
t89
WB/WT# Hold Time
1.0 ns
108
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold
times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold
times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain
asserted at least two clocks.
Chapter 16
Signal Switching Characteristics
305
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
16.9
23542A/0—September 2000
RESET and Test Signal Timing
Table 68. RESET and Configuration Signals for 100-MHz Bus Operation
Preliminary Data
Symbol Parameter Description
Min
Max
Figure
t90
RESET Setup Time
1.7 ns
109
t91
RESET Hold Time
1.0 ns
109
t92
RESET Pulse Width, VCC and CLK Stable
15 clocks
109
t93
RESET Active After VCC and CLK Stable
1.0 ms
109
t941
BF[2:0] Setup Time
1.0 ms
109
t951
BF[2:0] Hold Time
2 clocks
109
t96
Intentionally left blank
t97
Intentionally left blank
t98
Intentionally left blank
t992
FLUSH# Setup Time
1.7 ns
109
t1002
FLUSH# Hold Time
1.0 ns
109
t1013
FLUSH# Setup Time
2 clocks
109
t1023
FLUSH# Hold Time
2 clocks
109
Notes:
1. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
2. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET is
sampled negated.
3. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of RESET.
306
Signal Switching Characteristics
Chapter 16
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 69. RESET and Configuration Signals for 66-MHz Bus Operation
Preliminary Data
Symbol Parameter Description
Min
Max
Figure
t90
RESET Setup Time
5.0 ns
109
t91
RESET Hold Time
1.0 ns
109
t92
RESET Pulse Width, VCC and CLK Stable
15 clocks
109
t93
RESET Active After VCC and CLK Stable
1.0 ms
109
t941
BF[2:0] Setup Time
1.0 ms
109
t951
BF[2:0] Hold Time
2 clocks
109
t96
Intentionally left blank
t97
Intentionally left blank
t98
Intentionally left blank
t992
FLUSH# Setup Time
5.0 ns
109
t1002
FLUSH# Hold Time
1.0 ns
109
t1013
FLUSH# Setup Time
2 clocks
109
t1023
FLUSH# Hold Time
2 clocks
109
Notes:
1. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
2. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET is sampled negated.
3. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of RESET.
Chapter 16
Signal Switching Characteristics
307
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 70. TCK Waveform and TRST# Timing at 25 MHz
Symbol
Preliminary Data
Parameter Description
Min
Max
TCK Frequency
25 MHz
Figure
110
t103
TCK Period
40.0 ns
110
t104
TCK High Time
14.0 ns
110
t105
TCK Low Time
14.0 ns
110
t1061,2
TCK Fall Time
5.0 ns
110
t107
TCK Rise Time
5.0 ns
110
t1083
TRST# Pulse Width
30.0 ns
111
Notes:
1. Rise/Fall times can be increased by 1.0 ns for each 10 MHz that TCK is run below its maximum frequency of 25 MHz.
2. Rise/Fall times are measured between 0.8 V and 2.0 V.
3. Asynchronous.
Table 71. Test Signal Timing at 25 MHz
Symbol
Preliminary Data
Parameter Description
Min
Max
Figure
t1091
TDI Setup Time
5.0 ns
112
t1101
TDI Hold Time
9.0 ns
112
t1111
TMS Setup Time
5.0 ns
112
t1121
TMS Hold Time
9.0 ns
112
t1132
TDO Valid Delay
3.0 ns
t1142
TDO Float Delay
t1152
All Outputs (Non-Test) Valid Delay
t1162
All Outputs (Non-Test) Float Delay
t1171
All Inputs (Non-Test) Setup Time
5.0 ns
112
t1181
All Inputs (Non-Test) Hold Time
9.0 ns
112
3.0 ns
13.0 ns
112
16.0 ns
112
13.0 ns
112
16.0 ns
112
Notes:
1. Parameter is measured from the TCK rising edge.
2. Parameter is measured from the TCK falling edge.
308
Signal Switching Characteristics
Chapter 16
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
16.10
Timing Diagrams
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Steady
Can change from
High to Low
Changing from High to Low
Can change
from Low to High
Changing from Low to High
Don’t care, any
change permitted
Changing, State Unknown
(Does not apply)
Center line is high
impedance state
Figure 105. Key to Timing Diagrams
Chapter 16
Signal Switching Characteristics
309
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Tx
Tx
CLK
1.5 V
Max
tv
Output Signal
Min
Valid n
Valid n +1
Note: For symbols tv listed in Table 64 on page 298 and Table 66 on page 302, where:
v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42
Figure 106. Output Valid Delay Timing
CLK
1.5 V
Tx
Tx
Tx
Tx
tf
Output Signal
Valid
tv
Min
Note: For symbols tv and tf listed in Table 64 on page 298 and Table 66 on page 302, where:
v = 6, 8, 10, 12, 15, 18, 20, 22, 24, 30, 32, 34, 37, 39, 42
f = 7, 9, 11, 13, 16, 19, 21, 23, 25, 31, 33, 35, 38, 40, 43
Figure 107. Maximum Float Delay Timing
Tx
Tx
Tx
Tx
1.5 V
CLK
ts
th
Input Signal
Note: For symbols ts and th listed in Table 65 on page 300 and Table 67 on page 304, where:
s = 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88
h = 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89
Figure 108. Input Setup and Hold Timing
310
Signal Switching Characteristics
Chapter 16
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Tx
Tx
CLK
t90
RESET
1.5 V
•••
1.5 V
t91
•••
1.5 V
t92, 93
t99
FLUSH#
(Synchronous)
•••
FLUSH#
(Asynchronous)
•••
BF[2:0]
(Asynchronous)
t 101
t100
t 102
•••
t94
t95
Figure 109. Reset and Configuration Timing
Chapter 16
Signal Switching Characteristics
311
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
t104
2.0 V
1.5 V
t105
0.8 V
t106
t107
t103
Figure 110. TCK Waveform
t108
1.5 V
Figure 111. TRST# Timing
t103
TCK
1.5 V
t109, 111
t110, 112
TDI, TMS
t114
t113
TDO
Output
Signals
t116
t115
Input
Signals
t117
t118
Figure 112. Test Signal Timing Diagram
312
Signal Switching Characteristics
Chapter 16
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
17
17.1
Thermal Design
Package Thermal Specifications
The AMD-K6-2E+ processor operating specification calls for the
case temperature (T C ) to be in the range of 0°C to 70°C for
standard-power devices and 0°C to 85°C for low-power devices.
The ambient temperature (TA) is not specified as long as the
case temperature is not violated. The case temperature must be
measured on the top center of the package.
Table 72 on page 314 and Table 73 on page 314 show the processor thermal specifications for the low-power and standard
power AMD-K6-2E+ devices, respectively.
Chapter 17
Thermal Design
313
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 72. Package Thermal Specification for Low-Power AMD-K6™-2E+
Devices
Maximum Thermal Power
qJC
Junction-Case
350 MHz
400 MHz
450 MHz
1.0° C/W
7.50 W
9.50 W
12.00 W
2.50 W
Stop Grant Mode
1.60 W
Stop Clock Mode
1.90 W
0°C–85°C
TC Case Temperature
Table 73. Package Thermal Specification for Standard-Power AMD-K6™-2E+
Devices
Maximum Thermal Power
qJC
Junction-Case
400 MHz
450 MHz
500 MHz
1.0°C/W
16.50 W
17.50 W
18.50 W
Stop Grant Mode
4.50 W
Stop Clock Mode
4.00 W
TC Case Temperature
0°C–70°C
Figure 113 on page 315 shows the thermal model of a processor
w it h a p as sive t h e rm a l so lut i on. The c a se -t o -a m b ie n t
temperature (T CA ) can be calculated from the following
equation:
TCA
= PMAX • qCA
= PMAX • ( qIF + qSA)
Where:
PMAX
qCA
qIF
qSA
314
=
=
=
=
Maximum Power Consumption
Case-to-Ambient Thermal Resistance
Interface Material Thermal Resistance
Sink-to-Ambient Thermal Resistance
Thermal Design
Chapter 17
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Thermal
Resistance
(°C/W)
Temperature
(Ambient)
TCA
qSA
qCA
Sink
Case
qIF
Figure 113. Thermal Model (CPGA Package)
Figure 114 illustrates the case-to-ambient temperature (TCA) in
relation to the power consumption (X-axis) and the thermal
resistance (Y-axis). If the power consumption and case
te mpe rat ure are known, t he ther mal re sista nce ( q C A )
requirement can be calculated for a given ambient temperature
(TA) value.
TCA = TC - TA
Case-to-Ambient Temperature
(TC - TA)
CA
Thermal Resistance (°C/W)
q
GHJ&
GHJ&
GHJ&
GHJ&
:
:
:
:
:
:
:
:
:
:
Power Consumption (Watts)
Figure 114. Power Consumption and Thermal Resistance (CPGA Package)
Chapter 17
Thermal Design
315
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
The thermal resistance of a heatsink is determined by the heat
dissipation surface area, the material and shape of the
heatsink, and the airflow volume across the heatsink. In
general, the larger the surface area the lower the thermal
resistance.
The required thermal resistance of a heatsink ( q SA ) can be
calculated using the following example:
If:
TC = 70°C
TA = 45°C
PMAX = 19.50W
Then:
TC – T A
25•C - = 1.28•C ‰ W
q CA ˆ ËÍ --------------------ÛÝ = -----------------19.50W
P MAX
Thermal grease is recommended as interface material because
it provides the lowest thermal resistance (@ 0.20°C/W). The
required thermal resistance ( q SA ) of the heatsink in this
example is calculated as follows:
qSA = qCA – qIF = 1.28 – 0.20 = 1.08°C/W
Heat Dissipation Path
Figure 115 illustrates the heat dissipation path of the processor.
Due to the lower thermal resistance between the processor die
junction and case, most of the heat generated by the processor
is transferred from the top surface of the case. The small
amount of heat generated from the bottom side of the processor
where the processor socket blocks the convection can be safely
ignored.
Ambient Temperature
Thin Lid
Case temperature
Figure 115. Processor Heat Dissipation Path
316
Thermal Design
Chapter 17
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
17.2
Measuring Case Temperature
The processor case temperature is measured to ensure that the
t h e r m a l s o l u t i o n m e e t s t h e p ro c e s s o r ’s o p e ra t i o n a l
specification. This temperature should be measured on the top
center of the package, where most of the heat is dissipated.
Figure 116 shows the correct location for measuring the case
temperature. The tip of the thermocouple should be secured to
the package surface with a small amount of thermally
conductive epoxy. It is also recommended to secure a second
location along the thermocouple to avoid any movement during
testing.
If a heatsink is installed while measuring, the thermocouple
must be installed into the heatsink via a small hole drilled
through the heatsink base (for example, 1/16 of an inch). Secure
the thermocouple to the base of the heatsink by filling the
small hole with thermal epoxy, allowing the tip of the
thermocouple to protrude the epoxy and touch the top of the
processor case.
Thermally Conductive Epoxy
Thermocouple
Figure 116. Measuring Case Temperature
17.3
Layout and Airflow Considerations
Voltage Regulator
Chapter 17
A voltage regulator is required to support the lower voltage
(3.3 V and lower) to the processor. In most applications, the
voltage regulator is designed with power transistors. As a
result, additional heatsinks are required to dissipate the heat
from the power transistors. Figure 117 on page 318 shows the
Thermal Design
317
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
voltage regulator placed parallel to the processor with the
airflow aligned with the devices. With this alignment, the heat
generated by the voltage regulator has minimal effect on the
processor.
Voltage Regulator
Processor
Airflow
Figure 117. Voltage Regulator Placement
A heatsink and fan combination can deliver much better
thermal performance than a heatsink alone. More importantly,
with a fan/sink the airflow requirements in a system design are
not as critical. A unidirectional heatsink with a fan moves air
from the top of the heatsink to the side. In this case, the best
location for the voltage regulator is on the side of the processor
in the path of the airflow exiting the fan sink (see Figure 118 on
page 319). This location guarantees that the heatsinks on both
t he pro cess or a nd t he re gula to r rece ive ade quat e ai r
circulation.
318
Thermal Design
Chapter 17
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Airflow
Ideal areas for voltage regulator
Figure 118. Airflow for a Heatsink with Fan
Airflow Management
in a System Design
Complete airflow management in a system is important. In
addition to the volume of air, the path of the air is also
important. Figure 119 shows the airflow in a dual-fan system.
The fan in the front end pulls cool air into the system through
intake slots in the chassis. The power supply fan forces the hot
air out of the chassis. The thermal performance of the heatsink
can be maximized if it is located in the shaded area, where it
receives greatest benefit from this air exchange system.
Fan
P/S
Main Board
V
e
n
t
s
Drive Bays
Fan
Vents
Front
Figure 119. Airflow Path in a Dual-Fan System
Chapter 17
Thermal Design
319
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Figure 120 shows the airflow management in a system using the
ATX form-factor. The orientation of the power supply fan and
the motherboard are modified in the ATX platform design. The
power supply fan pulls cool air through the chassis and across
the processor. The processor is located near the power supply
fan, where it can receive adequate airflow without an auxiliary
fan. The arrangement significantly improves the airflow across
the processor with minimum installation cost.
Main Board
F
a
n
P/S
Drive Bays
Figure 120. Airflow Path in an ATX Form-Factor System
For more information about thermal design considerations, see
the AMD-K6 ® Processor Thermal Solution Design Application
Note, order# 21085.
320
Thermal Design
Chapter 17
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
18
Pin Designations
This chapter includes pin connection diagrams and pin
designation tables for each of two packages, the Ceramic Pin
Grid Array (CPGA) and the Organic Ball Grid Array (OBGA).
Th e p i n d e s i g n a t i o n d i a g ra m s i n c l u d e t h e fo l l ow i n g
annotations:
Control/Parity Pins
Address Pins
VSS Pins
T
Test Pins
VCC2 Pins
NC, INC (Internal No Connect) Pins
VCC3 Pins
RSVD (Reserved) Pins
Data Pins
Note that the OBGA package includes additional pins not
supported on the CPGA package. Table 74 shows the pin
differences between the two packages.
Table 74. Pin Differences Between the CPGA and OBGA Packages
Pin
CPGA Package
OGBA Package
VCC2DET
Supported
Not supported
VCC2H/L#
Supported
Not supported
VID[4:0]
Supported on lowpower versions only
Supported on lowpower versions only
VCC2
28
37
VCC3
32
26
VSS
68
99
No Connects
131
82
131
82
Internal
No Connects
7
1
Reserved
14
16
Comment
These pins are no-connects
(NC) on standard-power
versions for both packages.
Notes:
1.
2.
Chapter 18
Standard-power versions only, since the VID[4:0] outputs are not supported.
Low-power versions only.
Pin Designations
321
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
18.1
23542A/0—September 2000
Pins Designations for CPGA Package
Data Pins
B
D
A
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
F
C
E
D11
DP0
D15
D6
D13
D5
D14
D18
D16
D22
D7
Top
View
A20
Vcc3
Vss
Vss
BE6#
Vss
Vss
Vcc2
D42
Vss
BE1#
Vss
BE0#
Vcc2
A20M#
Vss
DP5
D49
D56
D55
D52
D57
Vcc2
F
E
Vss
Vss
K
J
RSVD
Vss
Vcc2
M
L
RSVD
RSVD
D63
Vcc2
Vcc2
R
Q
INV
M/IO#
KEN#
WB/WT# RSVD
NA#
AHOLD# BRDY#
BOFF# HOLD
APCHK#
RSVD
PCD
ADS#
W/R#
HITM# VCC2H/L#
PCHK# LOCK# D/C#
EADS#
RSVD CACHE# EWBE# BRDYC# RSVD
RSVD RSVD SMIACT# HLDA PWT
INC
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
ADSC#
AP
Vcc2
P
N
RSVD
FERR#
DP7
D62
D61
Vcc2
H
G
D60
D59
Vss
DP6
D54
D
D58
D53
Vcc2
FLUSH#
INC
HIT#
D
D51
D50
BE2#
Vss
D46
D47
Vcc2
BE4#
Vss
D48
C
Vcc2
Vss
BE3#
D44
D45
Vcc2
Vss
BE5#
DP4
B
Vss
SCYC
NC
Vcc2
NC
Vcc2
NC
CLK
D40
Vcc2
Vcc3
Vss
RESET
BE7#
D38
D43
Vcc3
Vss
Vss
D39
Vss
A
A18
D37
Vss
Vcc3
Vss
A19
VID4
D36
Vss
A16
NC
D35
Vss
Vcc3
Vss
A17
Vcc3
D34
Vss
A14
D33
Vss
Vcc3
A12
Vss
Vss
D32
Vss
Vss
VID3
D31
Vss
A10
A11
Vcc3
D30
Vss
A6
A8
A9
Vss
D29
Vcc3
Vss
DP3
D41
A7
A5
A15
D27
Vcc2
A31
Vss
D28
Vss
A4
A29
A27
Vcc3
D25
Vcc2
A23
NMI
VID1
A3
A26
D26
Vss
Vcc2
A21
A30
A25
A24
RSVD
INTR
Vss
A28
A13
DP2
Vcc2
INIT
BF0
A22
D23
Vss
Vcc2
INC
SMI#
Vss
Vss
Vcc3
Vss
Vss
D24
Vcc2
NC
Vss
IGNNE#
INC
Vcc3
Vcc3
Vss
D19
Vss
Vcc3
INC
BF2
STPCLK# BF1
Vcc3
NC
Vcc3
Vss
Vss
D21
Vcc3
TRST#
TDO
Vcc3
AB AD AF AH AK AM
AA AC AE AG AJ AL AN
Vcc3
Vss
Vss
Vss
NC
VID2
Z
Y
Vcc3
Vcc3
Vss
RSVD
X
W
DP1
Vss
Vcc3
Vcc3
Vcc3
Vss
TMS
TCK
RSVD
D3
Vss
TDI
V
U
VID0
D17
Vcc3
RSVD
T
S
Vcc3
Vcc3
Vss
D0
R
Q
D12
D20
Vcc3
Vcc3
D2
INC
P
N
Vss
D1
D8
M
L
Vcc3
Vss
D4
D10
K
J
Vcc3
Vcc3
D9
NC
H
G
Vcc2
T
S
Vcc2
V
U
Vcc2
X
W
Vcc2
Z
Y
Vcc2
Vcc2
Vcc2
BREQ VCC2DET
INC
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AB AD AF AH AK AM
AA AC AE AG AJ AL AN
Notes:
The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.
Figure 121. CPGA Connection Diagram (Top-Side View)
322
Pin Designations
Chapter 18
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
VID1 Vss
A6
INC VCC2H/L# FLUSH# Vcc2
Vcc2
Vcc2 Vcc2
Vcc2
Vcc2
Vcc3 Vcc3
Vcc3
Vcc3 A10
Vcc3
A8
A30
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A4
BE0# BE2# BE4# BE6# SCYC
VCC2DET PWT
Vss
NC
HITM# INC
A20
A12
A16
A14
A11
A3
A7
A18
AP
D/C# HIT# A20M# BE1# BE3# BE5#
RESET A19
A17
A15
BE7# CLK
A29
A28
A9
A5
A13
INC
ADSC# EADS# W/R#
BREQ
HLDA
Vss
ADS#
Vss
Vss
Vcc2
Vss
Vss
NC
Vcc3
Vss
Vss
NC
Vss
Vcc3
Vss
LOCK#
A31
Vcc2 SMIACT# PCD
Vss PCHK#
Vcc2
Vss
Vcc2
A24
Vcc3
Vss
A21
A23 RSVD Vcc3
Vss
INTR
RSVD
INC Vcc3
Vss
SMI#
INIT IGNNE# Vcc3
NMI
RSVD
Vss
HOLD
RSVD WB/WT#
Vss
BOFF#
Vcc2 BRDYC# NA#
Vss
BRDY#
Vcc2
Vcc2
Vcc2
Vcc2
D59
D58
D57
Vss
D55
D52
D48
NC
Vcc2
Vss
INC
D53
D51
D3
D44
D1
D5
DP5
D49
D46
D42
D40
Vss
Vss
D39
D37
Vcc2
D35
D33
VID4
DP3
Vss
Vss
Vcc3
D30
D28
VID3
D26
D23
Vss
Vcc3
D19
Vss
DP1
Vcc3
D4
D6
D7
D12
Vcc3
D2
RSVD
D56
DP6
D54
RSVD Vcc3
Vss
TMS
TDI
Vcc3
TDO
Vss
TCK
Vcc3
RSVD Vcc3
Vss
D0
D60
D61
Vcc2
TRST#
D62
Vss
Vcc2
BF2 Vcc3
STPCLK# Vss
Vss
Vcc3
Vcc3
Vss
Vcc3
Vcc3
NC
NC
VID2 Vss
DP7
D63
Vcc3
Vss
NC
Bottom
View
RSVD FERR#
RSVD
Vss
INC
BF1
Vcc2 CACHE# INV
Vss
M/IO#
Vcc2
RSVD RSVD
Vss
RSVD
Vss
Vss
INC
BF0
EWBE# KEN#
Vss
AHOLD
Vcc2
A22
A27
RSVD APCHK#
RSVD
Vss
A25
A26
VID0
D8
Vcc3
DP0
D47
D45
DP4
D38
D36
D34
D32
D31 D29
D27
D25
DP2
D24
D21
D17
D14
D10
D9
D43
D11
D20
D16
D13
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
D41 Vcc2
D15
D22
D18
NC
Vss
Vcc2
Vcc2
Vcc2
Vcc2
Vcc2
Vcc3
Vcc3 Vcc3
Vcc3
Vcc3
Vcc3
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Notes:
The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.
Figure 122. CPGA Connection Diagram (Bottom-Side View)
Chapter 18
Pin Designations
323
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 75. CPGA Pin Designations by Functional Grouping
Pin Name
Pin Number
Control
A20M#
ADS#
ADSC#
AHOLD
APCHK#
BE0#
BE1#
BE2#
BE3#
BE4#
BE5#
BE6#
BE7#
BF0
BF1
BF2
BOFF#
BRDY#
BRDYC#
BREQ
CACHE#
CLK
D/C#
EADS#
EWBE#
FERR#
FLUSH#
HIT#
HITM#
HLDA
HOLD
IGNNE#
INIT
INTR
INV
KEN#
LOCK#
M/IO#
NA#
NMI
PCD
PCHK#
PWT
RESET
SCYC
SMI#
SMIACT#
STPCLK#
VCC2DET
VCC2H/L#
W/R#
WB/WT#
AK-08
AJ-05
AM-02
V-04
AE-05
AL-09
AK-10
AL-11
AK-12
AL-13
AK-14
AL-15
AK-16
Y-33
X-34
W-35
Z-04
X-04
Y-03
AJ-01
U-03
AK-18
AK-04
AM-04
W-03
Q-05
AN-07
AK-06
AL-05
AJ-03
AB-04
AA-35
AA-33
AD-34
U-05
W-05
AH-04
T-04
Y-05
AC-33
AG-05
AF-04
AL-03
AK-20
AL-17
AB-34
AG-03
V-34
AL-01
AN-05
AM-06
AA-05
Pin Name
Pin Number
Address
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
AL-35
AM-34
AK-32
AN-33
AL-33
AM-32
AK-30
AN-31
AL-31
AL-29
AK-28
AL-27
AK-26
AL-25
AK-24
AL-23
AK-22
AL-21
AF-34
AH-36
AE-33
AG-35
AJ-35
AH-34
AG-33
AK-36
AK-34
AM-36
AJ-33
Pin Name
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
Pin Number
Data
K-34
G-35
J-35
G-33
F-36
F-34
E-35
E-33
D-34
C-37
C-35
B-36
D-32
B-34
C-33
A-35
B-32
C-31
A-33
D-28
B-30
C-29
A-31
D-26
C-27
C-23
D-24
C-21
D-22
C-19
D-20
C-17
C-15
D-16
C-13
D-14
C-11
D-12
C-09
D-10
D-08
A-05
E-09
B-04
D-06
C-05
E-07
C-03
D-04
E-05
D-02
F-04
Pin Name
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
Pin Number
Data
E-03
G-05
E-01
G-03
H-04
J-03
J-05
K-04
L-05
L-03
M-04
N-03
Test
TCK
TDI
TDO
TMS
TRST#
M-34
N-35
N-33
P-34
Q-33
Parity
AP
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
AK-02
D-36
D-30
C-25
D-18
C-07
F-06
F-02
N-05
Voltage ID1
VID4
VID3
VID2
VID1
VID0
E-17
E-25
R-34
AN-35
AH-32
Notes: 1. The VID[4:0] pins are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.
324
Pin Designations
Chapter 18
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 76. CPGA Pin Designations for No Connect, Reserved, Power, and Ground Pins
No Connect (NC)
VCC2
A-37
C-01
E-171
E-251
R-341
S-33
S-35
W-33
AH-321
AJ-15
AJ-23
AL-19
AN-351
A-07
A-09
A-11
A-13
A-15
A-17
B-02
E-15
G-01
J-01
L-01
N-01
Q-01
S-01
U-01
W-01
Y-01
AA-01
AC-01
AE-01
AG-01
AJ-11
AN-09
AN-11
AN-13
AN-15
AN-17
AN-19
Internal No Connect (INC)
H-34
Y-35
Z-34
AC-35
AL-07
AN-01
AN-03
Reserved (RSVD)
J-33
L-35
P-04
Q-03
Q-35
R-04
S-03
S-05
AA-03
AC-03
AC-05
AD-04
AE-03
AE-35
Pin Numbers
VCC3
A-19
A-21
A-23
A-25
A-27
A-29
E-21
E-27
E-37
G-37
J-37
L-33
L-37
N-37
Q-37
S-37
T-34
U-33
U-37
W-37
Y-37
AA-37
AC-37
AE-37
AG-37
AJ-19
AJ-29
AN-21
AN-23
AN-25
AN-27
AN-29
VSS
VSS
A-03
B-06
B-08
B-10
B-12
B-14
B-16
B-18
B-20
B-22
B-24
B-26
B-28
E-11
E-13
E-19
E-23
E-29
E-31
H-02
H-36
K-02
K-36
M-02
M-36
P-02
P-36
R-02
R-36
T-02
T-36
U-35
V-02
V-36
X-02
X-36
Z-02
Z-36
AB-02
AB-36
AD-02
AD-36
AF-02
AF-36
AH-02
AJ-07
AJ-09
AJ-13
AJ-17
AJ-21
AJ-25
AJ-27
AJ-31
AJ-37
AL-37
AM-08
AM-10
AM-12
AM-14
AM-16
AM-18
AM-20
AM-22
AM-24
AM-26
AM-28
AM-30
AN-37
Notes: 1. These pins are no-connects on standard-power versions only. They are defined as VID[4:0] on low-power versions. See page 324.
Chapter 18
Pin Designations
325
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
18.2
23542A/0—September 2000
Pins Designations for OBGA Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
D52
DP5
D47
D45
D40
D39
D37
D33
VID4
D29
D28
D26
D23
D20
D16
D51
VSS
NC
VSS
D44
VSS
D41
VSS
D32
VSS
D30
VCC3
DP2
VSS
D19
VCC3
D17
A
B
18
19
A
B
C
DP6
VCC2
D54
D50
D49
D46
D43
DP4
D38
D35
DP3
D27
D25
D24
VID3
D22
DP1
VSS
D18
C
D
D59
D56
D58
VCC2
D53
D48
D42
VSS
D36
D34
D31
VSS
D21
D13
D15
VSS
D14
D12
D10
D
E
D60
VSS
D55
D57
VCC2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D7
D8
VCC3
D9
E
F
DP7
D62
D61
D63
VSS
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VSS
VSS
VCC3
VSS
D11
D3
D5
D6
F
G
RSVD
VCC2
RSVD
FERR#
VCC2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC3
RSVD
DP0
VSS
D1
G
H
RSVD
RSVD
RSVD
VCC2
VSS
VCC2
VCC2
VSS
VSS
VCC3
VCC3
VCC3
VCC3
VCC3
VSS
VCC3
D4
D0
D2
H
T
J
INV
VSS
M/IO#
CACHE#
VCC2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC3
TDO
T
RSVD
VCC3
TCK
T
T
T
J
K
BRDY#
KEN#
EWBE#
AHOLD
VSS
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VSS
VSS
VCC3
VSS
RSVD
TRST#
TMS
TDI
K
L
BRDYC#
VCC2
BOFF#
NA#
VCC2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC3
VSS
NC
VSS
VID2
L
M
RSVD
WB/WT#
HOLD
VCC2
VSS
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VSS
VSS
VCC3
VSS
NC
BF1
STPCLK#
NC
M
N
RSVD
VSS
RSVD
RSVD
VCC2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC3
INC
BF0
VCC3
BF2
N
P
RSVD
BREQ
VSS
VCC2
VSS
RSVD
VSS
VSS
VCC3
VCC3
VSS
VCC3
VSS
INTR
INIT
SMI#
IGNNE#
P
R
APCHK#
VCC2
AP
PCD
VCC2
VSS
VSS
RSVD
VSS
VCC3
VSS
VSS
VCC3
VSS
VSS
A28
NMI
VSS
RSVD
R
T
LOCK#
HLDA
ADSC#
VCC2
NC
VSS
FLUSH#
BE5#
NC
A20
A16
A8
A4
A3
A27
VSS
A21
A24
A22
T
U
ADS#
VSS
D/C#
HITM#
W/R#
BE0#
BE4#
BE6#
CLK
A19
NC
A15
A13
A7
A31
A29
A26
VCC3
A23
U
PWT
VCC2
EADS#
VSS
BE2#
VCC2
BE7#
VSS
A18
VCC3
A10
VSS
A6
VCC3
A30
VSS
A25
HIT#
A20M#
BE1#
BE3#
NC
SCYC
RESET
A17
A14
A12
A11
A9
A5
VID1
VID0
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
V
SMIACT# PCHK#
W
1
2
V
W
18
19
Notes:
There are three pads missing on each corner of the OBGA package due to manufacturing requirements.
The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.
Figure 123. OBGA Connection Diagram (Top-Side View)
326
Pin Designations
Chapter 18
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
A
B
C
D
E
F
G
H
J
K
L
M
N
P
DP6
D59
D60
DP7
RSVD
RSVD
INV
BRDY#
BRDYC#
RSVD
RSVD
RSVD
D51
VCC2
D56
VSS
D62
VCC2
RSVD
VSS
KEN#
VCC2
WB/WT#
VSS
SMIACT#
VCC2
HLDA
VSS
PWT
M/IO#
EWBE#
BOFF#
HOLD
RSVD
PCHK#
AP
ADSC#
D/C#
VCC2
HIT#
3
NA#
VCC2
RSVD
BREQ
PCD
VCC2
HITM#
EADS#
A20M#
4
1
2
R
T
APCHK# LOCK#
U
V
W
1
ADS#
2
3
D52
VSS
D54
D58
D55
D61
RSVD
RSVD
4
DP5
NC
D50
VCC2
D57
D63
FERR#
VCC2
5
D47
VSS
D49
D53
VCC2
VSS
VCC2
VSS
VCC2
VSS
VCC2
VSS
VCC2
VSS
VCC2
NC
W/R#
VSS
BE1#
5
6
D45
D44
D46
D48
VSS
VCC2
VSS
VCC2
VSS
VCC2
VSS
VCC2
VSS
VCC2
VSS
VSS
BE0#
BE2#
BE3#
6
7
D40
VSS
D43
D42
VSS
VCC2
VSS
VCC2
VSS
VCC2
VSS
VCC2
VSS
VSS
VSS
FLUSH#
BE4#
VCC2
NC
7
8
D39
D41
DP4
VSS
VSS
VCC2
VSS
VSS
VSS
VCC2
VSS
VCC2
VSS
RSVD
RSVD
BE5#
BE6#
BE7#
SCYC
8
9
D37
VSS
D38
D36
VSS
VCC2
VSS
VSS
VSS
VCC2
VSS
VCC2
VSS
VSS
VSS
NC
CLK
VSS
RESET
9
10
D33
D32
D35
D34
VSS
VCC2
VSS
VCC3
VSS
VCC2
VSS
VCC2
VSS
VSS
VCC3
A20
A19
A18
A17
10
11
VID4
VSS
DP3
D31
VSS
VCC2
VSS
VCC3
VSS
VCC2
VSS
VCC2
VSS
VCC3
VSS
A16
NC
VCC3
A14
11
12
D29
D30
D27
VSS
VSS
VSS
VSS
VCC3
VSS
VSS
VSS
VSS
VSS
VCC3
VSS
A8
A15
A10
A12
12
13
D28
VCC3
D25
D21
VSS
VSS
VSS
VCC3
VSS
VSS
VSS
VSS
VSS
VSS
VCC3
A4
A13
VSS
A11
13
14
D26
DP2
D24
D13
VSS
VCC3
VSS
VCC3
VSS
VCC3
VSS
VCC3
VSS
VCC3
VSS
A3
A7
A6
A9
14
15
D23
VSS
VID3
D15
VSS
VSS
VCC3
VSS
VCC3
VSS
VCC3
VSS
VCC3
VSS
VSS
A27
A31
VCC3
A5
15
16
D20
D19
D22
VSS
D7
D11
RSVD
VCC3
TDO
RSVD
VSS
NC
INC
INTR
A28
VSS
A29
A30
VID1
16
17
D16
VCC3
DP1
D14
D8
D3
DP0
D4
RSVD
TRST#
NC
BF1
BF0
INIT
NMI
A21
A26
VSS
VID0
17
D17
VSS
D12
VCC3
D5
VSS
D0
VCC3
TMS
VSS
STPCLK#
VCC3
SMI#
VSS
A24
VCC3
A25
T
T
D18
D10
D9
D6
D1
D2
TCK
TDI
VID2
NC
BF2
IGNNE#
RSVD
A22
A23
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
CACHE# AHOLD
T
T
T
18
19
A
B
18
19
V
W
Notes:
There are three pads missing on each corner of the OBGA package due to manufacturing requirements.
The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.
Figure 124. OBGA Connection Diagram (Bottom-Side View)
Chapter 18
Pin Designations
327
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 77. OBGA Pin Designations by Functional Grouping
Pin Name
Pin Number
Control
A20M#
ADS#
ADSC#
AHOLD
APCHK#
BE0#
BE1#
BE2#
BE3#
BE4#
BE5#
BE6#
BE7#
BF0
BF1
BF2
BOFF#
BRDY#
BRDYC#
BREQ
CACHE#
CLK
D/C#
EADS#
EWBE#
FERR#
FLUSH#
HIT#
HITM#
HLDA
HOLD
IGNNE#
INIT
INTR
INV
KEN#
LOCK#
M/IO#
NA#
NMI
PCD
PCHK#
PWT
RESET
SCYC
SMI#
SMIACT#
STPCLK#
W/R#
WB/WT#
W4
U1
T3
K4
R1
U6
W5
V6
W6
U7
T8
U8
V8
N17
M17
N19
L3
K1
L1
P4
J4
U9
U3
V4
K3
G4
T7
W3
U4
T2
M3
P19
P17
P16
J1
K2
T1
J3
L4
R17
R4
P3
V2
W9
W8
P18
P2
M18
U5
M2
Pin Name
Pin Number
Address
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
T14
T13
W15
V14
U14
T12
W14
V12
W13
W12
U13
W11
U12
T11
W10
V10
U10
T10
T17
T19
U19
T18
V18
U17
T15
R16
U16
V16
U15
Pin Name
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
Pin Number
Data
H18
G19
H19
F17
H17
F18
F19
E16
E17
E19
D19
F16
D18
D14
D17
D15
A17
B18
C19
B16
A16
D13
C16
A15
C14
C13
A14
C12
A13
A12
B12
D11
B10
A10
D10
C10
D9
A9
C9
A8
A7
B8
D7
C7
B6
A6
C6
A5
D6
C5
C4
B2
Pin Name
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
Pin Number
Data
A3
D5
C3
E3
D2
E4
D3
D1
E1
F3
F2
F4
Test
TCK
TDI
TDO
TMS
TRST#
J19
K19
J16
K18
K17
Parity
AP
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
R3
G17
C17
B14
C11
C8
A4
C1
F1
Voltage ID1
VID0
VID1
VID2
VID3
VID4
W17
W16
L19
C15
A11
Notes: 1. The VID[4:0] pins are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.
328
Pin Designations
Chapter 18
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 78. OBGA Pin Designations for No Connect, Reserved, Power, and Ground Pins
No Connect (NC)
VCC2
A111
B4
C151
L17
L191
M16
M19
T5
T9
U11
W7
W161
W171
C2
D4
E5
F6
F7
F8
F9
F10
F11
G2
G5
H4
H6
H7
J5
K6
K7
K8
K9
K10
K11
L2
L5
M4
M6
M7
M8
M9
M10
M11
N5
P6
R2
R5
T4
V3
V7
Internal No Connect (INC)
N16
Reserved (RSVD)
G1
G3
G16
H1
H2
H3
J17
K16
M1
N1
N3
N4
P1
P8
R8
R19
Pin Numbers
VCC3
B13
B17
E18
F14
G15
H10
H11
H12
H13
H14
H16
J15
J18
K14
L15
M14
N15
N18
P11
P12
P14
R10
R13
U18
V11
V15
VSS
VSS
B3
B5
B7
B9
B11
B15
C18
D8
D12
D16
E2
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
F5
F12
F13
F15
G6
G7
G8
G9
G10
G11
G12
G13
G14
G18
H5
H8
H9
H15
J2
J6
J7
J8
J9
J10
J11
J12
J13
J14
K5
K12
K13
K15
L6
L7
L8
L9
L10
L11
L12
L13
L14
L16
L18
M5
M12
M13
M15
N2
N6
N7
N8
N9
N10
N11
N12
N13
N14
P5
P7
P9
P10
P13
P15
R6
R7
R9
R11
R12
R14
R15
R18
T6
T16
U2
V5
V9
V13
V17
Notes: 1. These pins are no-connects on standard-power versions only. They are defined as VID[4:0] on low-power versions. See page 328.
Chapter 18
Pin Designations
329
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
330
Pin Designations
23542A/0—September 2000
Chapter 18
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
19
19.1
Package Specifications
321-Pin Staggered CPGA Package Specification
Figure 125. 321-Pin Staggered CPGA Package Specification
Chapter 19
Package Specifications
331
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
19.2
23542A/0—September 2000
349-Ball OBGA Package Specification
Dwg rev. AA.04; 08/00
Figure 126. 349-Ball OBGA Package Specification
332
Package Specifications
Chapter 19
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
20
Ordering Information
Standard AMD-K6-2E+ Embedded Processor Products
AMD standard products are available in several operating ranges. The ordering part
number (OPN) is formed by a combination of the elements below. See Table 79 on
page 334 for valid ordering part number combinations.
AMD-K6-2E+ /500
A C R
Case Temperature
R = 0°C–70°C
Z = 0°C–85°C
Operating Voltage
U
T
P
C
=
=
=
=
1.4 V–1.6 V (Core)/ 3.135 V–3.6 V (I/O)
1.5 V–1.7 V (Core)/ 3.135 V–3.6 V (I/O)
1.6 V–1.8 V (Core)/ 3.135 V–3.6 V (I/O)
1.9 V–2.1 V (Core)/ 3.135 V–3.6 V (I/O)
Package Type
A = 321-pin CPGA
I = 349-ball OBGA
Performance Rating
/500
/450
/400
/350
Family/Core
AMD-K6-2E+
Chapter 20
Ordering Information
333
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Table 79. AMD-K6™-2E+ Embedded Processor Valid Ordering Part Number Combinations
Device
Type
Low
Power
Standard
Power
OPN1
Package Type
Operating Voltage
Case
Temperature
Maximum CPU/Bus
Frequency
AMD-K6-2E+/350AUZ
321-pin CPGA
1.4 V–1.6 V (Core)
3.135 V–3.6 V (I/O)
0°C–85°C
350 MHz/100 MHz
AMD-K6-2E+/400ATZ
321-pin CPGA
1.5 V–1.7 V (Core)
3.135 V–3.6 V (I/O)
0°C–85°C
400 MHz/100 MHz
AMD-K6-2E+/450APZ
321-pin CPGA
1.6 V–1.8 V (Core)
3.135 V–3.6 V (I/O)
0°C–85°C
450 MHz/100 MHz
AMD-K6-2E+/350IUZ
349-ball OBGA
1.4 V–1.6 V (Core)
3.135 V–3.6 V (I/O)
0°C–85°C
350 MHz/100 MHz
AMD-K6-2E+/400ITZ
349-ball OBGA
1.5 V–1.7 V (Core)
3.135 V–3.6 V (I/O)
0°C–85°C
400 MHz/100 MHz
AMD-K6-2E+/400ACR
321-pin CPGA
1.9 V–2.1 V (Core)
3.135 V–3.6 V (I/O)
0°C–70°C
400 MHz/100 MHz
AMD-K6-2E+/450ACR
321-pin CPGA
1.9 V–2.1 V (Core)
3.135 V–3.6 V (I/O)
0°C–70°C
450 MHz/100 MHz
AMD-K6-2E+/500ACR
321-pin CPGA
1.9 V–2.1V (Core)
3.135 V–3.6 V (I/O)
0°C–70°C
500 MHz/100 MHz
AMD-K6-2E+/400ICR
349-ball OBGA
1.9 V–2.1 V (Core)
3.135 V–3.6 V (I/O)
0°C–70°C
400 MHz/100 MHz
AMD-K6-2E+/450ICR
349-ball OBGA
1.9 V–2.1 V (Core)
3.135 V–3.6 V (I/O)
0°C–70°C
450 MHz/100 MHz
Notes:
1. This table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly-released combinations.
334
Ordering Information
Chapter 20
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Index
Numerics
0.18-Micron Process Technology . . . . . . . . . . . . . . . . . . . . . . . 7
100-MHz Bus
clock switching characteristics . . . . . . . . . . . . . . . . . . . . 296
frontside. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 8
input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 300
output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Super7 platform support . . . . . . . . . . . . . . . . . . . . . . . . . 1, 8
321-Pin Staggered CPGA Package . . . . . . . . . . . . . . . . . . . . . 2
specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
349-Ball OBGA Package
specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
3DNow!™ Technology. . . . . . . 2, 5, 7, 15, 17, 19, 21–24, 127
data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
INIT state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
instruction compatibility, floating-point and . . . . . . . . . 240
instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89–90, 240
PREFETCH instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 220
register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
RESET state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
software prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
66-MHz Bus
clock switching characteristics . . . . . . . . . . . . . . . . . . . . 297
input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 304
output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
A
A[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
A20M# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94, 242
masking cache accesses with . . . . . . . . . . . . . . . . . . . . . . 227
Absolute Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Accelerated Graphic Port (AGP) . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledge, Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Address
bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100, 109
A[31:3] signals] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
address hold signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
address strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
AHOLD restriction . . . . . . . . . . . . . . . . . . . 174, 178, 180
coherencey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98–99
generation sequence during bursts (table) . . . . . . . . . . 162
hold signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
parity check signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
parity signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ADS# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ADSC# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
AGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AHOLD
-initiated inquire hit to modified line. . . . . . . . . . . . . . . 178
-initiated inquire hit to shared or exclusive line . . . . . . 176
-initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
AHOLD Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 278
Index
Airflow
consideration in layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
heatsink with fan (figure). . . . . . . . . . . . . . . . . . . . . . . . . 319
management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
path in a dual-fan system (figure) . . . . . . . . . . . . . . . . . . 319
path in an ATX form-factor system (figure) . . . . . . . . . . 320
Aligned Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Allocate, Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
AMD PowerNow!™ Technology . . . . . . . . . . . 6, 143, 151, 275
disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
dynamic core voltage control . . . . . . . . . . . . . . . . . . . . . . 151
enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
enhanced power management register (EPMR) . . . . . . 144
EPM 16-byte I/O block . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
EPM stop grant state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
I/O base address definition. . . . . . . . . . . . . . . . . . . . . . . . 145
processor state observability register (PSOR) . . . . . . . . 148
SMM handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
voltage identification signals . . . . . . . . . . . . . . . . . 137, 151
AP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
APCHK# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Asserted signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
B
Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
BDC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
BE[7:0]# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 199, 283
BIOS, enhanced power management. . . . . . . . . . . . . . . . . . 145
BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BOFF# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102, 182
locked operation with . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Boundary-Scan
bit definitions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
test access port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
BR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Branch
execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
history table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 7, 15, 23, 26
target cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
BRDY# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
BRDYC# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
BREQ Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
BSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Burst
pipelined burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ready copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104, 200
writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
writeback due to cache-line replacement . . . . . . . .164–165
Bus
100-MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 8
address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
A[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
AHOLD restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
335
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
external address strobe signal. . . . . . . . . . . . . . . . . . . 109
hold signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
inquire cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100, 174
parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98–99
strobe copy signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
arbitration cycles, inquire and . . . . . . . . . . . . . . . . . . . . 168
backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
byte enable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153–197
aligned transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
definitions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
order during misaligned I/O transfers (table) . . . . . . 167
order during misaligned memory transfers (table). . 160
special . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142, 190
data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 103, 174
AHOLD restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
aligned transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
byte enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
D[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
memory reads and writes. . . . . . . . . . . . . . . . . . . . . . . 158
misaligned transfers . . . . . . . . . . . . . . . . . . . . . . . 129, 184
parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 125
state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
frequency signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
hold request signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
lock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
request signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
states
address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
data-NA# requested . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
pipeline address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
pipeline data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
state machine (figure) . . . . . . . . . . . . . . . . . . . . . . . . . 155
transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
BVC Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
definition (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
BVCM Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Bypass Register (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
C
Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
branch target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
burst writeback cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
cacheable access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
disabling . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 211, 251, 263
enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112, 191
inhibiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251, 263
inquire cycles . . . . . . . . . . . . . . . . . . . . . . . . . 168, 174, 178
inquire cycles (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
336
23542A/0—September 2000
instruction cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
instruction fetch and decode . . . . . . . . . . . . . . . . . . . . . . . 17
instruction prefetch. . . . . . . . . . . . . . . . . . . . . . . 16–17, 220
L1 cache
cache-line replacement. . . . . . . . . . . . . . . . . . . . . . . . . 214
coherency states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
data cache line (figure). . . . . . . . . . . . . . . . . . . . . . . . . 207
instruction cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
instruction cache line (figure) . . . . . . . . . . . . . . . . . . . 207
internal snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
L2 cache
cache line (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
cache-line replacement. . . . . . . . . . . . . . . . . . . . . . . . . 214
data reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
direct access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
disabling for debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
EDX register content . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Level-2 Cache Array Access Register (L2AAR). . . . . . 50
organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
RDMSR instruction effect . . . . . . . . . . . . . . . . . . . . . . 265
sector and line organization (figure). . . . . . . . . . . . . . 265
tag array testing . . . . . . . . . . . . . . . . . . . . . . . . . 213, 264
tag information (figure) . . . . . . . . . . . . . . . . . . . . . . . . . 52
tag or data location (figure) . . . . . . . . . . . . . . . . . . . . . . 51
testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
WRMSR instruction effect . . . . . . . . . . . . . . . . . . . . . . 265
L3 cache
debugging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
PCD signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Level-2 Cache Array Access Register (L2AAR) . . . . . . . 264
-line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213, 264
-line replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . 214, 224
masking cache accesses with A20M# . . . . . . . . . . . . . . . 227
MESI states in the data. . . . . . . . . . . . . . . . . . . . . . . . . . . 207
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
predecode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–17, 208
prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–17, 220
sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
sector organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . 16
signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Super7 platform support . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
total internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
TR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
translation lookaside buffers (TLBs). . . . . . . . . . . . . . . . 205
write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
write cycle order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
write merge buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
write to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . 216
writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 16
writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
CACHE# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
generation (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
capacitor placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
large capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Index
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Capture-DR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Capture-IR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
measuring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CLK
switching characteristics
100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 296
60-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 297
CLK Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105, 275
states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
enhanced power management stop grant . . . . . . . . . 275
halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
normal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
state transitions (figure) . . . . . . . . . . . . . . . . . . . 276–277
stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193, 283
stop grant. . . . . . . . . . . . . . . . . . . . . . . . . . . 193, 278, 281
stop grant inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
switching characteristics
100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 296
66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 297
Coherency
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Compatibility, Floating-Point, MMX, and 3DNow!
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Configuration
power-on initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
signal timing (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
signal timing for 100-MHz bus operation (table) . . . . . . 306
signal timing for 66-MHz bus operation . . . . . . . . . . . . . 307
VCC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Connections
pin requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
power requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Control Register 0 (CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Control Register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Control Register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Control Register 3 (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Control Register 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Counter, Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
pin designations (figure) . . . . . . . . . . . . . . . . . . . . . . . . . 322
pin designations by function (table) . . . . . . . . . . . . . . . . 324
pin differences (table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
CR4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Cycles
bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
hold and hold acknowledge . . . . . . . . . . . . . . . . . . . . . . . 168
inquire . . . 94–99, 109, 113–114, 131, 139, 164, 168, 170,
. . . . 172, 174, 176–178, 182, 186, 222, 263, 275, 278–280
inquire and bus arbitration . . . . . . . . . . . . . . . . . . . . . . . 168
interrupt acknowledge . . . . . . . . 95, 98, 100, 106, 123, 138
locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 96
pipelined write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
special bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Index
writeback . . . . . . 94, 96–97, 110, 113, 139, 164, 172, 176,
. . . . . . . . . . . . . . . . . . . . . 178, 180, 186, 210, 264, 277, 280
D
D/C# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
D[63:0] Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Data
bus
AHOLD restriction . . . . . . . . . . . . . . . . . . . . . . . . 97, 180
AHOLD timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
aligned transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
BRDY# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
byte enable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
D[63:0] signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
data state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
memory reads and writes . . . . . . . . . . . . . . . . . . . . . . . 158
misaligned transfers . . . . . . . . . . . . . . . . . . . . . . 129, 184
parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 125
split cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MESI states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
types
3DNow!™ Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . 37
floating-point register . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MMX technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data/Code Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Data-NA# Requested State. . . . . . . . . . . . . . . . . . . . . . . . . . 156
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 269
DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
System Management Mode (SMM) . . . . . . . . . . . . .249–250
Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . 292
Descriptors and Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Device Identification Register (DIR) . . . . . . . . . . . . . . . . . 258
Diagrams
key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153, 309–312
waveform definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Digital Signal Processing Instructions . . . . . . . . . . . . . . . . . 90
DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Dissipation, Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
DP[7:0] Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Driven signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DSP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90, 239
Dual Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
337
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
E
EADS# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
EAS Register
time stamp counter value . . . . . . . . . . . . . . . . . . . . . . . . . 46
EAX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
BIST results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
cache accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
EBF Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
EBP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EBX Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ECX Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28, 46
EDI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EDX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
cache accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50–51
stepping ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
time stamp counter value . . . . . . . . . . . . . . . . . . . . . . . . . 46
EFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44, 47, 202, 229
Effective Bus Frequency Divisor Field . . . . . . . . . . . . . . . . 150
EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38, 242
EIP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
absolute ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
power and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Embedded Processor Features . . . . . . . . . . . . . . . . . . . . . . . . 1
EMMS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
EN Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Enhanced Power Management
special bus cycle (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 142
special bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Enhanced Power Management Register (EPMR) . . . . . . . 144
EPM 16-Byte I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
EPM Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . 142, 150
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
voltage identification output state . . . . . . . . . . . . . . . . . 147
EPMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44, 144
ESI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ESP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EWBE# Control (EWBEC) . . . . . . . . . . . . . . . . . . . . . . . . . . 229
EWBE# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 110, 229, 278
Exception. . . . 98–99, 108, 125, 192, 240, 249–250, 272–274
debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32–33
floating-point. . . . . . . . . . . . . . . . . . 111, 116, 237–238, 240
handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
handling floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . 237
machine check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MMX technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
summary (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
System Management Mode (SMM) . . . . . . . . . . . . . . . . . 250
Execution
latency (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3DNow!™ technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 26
execution latency (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 21, 237
multimedia . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 23–24, 239
register X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 24
338
23542A/0—September 2000
register Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 24
throughput (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Extended Feature Enable Register (EFER) . 44, 47, 202, 229
External
address strobe signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
write buffer empty signal . . . . . . . . . . . . . . . . . . . . . . . . . 110
EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
F
FEMMS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FERR# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 111, 238, 240
Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136, 141
Floated signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Floating-Point
and MMX/3DNow! instruction compatibility . . . . . . . . . 240
and multimedia execution units . . . . . . . . . . . . . . . . . . . 237
error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
handling exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
instructions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
register data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FLUSH# Signal . . . . . . . . . . . . . . . . . . 112, 199, 223, 252, 278
FPU
control word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
status word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
tag word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . 283, 296–297, 308
control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 105, 199
G
Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59, 62
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Generate Special Bus Cycle Bit . . . . . . . . . . . . . . . . . . . . . . 145
Global EWBE# Disable (GEWBED). . . . . . . . . . . . . . . . . . . 230
Ground
pin designations (table) . . . . . . . . . . . . . . . . . . . . . 325, 329
plane capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
pulldown resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
split planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
unused active high inputs . . . . . . . . . . . . . . . . . . . . . . . . . 293
GSBC Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
H
Halt
restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
HIGHZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Hit to
modified line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
modified line, AHOLD-initiated inquire. . . . . . . . . . . . . 178
modified line, HOLD-initiated inquire . . . . . . . . . . . . . . 172
shared or exclusive line, AHOLD-initiated inquire . . . . 176
shared or exclusive line, HOLD-initiated inquire . . . . . 170
HIT# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
HITM# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
HLDA Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Index
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Hold
acknowledge cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
acknowledge signal. . . . . . . . . . . . . . . . . . . . . .114, 168–170
HOLD Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
-initiated inquire hit to modified line. . . . . . . . . . . . . . . 172
-initiated inquire hit to shared or exclusive line . . . . . . 170
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295, 310
I
I/O
misaligned read and write . . . . . . . . . . . . . . . . . . . . . . . . 167
read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
trap doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
IBF Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
IEEE 1149.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 253
IEEE 754 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 31, 237
IEEE 854 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
IGNNE# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . 116, 238, 240
Ignore Numeric Exception . . . . . . . . . . . . . . . . . . . . . . . . . . 116
INIT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117, 242, 278
-initiated transition from protected mode to real mode 196
processor state after . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
output signal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
power-on configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 199
processor state after INIT . . . . . . . . . . . . . . . . . . . . . . . . 203
processor state after RESET . . . . . . . . . . . . . . . . . . . . . . 200
register state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
RESET requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
signals sampled during RESET . . . . . . . . . . . . . . . . . . . . 199
Input
capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
pin float conditions (table) . . . . . . . . . . . . . . . . . . . . . . . 141
pin types (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
setup and hold timing
100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 300
66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 304
Input/Output (I/O)
capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171, 173, 175, 275
bus arbitration cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
cycle hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
cycle hit to modified line . . . . . . . . . . . . . . . . . . . . . . . . . 113
cycles . . . . . . . . .94–99, 109, 113–114, 131, 139, 164, 168,
. . . . . . . . . . . 170, 172, 174, 176–178, 180, 182, 186, 222,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263, 275, 278–280
miss, AHOLD-initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3DNow!™ technology . . . . . . . . . . . . . . . . . . . . . .89–90, 239
3DNow!™ technology (table) . . . . . . . . . . . . . . . . . . . . 89–90
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
digital signal processing. . . . . . . . . . . . . . . . . . . . . . . . . . 239
digital signal processing (table) . . . . . . . . . . . . . . . . . . . . 90
EMMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FEMMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
floating-point (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
integer (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
MMX technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86, 239
Index
MMX technology (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PREFETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 220
RSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
serializing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
supported by the processor (table) . . . . . . . . . . . . . . . . . . 63
Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
WBINVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Integer
data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
instructions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interrupts . . . . . . . . . 130, 188, 192, 196, 237–238, 240, 242,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250, 273, 280
01h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
03h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
acknowledge. . . . . . . 95, 103, 106, 118, 120, 125, 184, 188
acknowledge cycle definition (table) . . . . . . . . . . . . . . . 188
acknowledge cycles . . . . . . . . . . 95, 98, 100, 106, 123, 138
clock grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
descriptor table register . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38, 118, 130
floating-point exceptions . . . . . . . . . . . . . . . . . . . . .237–238
gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196, 242
INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
IRQ13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
MMX instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123, 203, 242
redirection bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
service routine . . . . . . . . . . . . . . . . . . . . . 118, 123, 238, 241
STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
summary (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
system management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
type of. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
INTR Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118, 278
INV Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Invalidation Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
INVD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
IOBASE Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
K
KEN# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
L
L1 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
cache line (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
cache-line replacements . . . . . . . . . . . . . . . . . . . . . . . . . . 214
coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222, 227
data cache line (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . 207
disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 211–212
flushing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
inquire cycles (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
instruction cache line (figure) . . . . . . . . . . . . . . . . . . . . . 207
internal snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
MESI states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
sector organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . 16
339
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . .221, 225–226
write allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . 112–113, 139, 142
access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
built-in self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
cache line (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
cache sector and line organization (figure) . . . . . . . . . . 265
cache-line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
cache-line replacements. . . . . . . . . . . . . . . . . . . . . . . . . . 214
coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
data location (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
data reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
direct access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211–212
disabling for debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
inquire cycles (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
least recently used (LRU) algorithm . . . . . . . . . . . . . . . 215
Level-2 Cache Array Access Register (L2AAR). . . . . . . . 50
LRU field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
MESI states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
organization (figure). . . . . . . . . . . . . . . . . . . . . . . . . 206, 265
predecode bits not stored. . . . . . . . . . . . . . . . . . . . . . . . . 208
prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
sector organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . 16
states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . .221, 225–226
Super7 platform support . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
T/D bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
tag array testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213, 264
tag information (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
tag location (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
write allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
L2AAR . . . . . . . . . . . . . . . . . . . . . . . 44, 50, 212–213, 264–266
L3 Cache
debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
PCD signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Latency, execution (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Layout and Airflow Considerations . . . . . . . . . . . . . . . . . . 317
Level-2 Cache Array Access Register (L2AAR). . . . . 264–266
Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
LOCK# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Locked
cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
operation with BOFF# intervention . . . . . . . . . . . . . . . . 186
operation, basic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Logic
branch-prediction . . . . . . . . . . . . . . . . . . . . . . 15, 23, 25–26
external support of floating-point exceptions . . . . . . . . 238
symbol (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Low-Power Devices . . . . . . . . . . . . . . . . . . . . . 4, 286, 289, 334
M
M/IO# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Machine Check Address Register (MCAR) . . . . . .44–45, 202
Machine Check Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Machine Check Type Register (MCTR) . . . . . . . . .44–45, 202
Maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
MCAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44–45, 202
MCTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44–45, 202
340
23542A/0—September 2000
Memory
management registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
or I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
read and write, misaligned single-transfer . . . . . . . . . . . 160
read and write, single-transfer . . . . . . . . . . . . . . . . . . . . . 158
reads and writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
type range registers (MTRR) . . . . . . . . . . . . . . . . . . 49, 231
MESI . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 168, 172, 206, 227
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 207, 209
states in the data cache . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 11–26
branch-prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
centralized scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
enhanced RISC86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
instruction fetching and decode . . . . . . . . . . . . . . . . . . . . 17
instruction prefetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
predecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Misaligned
I/O read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
I/O transfers (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
memory transfers (table) . . . . . . . . . . . . . . . . . . . . . . . . . 160
single-transfer memory read and write . . . . . . . . . . . . . . 160
transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MMX Technology . . . . . . . . . . . . . . . . . . . . . . . . 19, 21–24, 127
3DNow!™ registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
INIT state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
instruction compatibility, floating-point and . . . . . . . . . 240
instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
instructions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
RESET state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . 44
MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
MTRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49, 231
Multimedia
and 3DNow!™ execution units . . . . . . . . . . . . . . . . . . . . . 239
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 239
functional unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
N
NA# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Negated signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Next Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
NMI Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123, 242, 278
No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128, 293
Non-Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Non-Pipelined Single-Transfer Memory Read/Write and
Write Delayed by EWBE#. . . . . . . . . . . . . . . . . . . . . 159
Normal State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
O
OBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2–3
pin designations (figure) . . . . . . . . . . . . . . . . . . . . . . . . . 326
pin designations by function (table) . . . . . . . . . . . . . . . . 328
pin differences (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Index
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
OPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Ordering Part Number (OPN) . . . . . . . . . . . . . . . . . . . . . . . 333
Output
delay timings
100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 298
66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 302
leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
pin float conditions (table) . . . . . . . . . . . . . . . . . . . . . . . 141
signal state after RESET (table) . . . . . . . . . . . . . . . . . . . 200
P
Package
Socket 7 platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Super7 platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Packed Decimal Data Register . . . . . . . . . . . . . . . . . . . . . . . 34
Page
cache disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
directory entry (PDE) . . . . . . . . . . . . . . . . . . . . . .57–58, 209
flush/invalidate register (PFIR) . . . . . . . . . . . . . . . . . . . 223
table entry (PTE) . . . . . . . . . . . . . . . . . . . . . . . . 57, 59, 209
writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 100, 108, 125, 158
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 108, 125
check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98–99, 108, 125
error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99, 125, 174, 255
flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
PCD Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124, 209, 219
generation (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
PCHK# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49–50, 202, 223
Pins
connection requirements . . . . . . . . . . . . . . . . . . . . . . . . . 293
designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321–329
float conditions (table). . . . . . . . . . . . . . . . . . . . . . . . . . . 141
I/O voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
input pin types (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
logic symbol (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
no-connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 93–139
Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156–157, 162
address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24–25
data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
register X and Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pipelined . . . . . . . . . . . . . . . .23, 122, 157, 162–163, 180, 220
burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 96, 107
design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Platform
Socket 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Super7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pointer, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power
and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
consumption and thermal resistance (figure) . . . . . . . . 315
dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
isolation region between planes . . . . . . . . . . . . . . . . . . . 291
Index
management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
management, enhanced . . . . . . . . . . . . . . . . . . . . . . . . . . 143
plane capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
PowerNow! Technology. See AMD PowerNow!™ Technology.
Power-on Configuration and Initialization . . . . . . . . . . . . . 199
Precision Real Data Registers . . . . . . . . . . . . . . . . . . . . . . . . 34
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–17, 208
PREFETCH Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
PREFETCH instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 220
software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Processor
absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
AMD PowerNow!™ technology. . . . . . . . . . . . . . . . . . . . . 143
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
cache organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4, 205
clock control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
heat dissipation path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
logic symbol (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
low-power devices . . . . . . . . . . . . . . . . . . . . . . 286, 289, 334
microarchitecture overview . . . . . . . . . . . . . . . . . . . . . . . . 11
multimedia execution unit . . . . . . . . . . . . . . . . . . . . . . . . 239
operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
pin connection requirements . . . . . . . . . . . . . . . . . . . . . . 293
power-on initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
process technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
signal switching characteristics . . . . . . . . . . . . . . . . . . . . 295
Socket 7 platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
software environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
standard-power devices. . . . . . . . . . . . . . . . . . . . . . 286, 334
state observability register (PSOR). . . . . . . . . . . . . 49, 202
Super7 platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
System Management Mode (SMM) . . . . . . . . . . . . . . . . . 241
test and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
write merge buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Processor State Observability Register (PSOR)
low-power version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Protected Mode
INIT-Initiated transition . . . . . . . . . . . . . . . . . . . . . . . . . . 196
real mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
PSOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49, 148, 202
PWT Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
generation (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
R
RDMSR Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
RDTSC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Read and Write
basic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
misaligned I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Reads, Burst Reads and Pipelined Burst . . . . . . . . . . . . . . 162
341
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
Real Mode
INIT-initiated transition . . . . . . . . . . . . . . . . . . . . . . . . . . 196
protected mode transition . . . . . . . . . . . . . . . . . . . . . . . . 196
Register X and Y
functional unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14, 27, 240
3DNow!™ technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
boundary scan (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
bypass (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
control 0 (CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
control 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
control 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
control 3 (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
control 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
data types, floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . 34
debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 269
descriptors and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
device identification (DIR) . . . . . . . . . . . . . . . . . . . . . . . 258
DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
DR6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
DR7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EBP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EBX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ECX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
enhanced power management (EPMR) . . . . . . . . . . . . . 144
EPMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
ESI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ESP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
extended feature enable (EFER) . . . . . . . 44, 47, 202, 229
floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FPU control word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FPU status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FPU tag word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
general-purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
instruction (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
level-2 cache array access (L2AAR) . . . . . . . . . . . . . . . . 264
machine check address (MCAR) . . . . . . . . . . . . .44–45, 202
machine check type (MCTR) . . . . . . . . . . . . . . . .44–45, 202
MCAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
memory type range (MTRR) . . . . . . . . . . . . . . . . . . . . . . 231
MMX technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
model-specific (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
packed decimal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
precision real data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
processor state observability (PSOR) . . . . . . . . . . . . . . . 148
processor state observability register (PSOR) . . . . . 49, 202
PSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49, 148
reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
segment (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SYSCALL/SYSRET target address (STAR) . . . 44, 48, 202
System Management Mode (SMM) initial state (table) 243
test (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
time stamp counter (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . 46
TR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
342
23542A/0—September 2000
UWCCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
X and Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21–22, 24
Regulator, Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Reserved (RSVD) Pins
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
pin designations (table) . . . . . . . . . . . . . . . . . . . . . 325, 329
RESET Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 127, 200, 278
signals sampled during reset . . . . . . . . . . . . . . . . . . . . . . 199
state of processor after reset . . . . . . . . . . . . . . . . . . . . . . 200
timing (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
timing for 100-MHz bus operation . . . . . . . . . . . . . . . . . . 306
timing for 66-MHz bus operation . . . . . . . . . . . . . . . . . . . 307
Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
RISC86 Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RSM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246, 249
RSVD Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
S
SAMPLE/PRELOAD Instruction . . . . . . . . . . . . . . . . . . . . . 260
Sampled signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Scheduler/Instruction Control Unit. . . . . . . . . . . . . . . . 14, 21
SCYC Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Sector, Write to a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216, 220
Segment
descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30, 59–61
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
task state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Serializing Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SGTC Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147, 281
Shift-DR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Shift-IR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Signals
A[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
A20M#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94, 242
ADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ADSC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
AHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 278
AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
APCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
BE[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 283
BOFF#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102, 182
BRDY# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
BREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
CACHE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105, 210
cache-related . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
D/C# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
D[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93–139
DP[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
EADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110, 229, 278
FERR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111, 240
floated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
FLUSH# . . . . . . . . . . . . . 112, 199, 223, 252, 278, 281–282
HIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Index
Preliminary Information
23542A/0—September 2000
HITM# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
HLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
IGNNE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116, 240
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117, 278, 281
INTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118, 278, 281
INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
KEN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
LOCK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
logic symbol (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
M/IO# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
NA#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
negated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
NMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123, 278, 281
output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
PCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
PCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
PWT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127, 278, 281
RSVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
sampled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
sampled during RESET . . . . . . . . . . . . . . . . . . . . . . . . . . 199
SCYC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SMI# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 241, 278, 281
SMIACT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131, 241
STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132, 278
switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 295
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
timing (figures) . . . . . . . . . . . . . . . . . . . . .159–197, 309–312
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
VCC2DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
VCC2H/L# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
VID[4:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137, 151
W/R#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
WB/WT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SIMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Single Instruction Multiple Data (SIMD) operations . . . . . 15
Single-Transfer Memory Read and Write. . . . . . . . . . . . . . 158
SMI# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 241, 278
SMIACT# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131, 241
SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131, 139, 164
cache states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
instruction cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
internal cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
processor-initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
exceptions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
instructions supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
interrupts (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
memory management registers . . . . . . . . . . . . . . . . . . . . . 54
model-specific registers (MSR) . . . . . . . . . . . . . . . . . . . . . 44
paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Software Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Special Bus Cycles
BRDY# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
cache invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Index
AMD-K6™-2E+ Embedded Processor Data Sheet
cache writeback invalidation . . . . . . . . . . . . . . . . . . . . . . 190
definition (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
differentiating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142, 190
encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142, 190
enhanced power management . . . . . . . . . . . . . . . . . . . . . 145
EPM stop grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
EWBE# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
flush acknowledge . . . . . . . . . . . . . . . . . . 112, 164, 190, 212
halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190–191, 278
shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190, 192
signal states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
stop grant . . . . . . . . . . . . . . . . . . . . . . . . . 132, 190, 193, 279
System Management Mode (SMM) . . . . . . . . . . . . . . . . . 247
Speculative EWBE# Disable (SEWBED). . . . . . . . . . . . . . . 230
Split Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Standard-Power Devices . . . . . . . . . . . . . . . . . . . . . 4, 286, 334
STAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44, 48, 202
State
bus machine (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
processor
after INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
after RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Stepping ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Stop
clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
power dissipation . . . . . . . . . . . . . . . . . . . . . . . . .289–290
clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193, 283
grant
inquire state. . . . . . . . . . . . . . . . . . . . . . . . . 275, 278–280
state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193, 278, 280
grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Stop Grant Time-Out Counter Field . . . . . . . . . . . . . . . . . . 150
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
STPCLK# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132, 278
Super7 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
input setup and hold timings for 100-MHz bus. . . . . . . . 300
input setup and hold timings for 66-MHz bus. . . . . . . . . 304
output delay timings for 100-MHz bus . . . . . . . . . . . . . . 298
output delay timings for 66-MHz bus . . . . . . . . . . . . . . . 302
signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
valid delay, float, setup, and hold timings . . . . . . . . . . . 298
SYSCALL Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SYSCALL/SYSRET Target Address Register (STAR) . 44, 48,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
SYSRET Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
System
management interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
management interrupt active. . . . . . . . . . . . . . . . . . . . . . 131
System Design
airflow management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
ATX form factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
component placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
decoupling recommendations . . . . . . . . . . . . . . . . . . . . . 292
heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
pin connection requirements . . . . . . . . . . . . . . . . . . . . . . 293
power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
343
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . 241
AMD PowerNow!™ features . . . . . . . . . . . . . . . . . . . . . . 145
base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
debugging in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
default register values . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
enhanced power management . . . . . . . . . . . . . . . . . . . . . 145
entering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
exceptions in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
halt restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
I/O trap doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
I/O trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
initial register state (table) . . . . . . . . . . . . . . . . . . . . . . . 243
interrupts in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
memory (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
NMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
RSM instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
SMI# interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
SMIACT# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
state-save area (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
system management interrupt active signal . . . . . . . . . 131
system management interrupt signal . . . . . . . . . . . . . . . 130
T
TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Task State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
TCK Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
TDI Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
TDO Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286, 313, 315
ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
case-to-ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
extended for low-power devices . . . . . . . . . . . . . . . . . . . 313
storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Terminology, Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Test
boundary-scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
built-in self-test (BIST). . . . . . . . . . . . . . . . . . . . . . . . . . . 251
cache inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
data input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
data output signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
L2 cache testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
-logic-reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
register 12 (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
scan chain (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
signal timing (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
signal timing (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
tag array testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
test access port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
three-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Test Access Port (TAP)
instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
HIGHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
344
23542A/0—September 2000
IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
SAMPLE/PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
boundary scan (BSR). . . . . . . . . . . . . . . . . . . . . . . . . . . 255
bypass (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
device identification (DIR) . . . . . . . . . . . . . . . . . . . . . 258
instruction register (IR) . . . . . . . . . . . . . . . . . . . . . . . . 255
signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
states
capture-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
capture-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
shift-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
shift-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
test-logic-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
update-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
update-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315, 318–319
design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
extended temperature rating . . . . . . . . . . . . . . . . . . . . . . 313
heat dissipation path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
layout and airflow consideration . . . . . . . . . . . . . . . . . . . 317
measuring case temperature (figure) . . . . . . . . . . . . . . . 317
model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Third-Party Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Three-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Time Stamp Counter Register (TSC). . . . . . . . . . . . . . . . . . . 46
Timing
bus cycles (figures) . . . . . . . . . . . . . . . . . . . . . . . . . .159–197
switching characteristics (figures) . . . . . . . . . . . . . .309 –312
TLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
TMS Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
TR12 . . . . . . . . . . . . . . . . . . . . . . . . 44, 46, 202, 210, 218, 263
Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Translation Lookaside Buffer (TLB) . . . . . . . . . . . . . . . . . . 205
TRST# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
TSC . . . . . . . . . . . . . . . . . . . . . . . . . .44, 46, 202, 278–279, 281
TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 61–62, 244, 272
U
UC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
UC/WC Cacheability Control Register (UWCCR) . . 200, 202,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Uncacheable Memory . . . . . . . . . . . . . . . . . . . . . . 49, 230–231
UWCCR . . . . . . . . . . . . . . . . . . . . . . . . . 49, 200, 202, 210, 232
V
VCC2 Pins
absolute ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
pin designations (table) . . . . . . . . . . . . . . . . . . . . . 325, 329
power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
processor voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
RESET requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
VCC2DET Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
VCC2H/L# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
VCC3 Pins
absolute ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
I/O voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
pin designations (table) . . . . . . . . . . . . . . . . . . . . . 325, 329
Index
Preliminary Information
23542A/0—September 2000
power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
RESET requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
unused active low inputs . . . . . . . . . . . . . . . . . . . . . . . . . 293
VID[4:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137, 151
VID[4:0] Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
VIDC Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
VIDO Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Voltage
active high signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
active low signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
bus divisor (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
CLK switching characteristics . . . . . . . . . . . . . . . . . . . . . 296
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
dual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287, 291
input low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
plane isolation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317–318
supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
VCC2 detect signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
VCC2 High/Low Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
VCC2DET signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
voltage identification control (table) . . . . . . . . . . . . . . . 147
VSS Pins
connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
pin designations (table) . . . . . . . . . . . . . . . . . . . . . . 325, 329
unused active high inputs . . . . . . . . . . . . . . . . . . . . . . . . 293
AMD-K6™-2E+ Embedded Processor Data Sheet
cycles . . . . . 94, 96–97, 110, 113, 139, 164, 172, 176, 178,
. . . . . . . . . . . . . . . . . . . . . 180, 182, 186, 210, 264, 277, 280
L1 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
L2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
memory writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
or writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Write-Combining Memory . . . . . . . . . . . . . . . . . . 49, 230–231
Writethrough
coherency state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
memory writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
W
W/R# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
WB/WT# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
WBINVD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
WC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
WHCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44, 48, 202, 219
Write
allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . 208, 215–216, 219
conditions (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
logic mechanisms and conditions (figure) . . . . . . . . . 219
handling control register (WHCR) . . . . . . . . . . . . . 202, 219
to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
to a sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216, 220
Write Merge Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
EWBE# control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
EWBEC settings (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 231
memory type range registers (MTRRs) . . . . . . . . . . . . . 231
memory-range restrictions . . . . . . . . . . . . . . . . . . . . . . . . 233
examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
valid masks and range sizes (table) . . . . . . . . . . . . . . 234
performance (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
UC/WC Cacheability Control Register (UWCCR). . . . . 232
uncacheable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
write cycle order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
write-combining memory . . . . . . . . . . . . . . . . . . . . . . . . . 231
Write/Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Writeback . . . . . . . . . 105, 107–108, 119, 126, 131, 139, 142,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164–165, 190, 276
burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 16
coherency state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Index
345
Preliminary Information
AMD-K6™-2E+ Embedded Processor Data Sheet
346
23542A/0—September 2000
Index