DP8391/NS32491 Serial Network Interface General Description Features The DP8391 Serial Network Interface (SNI) provides the Manchester data encoding and decoding functions for IEEE 802.3 Ethernet/Cheapernet type local area networks. The SNI interfaces the DP8390 Network Interface Controller (NIC) to the Ethernet transceiver cable. When transmitting, the SNI converts non-return-to-zero (NRZ) data from the controller and clock pulses into Manchester encoding and sends the converted data differentially to the transceiver. The opposite process occurs on the receive path, where a digital phase-locked loop decodes 10 Mbit/s signals with as much as g 20 ns of jitter. The DP8391 SNI is a functionally complete Manchester encoder/decoder including ECL like balanced driver and receivers, on board crystal oscillator, collision signal translator, and a diagnostic loopback circuit. The SNI is part of a three chip set that implements the complete IEEE compatible network node electronics as shown below. The other two chips are the DP8392 Coax Transceiver Interface (CTI) and the DP8390 Network Interface Controller (NIC). Incorporated into the CTI are the transceiver, collision and jabber functions. The Media Access Protocol and the buffer management tasks are performed by the NIC. There is an isolation requirement on signal and power lines between the CTI and the SNI. This is usually accomplished by using a set of miniature pulse transformers that come in a 16-pin plastic DIP for signal lines. Power isolation, however, is done by using a DC to DC converter. Y Y Y Y Y Y Y Y Y Y Compatible with Ethernet II, IEEE 802.3 10base5 and 10base2 (Cheapernet) 10 Mb/s Manchester encoding/decoding with receive clock recovery Patented digital phase locked loop (DPLL) decoder requires no precision external components Decodes Manchester data with up to g 20 ns of jitter Loopback capability for diagnostics Externally selectable half or full step modes of operation at transmit output Squelch circuits at the receive and collision inputs reject noise High voltage protection at transceiver interface (16V) TTL/MOS compatible controller interface Connects directly to the transceiver (AUI) cable Table of Contents 1.0 System Diagram 2.0 Block Diagram 3.0 Functional Description 3.1 Oscillator 3.2 Encoder 3.3 Decoder 3.4 Collision Translator 3.5 Loopback 4.0 Connection Digram 5.0 Pin Description 6.0 Absolute Maximum Ratings 7.0 Electrical Characteristics 8.0 Switching Characteristics 9.0 Timing and Load Diagrams 10.0 Physical Dimensions 1.0 System Diagram IEEE 802.3 Compatible Ethernet/Cheapernet Local Area Network Chip Set TL/F/6758 – 1 C1995 National Semiconductor Corporation TL/F/6758 RRD-B30M115/Printed in U. S. A. DP8391/NS32491 Serial Network Interface July 1986 2.0 Block Diagram TL/F/6758 – 2 FIGURE 1 3.0 Functional Description accuracy on the transmitted signal frequency. Stray capacitance can shift the crystal’s frequency out of range, causing the transmitted frequency to exceed its 0.01% tolerance. The frequency marked on the crystal is usually measured with a fixed shunt capacitance (CL) that is specified in the crystal’s data sheet. This capacitance for 20 MHz crystals is typically 20 pF. The capacitance between the X1 and X2 pins of the SNI, of the PC board traces and the plated through holes plus any stray capacitance such as the socket capacitance, if one is used, should be estimated or measured. Once the total sum of these capacitances is determined, the value of additional external shunt capacitance required can be calculated. This capacitor can be a fixed 5% tolerance component. The frequency accuracy should be measured during the design phase at the transmit clock pin (TXC) for a given pc layout. Figure 2 shows the crystal connection. The SNI consists of five main logical blocks: a) the oscillatorÐgenerates the 10 MHz transmit clock signal for system timing. b) the Manchester encoder and differential output driverÐ accepts NRZ data from the controller, performs Manchester encoding, and transmits it differentially to the transceiver. c) the Manchester decoderÐreceives Manchester data from the transceiver, converts it to NRZ data and clock pulses, and sends them to the controller. d) the collision translatorÐindicates to the controller the presence of a valid 10 MHz signal at its input. e) the loopback circuitryÐwhen asserted, switches encoded data instead of receive input signals to the digital phase-locked loop. 3.1 OSCILLATOR The oscillator is controlled by a 20 MHz parallel resonant crystal connected between X1 and X2 or by an external clock on X1. The 20 MHz output of the oscillator is divided by 2 to generate the 10 MHz transmit clock for the controller. The oscillator also provides internal clock signals to the encoding and decoding circuits. TL/F/6758 – 3 CL e Load capacitance specified by the crystal’s manufacturer CP e Total parasitic capacitance including: a) SNI input capacitance between X1 and X2 (typically 5 pF) b) PC board traces, plated through holes, socket capacitances Crystal Specification Resonant frequency 20 MHz g 0.001% at 25§ C Tolerance Note 1: When using a Viking (San Jose) VXB49N5 crystal, the external capacitor is not required, as the CL of the crystal matches the input capacitance of the DP8391. g 0.005% 0–70§ C Stability Type AT-Cut Circuit Parallel Resonance The 20 MHz crystal connection to the SNI requires special care. The IEEE 802.3 standard requires a 0.01% absolute FIGURE 2. Crystal Connection 3.2 MANCHESTER ENCODER AND DIFFERENTIAL DRIVER The encoder combines clock and data information for the transceiver. Data encoding and transmission begins with the transmit enable input (TXE) going high. As long as TXE re2 signal. Once the input exceeds the squelch requirements, carrier sense (CRS) is asserted. Receive data (RXD) and receive clock (RXC) become available typically within 6 bit times. At this point the digital phase-locked loop has locked to the incoming signal. The DP8391 decodes a data frame with up to g 20 ns of jitter correctly. The decoder detects the end of a frame when the normal mid-bit transition on the differential input ceases. Within one and a half bit times after the last bit, carrier sense is de-asserted. Receive clock stays active for five more bit times before it goes low and remains low until the next frame. Figures 7, 8 and 9 illustrate the receive timing. 3.0 Functional Description (Continued) mains high, transmit data (TXD) is encoded out to the transmit-driver pair (TX g ). The transmit enable and transmit data inputs must meet the setup and hold time requirements with respect to the rising edge of transmit clock. Transmission ends with the transmit enable input going low. The last transition is always positive at the transmit output pair. It will occur at the center of the bit cell if the last bit is one, or at the boundary of the bit cell if the last bit is zero. The differential line driver provides ECL like signals to the transceiver with typically 5 ns rise and fall times. It can drive up to 50 meters of twisted pair AUI Ethernet transceiver cable. These outputs are source followers which need external 270X pulldown resistors to ground. Two different modes, full-step or half-step, can be selected with SEL input. With SEL low, transmit a is positive with respect to transmit b in the idle state. With SEL high, transmit a and transmit b are equal in the idle state, providing zero differential voltage to operate with transformer coupled loads. Figures 4, 5 and 6 illustrate the transmit timing. 3.4 COLLISION TRANSLATOR The Ethernet transceiver detects collisions on the coax cable and generates a 10 MHz signal on the transceiver cable. The SNI’s collision translator asserts the collision detect output (COL) to the DP8390 controller when a 10 MHz signal is present at the collision inputs. The controller uses this signal to back off transmission and recycle itself. The collision detect output is de-asserted within 350 ns after the 10 MHz input signal disappears. The collision differential inputs ( a and b) should be terminated in exactly the same way as the receive inputs. The collision input also has a squelch circuit that rejects signals with pulse widths less than 8 ns (negative going), or with levels less than b175 mV. Figure 10 illustrates the collision timing. 3.3 MANCHESTER DECODER The decoder consists of a differential input circuitry and a digital phase-locked loop to separate Manchester encoded data stream into clock signals and NRZ data. The differential input should be externally terminated if the standard 78X transceiver drop cable is used. Two 39X resistors connected in series and one optional common mode bypass capacitor would accomplish this. A squelch circuit at the input rejects signals with pulse widths less than 8 ns (negative going), or with levels less than b175 mV. Signals more negative than b300 mV and with a duration greater than 30 ns are always decoded. This prevents noise at the input from falsely triggering the decoder in the absence of a valid 3.5 LOOPBACK FUNCTIONS Logic high at loopback input (LBK) causes the SNI to route serial data from the transmit data input, through its encoder, returning it through the phase-locked-loop decoder to receive data output. In loopback mode, the transmit driver is in idle state and the receive input circuitry is disabled. 4.0 Connection Diagram *Refer to the Oscillator section TL/F/6758 – 4 Top View FIGURE 3 Order Number DP8391N See NS Package Number N24C 3 5.0 Pin Descriptions Pin No. Name 1 COL I/O O Collision Detect Output. A TTL/MOS level active high output. A 10 MHz ( a 25%–15%) signal at the collision input will produce a logic high at COL output. When no signal is present at the collision input, COL output will go low. Description 2 RXD O Receive Data Output. A TTL/MOS level signal. This is the NRZ data output from the digital phase-locked loop. This signal should be sampled by the controller at the rising edge of receive clock. 3 CRS O Carrier Sense. A TTL/MOS level active high signal. It is asserted when valid data from the transceiver is present at the receive input. It is de-asserted one and a half bit times after the last bit at receive input. 4 RXC O Receive Clock. A TTL/MOS level recovered clock. When the phase-locked loop locks to a valid incoming signal a 10 MHz clock signal is activated on this output. This output remains low during idle (5 bit times after activity ceases at receive input). 5 SEL I Mode Select. A TTL level input. When high, transmit a and transmit b outputs are at the same voltage in idle state providing a ‘‘zero’’ differential. When low, transmit a is positive with respect to transmit b in idle state. 6 GND 7 LBK 8 9 Negative Supply Pin. I Loopback. A TTL level active high on this input enables the loopback mode. X1 I Crystal or External Frequency Source Input (TTL). X2 O Crystal Feedback Output. This output is used in the crystal connection only. It must be left open when driving X1 with an external frequency source. 10 TXD I Transmit Data. A TTL level input. This signal is sampled by the SNI at the rising edge of transmit clock when transmit enable input is high. The SNI combines transmit data and transmit clock signals into a Manchester encoded bit stream and sends it differentially to the transceiver. 11 TXC O Transmit Clock. A TTL/MOS level 10 MHz clock signal derived from the 20 MHz oscillator. This clock signal is always active. 12 TXE I Transmit Enable. A TTL level active high data encoder enable input. This signal is also sampled by the SNI at the rising edge of transmit clock. 13 14 TXb TX a O Transmit Output. Differential line driver which sends the encoded data to the transceiver. These outputs are source followers and require 270X pulldown resistors to GND. 15 16 NC 17 CAP 18 19 VCC 20 NC 21 22 RXb RX a I Receive Input. Differential receive input pair from the transceiver. 23 24 CDb CD a I Collision Input. Differential collision input pair from the transceiver. No Connection. O Bypass Capacitor. A ceramic capacitor (greater than 0.001 mF) must be connected from this pin to GND. Positive Supply Pins. A 0.1 mF ceramic decoupling capacitor must be connected across VCC and GND as close to the device as possible. No Connection. 4 6.0 Absolute Maximum Ratings Supply Voltage (VCC) Recommended Operating Conditions 6V Input Voltage (TTL) 0 to 5.5V Supply Voltage (VCC) 5V g 5% Ambient Temperature 0§ to 70§ C Note: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. b 5.5 to a 16V Input Voltage (differential) Output Voltage (differential) 0 to 16V b 40 mA Output Current (differential) b 65§ to 150§ C Storage Temperature Lead Temperature (soldering, 10 sec) 300§ C 2.95W* Package Power Rating at 25§ C (PC Board Mounted) Derate Linearly at the rate of 23.8 mW/§ C *For actual power dissipation of the device please refer to Section 7.0. ESD rating is to be determined. 7.0 Electrical Characteristics VCC e 5V g 5%, TA e 0§ to 70§ C (Notes 1 & 2) Symbol Parameter Max Units 0.8 V VIN e VCC VIN e VCC 50 500 mA mA Input Low Current (TTL) Input Low Current (RX g CD g ) VIN e 0.5V VIN e 0.5V b 300 b 700 mA mA VCL Input Clamp Voltage (TTL) V Ouptut High Voltage (TTL/MOS) IIN e b12 mA IOH e b100 mA b 1.2 VOH VOL Output Low Voltage (TTL/MOS) IOL e 8 mA IOS Output Short Circuit Current (TTL/MOS) VOD Differential Output Voltage (TX g ) 78X termination, and 270X from each to GND VOB Diff. Output Voltage Imbalance (TX g ) same as above VDS Diff. Squelch Threshold (RX g CD g ) VCM Diff. Input Common Mode Voltage (RX g CD g ) ICC Power Supply Current VIH Input High Voltage (TTL and X1) VIL Input Low Voltage (TTL and X1) IIH Input High Current (TTL) Input High Current (RX g CD g ) IIL Test Conditions Min 2.0 V 3.5 V 0.5 V b 40 b 200 mA g 500 g 1200 mV g 40 mV b 175 b 300 mV 5.25 5.25 V 270 mA 10Mbit/s 8.0 Switching Characteristics VCC e 5V g 5%, TA e 0§ to 70§ C (Note 2) Symbol Parameter Figure Min Typ Max Units OSCILLATOR SPECIFICATION tXTH X1 to Transmit Clock High 12 8 20 ns tXTL X1 to Transmit Clock Low 12 8 20 ns 42 TRANSMIT SPECIFICATION tTCd Transmit Clock Duty Cycle at 50% (10 MHz) 12 tTCr Transmit Clock Rise Time (20% to 80%) 12 50 tTCf Transmit Clock Fall Time (80% to 20%) tTDs Transmit Data Setup Time to Transmit Clock Rising Edge 4 & 12 20 ns tTDh Transmit Data Hold Time from Transmit Clock Rising Edge 4 & 12 0 ns tTEs Transmit Enable Setup Time to Trans. Clock Rising Edge 4 & 12 20 ns tTEh Transmit Enable Hold Time from Trans. Clock Rising Edge 5 & 12 0 tTOd Transmit Output Delay from Transmit Clock Rising Edge 4 & 12 40 ns tTOr Transmit Output Rise Time (20% to 80%) 12 7 ns tTOf Transmit Output Fall Time (80% to 20%) 12 7 tTOj Transmit Output Jitter 12 tTOh Transmit Output High Before Idle in Half Step Mode 5 & 12 tTOi Transmit Output Idle Time in Half Step Mode 5 & 12 12 58 % 8 ns 8 ns ns g 0.25 ns ns 200 ns 800 ns Note 1: All currents into device pins are positive, all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 2: All typicals are given for VCC e 5V and TA e 25§ C. 5 8.0 Switching Characteristics VCC e 5V g 5%, TA e 0§ to 70§ C (Note 2) (Continued) Symbol Parameter Figure Min Typ Max 40 50 Units RECEIVE SPECIFICATION tRCd Receive Clock Duty Cycle at 50% (10 MHz) 12 60 % tRCr Receive Clock Rise Time (20% to 80%) 12 8 ns tRCf Receive Clock Fall Time (80% to 20%) 12 8 ns tRDr Receive Data Rise Time (20% to 80%) 12 8 ns tRDf Receive Data Fall Time (80% to 20%) 12 8 tRDs Receive Data Stable from Receive Clock Rising Edge tCSon Carrier Sense Turn On Delay 7 & 12 50 ns tCSoff Carrier Sense Turn Off Delay 8, 9 & 12 160 ns tDAT Decoder Acquisition Time 7 700 ns tDrej Differential Inputs Rejection Pulse Width (Squelch) 7 tRd Receive Throughput Delay 7 & 12 g 40 8 8 & 12 ns ns 30 ns 150 ns COLLISION SPECIFICATION tCOLon Collision Turn On Delay 10 & 12 50 ns tCOLoff Collision Turn Off Delay 10 & 12 350 ns LOOPBACK SPECIFICATION tLBs Loopback Setup Time 11 20 ns tLBh Loopback Hold Time 11 0 ns Note 2: All typicals are given for VCC e 5V and TA e 25§ C. 9.0 Timing and Load Diagrams TL/F/6758 – 5 FIGURE 4. Transmit Timing - Start of Transmission 6 9.0 Timing and Load Diagrams (Continued) TL/F/6758 – 6 FIGURE 5. Transmit Timing - End of Transmission (last bit e 0) TL/F/6758 – 7 FIGURE 6. Transmit Timing - End of Transmission (last bit e 1) 7 9.0 Timing and Load Diagrams (Continued) TL/F/6758 – 8 FIGURE 7. Receive Timing - Start of Packet TL/F/6758 – 9 FIGURE 8. Receive Timing - End of Packet (last bit e 0) 8 9.0 Timing and Load Diagrams (Continued) TL/F/6758 – 10 FIGURE 9. Receive Timing - End of Packet (last bit e 1) TL/F/6758 – 11 FIGURE 10. Collision Timing TL/F/6758 – 12 FIGURE 11. Loopback Timing TL/F/6758 – 13 *27 mH transformer is used for testing purposes, 100 mH transformers (Valor, LT1101, or Pulse Engineering 64103) are recommended for application use. FIGURE 12. Test Loads 9 DP8391/NS32491 Serial Network Interface 10.0 Physical Dimensions inches (millimeters) Lit. Ý103053 Molded Dual in Line Pkg (N) Order Number DP8391N NS Package Number N24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.