May 2001 Advance Information AS7C1026A AS7C31026A ® 5V/3.3V 64K X 16 CMOS SRAM Features • Latest 6T 0.25u CMOS technology • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packaging • AS7C1026A (5V version) • AS7C31026A (3.3V version) • Industrial and commercial versions • Organization: 65,536 words × 16 bits • Center power and ground pins for low noise • High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time • Low power consumption: ACTIVE - 44-pin 400 mil SOJ - 44-pin TSOP 2 - 48-ball 6 × 8 mm CSP/mBGA • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA - 660 mW (AS7C1026A) / max @ 10 ns - 324 mW (AS7C31026A) / max @ 10 ns • Low power consumption: STANDBY - 55 mW (AS7C1026A) / max CMOS I/O - 36 mW (AS7C31026A) / max CMOS I/O Pin arrangement Logic block diagram 44-Pin SOJ (400 mil), TSOP 2 A0 A3 A4 A5 A6 64K × 16 Array GND A7 I/O buffer Control circuit A15 A14 A13 A12 A11 A8 A9 Column decoder WE A10 I/O0–I/O7 I/O8–I/O15 UB OE LB CE 0000048-CSP/mini Ball-Grid-Array Package A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AS7C1026A AS7C31026A A2 VCC Row decoder A1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC A B C D E F G H 1 LB I/O8 I/O9 VSS VDD I/O14 I/O15 NC 2 3 OE A0 A3 UB I/O10 A5 I/O11 NC I/O12 NC I/O13 A14 NC A12 A8 A9 4 A1 A4 A6 A7 NC A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VDD VSS I/O6 I/O7 NC Selection guide AS7C1026A-10 AS7C31026A-10 AS7C1026A-12 AS7C31026A-12 AS7C1026A-15 AS7C31026A-15 AS7C1026A-20 AS7C31026A-20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns AS7C1026A 120 110 100 100 mA AS7C31026A 90 80 80 80 mA AS7C1026A 10 10 10 15 mA AS7C31026A 10 10 10 15 mA Maximum operating current Maximum CMOS standby current 5/17/01; v.0.9.4 Alliance Semiconductor P. 1 of 9 Copyright © Alliance Semiconductor. All rights reserved. AS7C1026A AS7C31026A ® Functional description The AS7C1026A and AS7C31026A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 65,536 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications. When CE is high the devices enter standby mode. The AS7C1026A is guaranteed not to exceed 55 mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0–I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026A) or 3.3V supply (AS7C31026A). the device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the smallest possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and external dimensions of 8 mm × 6 mm. Absolute maximum ratings Parameter Symbol Min Max Unit AS7C1026A Vt1 –0.50 +7.0 V AS7C31026A Vt1 –0.50 +5.0 V Voltage on any pin relative to GND Both Vt2 –0.50 VCC +0.50 V Power dissipation Both PD – 1.0 W Storage temperature (plastic) Both Tstg –65 +150 °C Ambient temperature with VCC applied Both Tbias –55 +125 °C DC current into outputs (low) Both IOUT – 20 mA Voltage on VCC relative to GND Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode H X X X X High Z High Z Standby (ISB), ISBI) L H L L H DOUT High Z Read I/O0–I/O7 (ICC) L H L H L High Z DOUT Read I/O8–I/O15 (ICC) L H L L L DOUT DOUT Read I/O0–I/O15 (ICC) L L X L L DIN DIN Write I/O0–I/O15 (ICC) L L X L H DIN High Z Write I/O0–I/O7 (ICC) L L X H L High Z DIN Write I/O8–I/O15 (ICC) L L H X H X X H X H High Z High Z Output disable (ICC) Key: H = High, L = Low, X = don’t care. 5/17/01; v.0.9.4 Alliance Semiconductor P. 2 of 9 AS7C1026A AS7C31026A ® Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature † Device AS7C1026A AS7C31026A AS7C1026A AS7C31026A Both commercial industrial Symbol VCC VCC VIH VIH VIL† TA TA Min 4.5 3.0 2.2 2.0 –0.5 0 –40 Nominal 5.0 3.3 – – – – – Max 5.5 3.6 VCC + 0.5 VCC + 0.5 0.8 70 85 Unit V V V V V o C oC VIL min. = –3.0V for pulse width less than tRC/2. DC operating characteristics (over the operating range)1 -10 Parameter -12 -15 -20 Sym Test conditions Device Input leakage current | ILI | VCC = Max VIN = GND to VCC Both – 1 – 1 – 1 – 1 µA Output leakage current | ILO | VCC = Max CE = VIH, VOUT = GND to VCC Both – 1 – 1 – 1 – 1 µA VCC = Max, CE ≤ VIL outputs open, f = fMax = 1/tRC AS7C1026A – 120 – 110 – 100 – 100 mA ICC AS7C31026A – 90 – 80 – 80 – 80 mA VCC = Max, CE ≤ VIL, outputs open, f = fMax = 1/tRC AS7C1026A – 30 – 25 – 20 – 20 ISB AS7C31026A – 30 – 25 – 20 – 20 VCC = Max, CE ≥ VCC–0.2V, VIN ≤ GND + 0.2V or VIN ≥ VCC–0.2V, f = 0 AS7C1026A – 10 – 10 – 10 – 15 ISB1 AS7C31026A – 10 – 10 – 10 – 15 VOL IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V VOH IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V Operating power supply current Standby power supply current Output voltage Min Max Min Max Min Max Both Min Max Unit mA mA Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE, LB, UB VIN = 0V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF 5/17/01; v.0.9.4 Alliance Semiconductor P. 3 of 9 AS7C1026A AS7C31026A ® Read cycle (over the operating range)3,9 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Notes Read cycle time tRC 10 – 12 – 15 – 20 – ns Address access time tAA – 10 – 12 – 15 – 20 ns 3 Chip enable (CE) access time tACE – 10 – 12 – 15 – 20 ns 3 Output enable (OE) access time tOE – 5 – 6 – 7 – 8 ns Output hold from address change tOH 2 – 3 – 3 – 3 – ns 5 CE Low to output in low Z tCLZ 0 – 0 – 0 – 0 – ns 4, 5 CE High to output in high Z tCHZ – 3 – 3 – 4 – 5 ns 4, 5 OE Low to output in low Z tOLZ 0 – 0 – 0 – 0 – ns 4, 5 Byte select access time tBA – 5 – 6 – 7 – 8 ns Byte select Low to low Z tBLZ 0 – 0 – 0 – 0 – ns 4, 5 Byte select High to high Z tBHZ – 5 – 6 – 6 – 8 ns 4, 5 OE High to output in high Z tOHZ – 3 – 3 – 4 – 5 ns 4, 5 Power up time tPU 0 – 0 – 0 – 0 – ns 4, 5 Power down time tPD – 10 – 12 – 15 – 20 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined output/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address DataOUT tAA tOH Previous data valid tOH Data valid Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9 tRC Address tAA OE tOE tOLZ tOH CE tLZ tOHZ tHZ tACE LB, UB tBLZ tBA DataIN 5/17/01; v.0.9.4 tBHZ Data valid Alliance Semiconductor P. 4 of 9 AS7C1026A AS7C31026A ® Write cycle (over the operating range) 11 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Notes Write cycle time tWC 10 – 12 – 15 – 20 – ns Chip enable (CE) to write end tCW 8 – 10 – 12 – 12 – ns Address setup to write end tAW 8 – 9 – 10 – 12 – ns Address setup time tAS 0 – 0 – 0 – 0 – ns Write pulse width tWP 7 – 8 – 9 – 12 – ns Address hold from end of write tAH 0 – 0 – 0 – 0 – ns Data valid to write end tDW 5 – 6 – 8 – 10 – ns Data hold time tDH 0 – 0 – 0 – 0 – ns 5 Write enable to output in high Z tWZ – 6 – 6 – 6 – 8 ns 4, 5 Output active from write end tOW 1 – 1 – 1 – 2 – ns 4, 5 Byte select low to end of write tBW 8 – 10 – 12 – 12 – ns Write waveform 1 (WE controlled)10,11 tWC Address tWR tCW CE tBW LB, UB tAW tAS tWP WE tDW DataIN tDH Data valid tWZ DataOUT tOW Data undefined high Z Write waveform 2 (CE controlled)10,11 tWC Address tAS tWR tCW CE tAW tBW LB, UB tWP WE tDH tDW Data valid DataIN tCLZ DataOUT 5/17/01; v.0.9.4 high Z tWZ Data undefined Alliance Semiconductor tOW high Z P. 5 of 9 AS7C1026A AS7C31026A ® AC test conditions – – – – Thevenin Equivalent: 168W DOUT +1.728V (5V and 3.3V) Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. +5V +3.3V 480W +3.0V GND DOUT 90% 10% 90% 2 ns Figure A: Input pulse 10% 255W 320W DOUT C(14) GND Figure B: 5V Output load 255W C(14) GND Figure C: 3.3V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ± 500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C=30pF, except all high Z and low Z parameters where C=5pF. 5/17/01; v.0.9.4 Alliance Semiconductor P. 6 of 9 AS7C1026A AS7C31026A ® Package dimensions c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-pin TSOP 2 Min (mm) A E He 44-pin TSOP 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 D l A2 A 0–5° A1 e b 0.05 A2 0.95 1.05 b 0.30 0.45 c 0.127 (typical) D 18.28 18.54 E 10.03 10.29 He 11.56 11.96 l D e E1 E2 Pin 1 c B A2 A A1 b 5/17/01; v.0.9.4 Seating Plane E2 Alliance Semiconductor 1.2 A1 e 44-pin SOJ Max (mm) A A1 A2 B b c D E E1 E2 e 0.80 (typical) 0.40 0.60 44-pin SOJ 400 mil Min (in) Max (in) 0.128 0.148 0.025 – 0.105 1.115 0.026 0.032 0.015 0.020 0.007 0.013 1.120 1.130 0.370 NOM 0.395 0.405 0.435 0.445 0.050 NOM P. 7 of 9 AS7C1026A AS7C31026A ® 48-ball FBGA Bottom View 6 5 4 3 Top View 2 Ball #A1 index Ball A1 1 * A B C D SRAM DIE C1 C F G H J Elastomer A B B1 *pin 1 indicator will show as engraved circle and/or Inc. trade mark Detail View Side View A E2 D E E2 Y E Die Die E1 0.3/Tµp (In mils) Minimum Typical Maximum A – 0.75 – B 5.90 8.00 8.10 B1 – 3.75 – C 7.90 8.00 8.10 C1 – 5.25 – D – 0.35 – E – – 1.20 E1 – 0.68 – E2 0.22 0.25 0.27 Y – – 0.08 5/17/01; v.0.9.4 Alliance Semiconductor Notes 1 Bump counts: 48 (8 row x 6 column). 2 Pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3 Units: millimeters. 4 All tolerance are +/- 0.050 unless otherwise specified. 5 Typ: typical. 6 Y is coplanarity: 0.08 (max). P. 8 of 9 AS7C1026A AS7C31026A ® Ordering codes Package \ Access time Plastic SOJ, 400 mil Volt/Temp 10 ns 15 ns 20 ns AS7C1026A-10JC AS7C1026A-12JC AS7C1026A-15JC AS7C1026A-20JC 5V industrial AS7C1026A-10JI AS7C1026A-12JI AS7C1026A-15JI AS7C1026A-20JI 3.3V commercial AS7C31026A-10JC AS7C31026A-12JC AS7C31026A-15JC AS7C31026A-20JC 5V commercial AS7C1026A-12TC AS7C1026A-15TC AS7C1026A-20TC AS7C31026A-12TC AS7C31026A-15TC AS7C31026A-20TC AS7C31026A-12TI AS7C31026A-15TI AS7C31026A-20TI AS7C1026A-10TC TSOP 2, 10.2 x 18.4 mm 3.3V commercial AS7C31026A-10TC CSP/BGA, 6 x 8 mm 12 ns 5V commercial 3.3V industrial AS7C31026A-10TI 5V commercial AS7C1026A-10BC AS7C1026A-12BC AS7C1026A-15BC AS7C1026A-20BC 3.3V commercial AS7C31026A-10BC AS7C31026A-12BC AS7C31026A-15BC AS7C31026A-20BC 3.3V industrial AS7C31026A-12BI AS7C31026A-15BI AS7C31026A-20BI AS7C31026A-10BI Part numbering system AS7C X Voltage: SRAM Blank=5V CMOS prefix 3=3.3V CMOS 5/17/01; v.0.9.4 1026 Device numbe r –XX X Package: Access J=SOJ 400 mil time T=TSOP 2, 10.2 x 18.4 mm B=CSP/BGA, 6 x 8 mm Alliance Semiconductor C Temperature range: C= Commercial: 0° C to 70° C I= Industrial: -40° C to 85° C P. 9 of 9 © Copyright Alliance Semiconductor Corporation. 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