ETC BUF11702PWP

BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
D
D
D
D
D
D
D
D
D
10 Gamma Correction Channels With
>10 mA Output Current
1 VCOM Buffer With >30 mA Output Current
Low Power Buffer . . . IDD < 5 mA
Unity Gain Buffers Capable of Driving
Large Capacitive Loads
Input Ranges Matched to LCD Reference
Requirements
Buffer1 Drives 10 mA Within 100 mV of VDD
Buffer10 Drives 10 mA Within 100 mV of
GND
Specified for 0°C to 85°C . . . 4.5 V to 16 V
1 pA Input Bias Current
PWP PACKAGE
(TOP VIEW)
VDD
NC
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUTCOM
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
NC
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
INCOM
GND
description
NC – No internal connection
The BUF11702 is a 10+1-channel buffer targeted
toward the needs of modern high resolution LCD
panels. These high resolution LCD panels are driven by external LCD source drivers, which require a varying
number of references. Due to nonideal characteristics of the LCD panels, the LCD source drivers must produce
nonlinear voltages to the LCD panel. This is called gamma-correction.
Buffers 1 through 10 have output voltage drive characteristics matched to the gamma correction voltage/current
requirements of these panels and are used to drive the reference inputs of the LCD source drivers. All outputs
can swing very close to both rails, but the actual limits are determined by the individual channel’s input offset
voltage, common-mode input range, and load current being delivered. The input/output characteristics have
been set at commonly requested levels.
The VCOM channel has increased output drive capability to meet the drive requirements of the common-node
of these panels.
The BUF11702 is available in the 28-pin PowerPAD package that enables it to meet the power handling
requirements of driving these load currents at the required voltage levels.
A flow through pin out has been adopted to allow simple PCB routing and maintain the cost effectiveness of this
solution.
Each buffer is capable of driving heavy capacitive loads and offers fast load current switching, often necessary
when used to drive large LCDs.
All inputs and outputs of the BUF11702 incorporate internal ESD protection circuits that prevent functional
failures at voltages up to 2000 V as tested under MIL-STD-883C Method 3015; however care should be
exercised in handling these devices as exposure to ESD may result in degradation of parametric performance.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
equivalent schematics of inputs and outputs
INPUT STAGE OF BUFFERS
1 TO 5 AND 11
INPUT STAGE OF BUFFERS
6 TO 10
OUTPUT STAGE OF ALL BUFFERS
Internal to
BUF11702
VS
VS
VS
Next Stage
Buffer
Input
GND
Buffer
Output
Buffer
Input
Buffer
Output
Internal to
BUF11702
Next Stage
Previous
Stage
Inverting
Input
Buffer
Output
Previous
Stage
GND
GND
Internal to
BUF11702
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VDD
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ 25°C
POWER RATING
PWP (28)
0.72
27.9
4.3 W
‡ See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report
(literature number SLMA002), for more information on the PowerPAD package. The thermal data was
measured on a PCB layout based on the information in the section entitled Texas Instruments
Recommended Board for PowerPAD on page 33 of the before mentioned document.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
recommended operating conditions
Supply voltage, VDD
Common-mode input voltage range, VICR§
MIN
MAX
UNIT
4.5
16
V
VDD
VDD–1
VDD
V
Buffers 1, 2, 3, 4 & 5
1
Buffers 6, 7, 8, 9 & 10
0
VCOM buffer
1
Operating free-air temperature, TA
0
85
°C
§ The common-mode input range was chosen to match the expected input/output range required for LCD reference buffers. These devices are
unity-gain buffers, and as such the effective input range will ultimately be limited by the voltage swing of the outputs and what load currents are
being driven.
electrical characteristics over recommended operating free-air temperature range, VDD = 4.5 V
to 16 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RS = 50 Ω
VIO
Input offset voltage
VI = VDD/2,
/2
IIB
Input bias current
VI = VDD/2
kSVR
Supply voltage rejection ratio (∆VDD/∆VIO)
5 V to 16 V
VDD = 4
4.5
IDD
Supply current
VO = VDD/2,, VI = VDD/2,,
VDD = 10 V
Buffer gain
† Full range is 0°C to 85°C.
VI = 5 V
POST OFFICE BOX 655303
TA†
25°C
TYP
MAX
1.5
Full Range
1
Full Range
25°C
62
60
80
2.5
Full Range
mV
dB
3.7
5.5
0.9995
UNIT
pA
200
Full Range
25°C
12
15
25°C
25°C
• DALLAS, TEXAS 75265
MIN
mA
V/V
3
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range, VDD = 4.5 V to
16 V, TA = 25°C (unless otherwise noted) (continued)
output characteristics
PARAMETER
Load regulation
TEST CONDITIONS
VCOM buffer
sinking
VDD = 10 V,
IO = 1 mA to 30 mA
VCOM buffer
sourcing
VDD = 10 V,
IO = –1 mA to –30 mA
Buffers 1–10
sinking
VDD = 10 V,
IO = 1 mA to 10 mA
Buffers 1–10
sourcing
VDD = 10 V,
IO = –1 mA to –10 mA
VOSH1
High-level
g
saturated output
voltage
Buffer 1
VDD = 16 V,,
VI = 16 V
IO = –10 mA,,
VOSL10
Low-level saturated output
voltage
Buffer 10
VDD = 16 V,,
VI = 0 V
IO = 10 mA,,
VOH1
Buffer 1
VDD = 10 V,,
VI = 9.8 V
IO = –10 mA,,
VOH2/3/4/5
Buffer 2/3/4/5
VDD = 10 V,,
VI = 9.5 V
IO = –10 mA,,
Buffer 6/7/8/9
VDD = 10 V,,
VI = 8 V
IO = –10 mA,,
VOH10
Buffer 10
VDD = 10 V,,
VI = 8 V
IO = –10 mA,,
VOHCOM
VCOM buffer
VDD = 10 V,,
VI = 8 V
IO = –30 mA,,
VOL1
Buffer 1
VDD = 10 V,,
VI = 2 V
IO = 10 mA,,
VOL2/3/4/5
Buffer 2/3/4/5
VDD = 10 V,,
VI = 2 V
IO = 10 mA,,
Buffer 6/7/8/9
VDD = 10 V,,
VI = 0.5 V
IO = 10 mA,,
VOL10
Buffer 10
VDD = 10 V,,
VI = 0.2 V
IO = 10 mA,,
VOLCOM
VCOM buffer
VDD = 10 V,
VI = 2 V
IO = 30 mA,
VOH6/7/8/9
VOL6/7/8/9
High level output voltage
High-level
Low level output voltage
Low-level
POST OFFICE BOX 655303
MIN
TYP
MAX
1
1.2
Full Range
1
Full Range
0.85
Full Range
0.85
Full Range
15.85
Full range
15.8
25°C
9.75
9.7
25°C
9.45
Full range
9.4
25°C
7.95
Full range
7.9
25°C
7.95
Full range
7.9
25°C
7.95
Full range
7.9
V
8
V
8
V
8
2
V
2.05
2.1
2
2.05
2.1
0.5
Full range
0.55
0.6
0.2
Full range
0.25
0.3
2
V
V
9.5
Full range
• DALLAS, TEXAS 75265
0.15
9.8
Full range
25°C
V
0.2
25°C
Full range
1
15.9
0.1
Full range
25°C
mV/mA
1.5
25°C
25°C
1
1.5
25°C
25°C
1.2
2.5
25°C
25°C
UNIT
2.5
25°C
Full range
† Full range is 0°C to 85°C.
4
TA†
25°C
2.05
2.1
V
V
V
V
V
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range, VDD = 4.5 V to
16 V, TA = 25°C (unless otherwise noted) (continued)
ac characteristics
PARAMETER
BW–3dB
3dB
3 dB Bandwidth
3-dB
SR
Slew rate
TEST CONDITIONS
Buffers 1–10
CL = 100 pF,
pF
RL = 2 kΩ
CL = 100 pF,,
VIN = 2 V to 8 V
RL = 2 kΩ,,
Transient load regulation disturbance
IO = 0 to ±5 mA,
CL = 100 pF,
VO = 5 V,
tT = 0.1 µs
Transient load response
See Figure 2
ts(I-sink)
Settling time – current
IO = 0 to –5 mA,
CL = 100 pF
ts(I-source)
Settling time – current
ts
Vn
VCOM buffer
Buffers 1–10
VCOM buffer
Crosstalk
TYP
1
0.6
1
0.7
MAX
UNIT
MHz
V/µs
900
mV
180
mV
VO = 5 V,
RL = 2 kΩ,
1
µs
IO = 0 to 5 mA,
CL = 100 pF
VO = 5 V,
RL = 2 kΩ,
2
µs
Buffers 1–10
1 10
VI = 4.5 V to 5.5 V
VI = 5.5 V to 4.5 V
0.1%
6
0.1%
4.6
VCOM buffer
VI = 4.5 V to 5.5 V
VI = 5.5 V to 4.5 V
0.1%
5.8
0.1%
5.6
Settling time – voltage
Noise voltage
MIN
Buffers 1–10
VCOM buffer
45
VI = 5 V,
V f = 1 kHz
VIp–p = 6 V
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• DALLAS, TEXAS 75265
40
f = 1 kHz
85
µs
nV/√Hz
dB
5
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
Buffer
RNULL
CL
RL
Figure 1. Bandwidth and Phase Shift Test Circuit
Buffer
VO
RS
5V
CS
5V
CL
RL
LCD Driver
Equivalent Load
VTL
tT
V1
Test
Source
Ch1–Ch10
V1
0V
VTL
2V
tT
0.1 µs
CS
100 pF
RS
100 Ω
CL
100 pF
RL
1 kΩ
Sink
Ch1–Ch10
10 V
2V
0.1 µs
100 pF
100 Ω
100 pF
1 kΩ
Figure 2. Transient Load Response Test Circuit
Buffer
tT
VO
5V
RNULL
RL
10 V
5V
0V
VTL
CL
VTL
Figure 3. Transient Load Regulation Test Circuit
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
DC Characteristics
VIO
IIB
Input offset voltage
vs Input voltage
4, 5, 6
Input bias current
vs Free-air temperature
VOH
VOL
High-level output voltage
vs High-level output current
8, 9, 10, 11, 12
Low-level output voltage
vs Low-level output current
13, 14, 15, 16, 17
IDD
Supply current
7
vs Supply voltage
18
vs Free-air temperature
19
vs Supply voltage
20
vs Free-air temperature
21
AC Characteristics
BW
PSRR
Vn
ZO
–3 dB Bandwidth
vs Load capacitance
22, 23, 24
Input-output phase shift
vs Load capacitance
25, 26, 27
Power supply rejection ratio
vs Frequency
28
Crosstalk
vs Frequency
29
Noise voltage
vs Frequency
30
Output impedance
vs Frequency
31
Transient Characteristics
IDD, VO
Supply current, output voltage, supply voltage
32
Large signal voltage follower
33, 34, 35
Small signal voltage follower
36, 38
Small signal pulse response
Transient load response
Transient load regulation
37
sourcing
39
sinking
40
sinking
41
sourcing
42
VCOM
43
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7
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
TYPICAL CHARACTERISTICS
dc curves
INPUT OFFSET VOLTAGE
vs
INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
INPUT VOLTAGE
20
20
V IO – Input Offset Voltage – mV
10
5
0
–5
–10
–15
–20
10
5
0
–5
–10
–15
–20
1
2
3 4 5 6 7
VI – Input Voltage – V
8
9
10
Figure 4
V OH – High-Level Output Voltage – V
I IB – Input Bias Current – pA
2
4
6
VI – Input Voltage – V
200
150
100
50
0
8
10 20 30 40 50 60 70
TA – Free-Air Temperature – °C
–15
0
9
TA = 0°C
8
TA = 25°C
7.5
7
TA = 85°C
6.5
6
5.5
TA = 0°C
8
TA = 25°C
TA = 85°C
7
6
50
100
25
75
125 150
IOH – High-Level Output Current – mA
Figure 10
8
10
VDD = 10 V
Channel 1
TA = 0°C
9.8
9.7
TA = 25°C
9.6
9.5
9.4
TA = 85°C
9.3
9.2
9.1
9
0
0
50
100
150
200
250
IOH – High-Level Output Current – mA
10
VDD = 10 V
Channels 6 to 10
9
8
7
TA = 0°C
TA = 25°C
6
TA = 85°C
5
4
3
2
1
0
25
75
125
50
100
150
IOH – High-Level Output Current – mA
Figure 11
POST OFFICE BOX 655303
5 10 15 20 25 30 35 40 45 50
IOH – High-Level Output Current – mA
Figure 9
0
5
4
6
VI – Input Voltage – V
9.9
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
V OH – High-Level Output Voltage – V
VDD = 10 V
Channels 2 to 5
2
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
Figure 8
10
8
–10
10
9
5
80 85
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0
–5
10
VDD = 10 V
Channel 1
Figure 7
8.5
0
Figure 6
10
VDD = 10 V
9.5
5
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
250
0
10
Figure 5
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
VDD = 10 V
VCOM Buffer
15
–20
0
V OH – High-Level Output Voltage – V
0
• DALLAS, TEXAS 75265
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
10
V OH – High-Level Output Voltage – V
V IO – Input Offset Voltage – mV
20
VDD = 10 V
Channels 6 to 10
15
V IO – Input Offset Voltage – mV
VDD = 10 V
Channels 1 to 5
15
V OH – High-Level Output Voltage – V
INPUT OFFSET VOLTAGE
vs
INPUT VOLTAGE
VDD = 10 V
VCOM Buffer
9
8
TA = 0°C
7
6
5
TA = 25°C
4
3
TA = 85°C
2
1
0
0
50
100
150
200
250
IOH – High-Level Output Current – mA
Figure 12
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
TYPICAL CHARACTERISTICS
dc curves (continued)
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
8
7
6
5
4
TA = 0°C
3
TA = 25°C
TA = 85°C
2
1
0
0
5
VDD = 10 V
Channels 6 to 9
4.5
4
3.5
3
2.5
2
TA = 0°C
1.5
TA = 25°C
1
TA = 85°C
0.5
125
25
75
50
100
150
IOL – Low-Level Output Current – mA
2
1
0
50
100
150
200
250
IOL – Low-Level Output Current – mA
Figure 15
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
4
0.6
0.5
0.4
TA = 0°C
0.3
TA = 25°C
TA = 85°C
0
TA = 0°C
VDD = 10 V
VCOM Buffer
9
3.5
I DD – Supply Current – mA
0.7
V OL– Low-Level Output Voltage – V
0.8
8
7
6
5
TA = 25°C
4
3
TA = 85°C
2
3
TA = 25°C
TA = 70°C
2.5
2
TA = 85°C
1.5
1
0.5
TA = 0°C
1
0
0
10 15 20 25 30 35 40 45 50
IOL – Low-Level Output Current – mA
5
0
50
100
150
200
IOL – Low-Level Output Current – mA
250
Figure 17
Figure 16
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VDD – Supply Voltage – V
Figure 18
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4
15 V
3.5
I DD – Supply Current – mA
0
TA = 85°C
1.5
50
100
150
25
75
125
IOL – Low-Level Output Current – mA
10
VDD = 10 V
Channels 10
0.1
3
2.5
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1
0.2
TA = 0°C
TA = 25°C
Figure 14
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.9
4
3.5
0
0
VDD = 10 V
Channel 10
4.5
0.5
0
Figure 13
V OL – Low-Level Output Voltage – V
V OL– Low-Level Output Voltage – V
VDD = 10 V
Channels 1 to 5
9
V OL– Low-Level Output Voltage – V
V OL – Low-Level Output Voltage – V
10
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
10 V
3
5V
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
60
70
80
TA – Free-Air Temperature – °C
Figure 19
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• DALLAS, TEXAS 75265
9
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
TYPICAL CHARACTERISTICS
ac curves
–3 dB BANDWIDTH
vs
SUPPLY VOLTAGE
–3 dB BANDWIDTH
vs
FREE-AIR TEMPERATURE
– 3 dB BANDWIDTH
vs
LOAD CAPACITANCE
1.2
1.25
3.5
1
0.75
VCOM Buffer
0.5
RL = 2 kΩ
CL = 100 pF
TA = 25°C
0.25
0
5V
1
10, 15 V
0.8
VCOM Buffer
0.6
5, 10, 15 V
0.4
0.2
RL = 2 kΩ
CL = 100 pF
0
0
2
4
6
8
10 12
VDD – Supply Voltage – V
14
16
10 V
0.7
15 V
0.6
0.5
0.4
0.3
0.2
0
1000
3
2
RNULL = 50
1.5
1
15 V
60
40
0 100 200 300 400 500 600 700 800 900 1000
CL – Load Capacitance – pF
1000
Figure 25
RNULL = 50
40
RL = 2 kΩ
VCOM Buffer
f = –3 dB BW
50
45
40
VDD = 5 V
35
30
25
VDD = 10 V
20
VDD = 15 V
15
10
5
0
0
100 200 300 400 500 600 700 800 900 1000
CL – Load Capacitance – pF
0
100 200 300 400 500 600 700 800 900 1000
CL – Load Capacitance – pF
Figure 27
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• DALLAS, TEXAS 75265
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
PSRR – Power Supply Rejection Ratio – dB
55
Input-Output Phase Shift
60
20
10
80
0
200
400
600
800
CL – Load Capacitance – pF
INPUT-OUTPUT PHASE SHIFT
vs
LOAD CAPACITANCE
RNULL = 0
5V
10 V
Figure 24
80
Figure 26
100
20
60
0
RL = 2 kΩ
Channel 1
f = –3 dB BW
120
2.5
0
140
1000
140
INPUT-OUTPUT PHASE SHIFT
vs
LOAD CAPACITANCE
100
200
400
600
800
CL – Load Capacitance – pF
INPUT-OUTPUT PHASE SHIFT
vs
LOAD CAPACITANCE
VDD = 10 V
RL = 2 kΩ
Channel 1
RNULL = 0
Figure 23
120
0.5
Figure 22
0
200
400
600
800
CL – Load Capacitance – pF
VDD = 10 V
RL = 2 kΩ
Channel 1
f = –3 dB BW
1
0
0.5
0.1
0
15 V
1.5
80
Input-Output Phase Shift
BW – –3 dB Bandwidth – MHz
BW – –3 dB Bandwidth – MHz
10 20 30 40 50 60 70
TA – Free-Air Temperature – °C
3.5
RL = 2 kΩ
VCOM Buffer
0.8
10 V
2
– 3 dB BANDWIDTH
vs
LOAD CAPACITANCE
1.1
0.9
2.5
Figure 21
– 3 dB BANDWIDTH
vs
LOAD CAPACITANCE
1
RL = 2 kΩ
Channel 1
3
0
0
Figure 20
Input-Output Phase Shift
BW – –3 dB Bandwidth – MHz
Channel 9
BW – –3 dB Bandwidth – MHz
BW – –3 dB Bandwidth – MHz
Channels 1 to 10
VDD = 10 V
RL = 2 kΩ
CL = 100 pF
80
70
60
50
Channels 1 to 10
VCOM Buffer
40
30
20
10
0
10
100
1k
10 k 100 k
f – Frequency – Hz
Figure 28
1M
10 M
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
TYPICAL CHARACTERISTICS
ac curves (continued)
CROSSTALK
vs
FREQUENCY
NOISE VOLTAGE
vs
FREQUENCY
0
120
–40
–50
–60
–70
–80
5V
–90
10 V
–100
15 V
–110
–120
1000
100
80
Zo – Output Impedance – Ω
–30
V n – Noise Voltage – nV/
–20
Hz
RL = 1 kΩ
CL = 100 pF
VI = 60% VDD
Adjacent Channels
–10
Crosstalk – dB
OUTPUT IMPEDANCE
vs
FREQUENCY
VCOM Buffer
60
40
Channels 1 to 10
20
0
10
1k
10 k
100
f – Frequency – Hz
Figure 29
100 k
10
100
1k
10 k
f – Frequency – Hz
100 k
Figure 30
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100
VCOM Buffer
10
Channel 1 to 10
1
0.1
0.01
0.1 k
1k
10 k
100 k
f – Frequency – Hz
1M
10 M
Figure 31
11
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
TYPICAL CHARACTERISTICS
transient curves
SUPPLY VOLTAGE, OUTPUT VOLTAGE
AND SUPPLY CURRENT
VDD
12
8
4
0
3
VDD = 0 to 15 V
RL = 2 kΩ
CL = 100 pF
VI = VDD/2
TA = 25°C
1
0
–1
0
5
10
15
20
25
30
35
40
45
50
4
VCOM
Buffer
3
2
Channels 1 to 10
1
0
0
2
6
4
VO – Output Voltage – V
8
VCOM
Buffer
Channels 1 to 10
0
10
15
20
t – Time – ns
25
30
9
6
0
15
12
9
VCOM
Buffer
6
Channels 1 to 10
3
0
0
4
8
12 16 20
t – Time – ns
Figure 35
POST OFFICE BOX 655303
12
3
Figure 34
12
16 18
VDD = 15 V
VI = 9 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
VI
VO – Output Voltage – V
8
0
10
5
14
15
VI – Input Voltage – V
VDD = 10 V
VI = 6 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
2
0
6
8 10 12
t – Time – ns
LARGE SIGNAL VOLTAGE FOLLOWER
10
2
4
Figure 33
LARGE SIGNAL VOLTAGE FOLLOWER
4
1
0
Figure 32
6
2
5
t – Time – ns
VI
3
• DALLAS, TEXAS 75265
24
28
32
36
VI – Input Voltage – V
IDD
2
4
VDD = 5 V
VI = 3 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
VI
VO – Output Voltage – V
IDD – Supply Current – mA
VO – All Channels
5
V I – Input Voltage – V
16
VO – Output Voltage – V
VDD – Supply Voltage – V
LARGE SIGNAL VOLTAGE FOLLOWER
20
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
TYPICAL CHARACTERISTICS
transient curves (continued)
2.55
VDD = 5 V
VI = 100 mV
RL = 2 kΩ
CL = 100 pF
TA = 25°C
2.50
2.45
VO – Output Voltage – V
2.40
2.60
VI
5.05
VDD = 10 V
VI = 100 mV
RL = 2 kΩ
CL = 100 pF
TA = 25°C
5
4.95
Channels 1 to 10
Channels 1 to 10
5.05
2.55
VCOM Buffer
VCOM Buffer
4.95
2.45
2.40
0 0.5
1
1.5 2 2.5 3 3.5
t – Time – ns
4 4.5
0
5
0.50
1
1.50 2
2.50 3
3.50
4
4.90
4.50
t – Time – ns
Figure 36
Figure 37
TRANSIENT LOAD RESPONSE – SOURCING
VI
7.55
VDD = 15 V
VI = 100 mV
RL = 2 kΩ
CL = 100 pF
TA = 25°C
7.50
7.45
VI – Input Voltage – V
7.60
VLT – Input Voltage – V
SMALL SIGNAL VOLTAGE FOLLOWER
VO – Output Voltage – V
5
2.50
7
6
5
4
3
2
1
0
Transient Load
Pulse
Channel 1
VDD = 10 V, VI = 5 V,
CS = 100 pF, RS = 100 Ω,
CL = 100 pF, RL = 1 kΩ,
tT = 0.1 µs, TA = 25°C
5.15
5.1
5.05
7.40
7.60
5
7.55
4.95
7.50
VCOM Buffer
Output Voltage
7.45
7.40
Channels 1 to 10
0
0.5
1
1.5
2
2.5
4.9
4.85
3
3.5
4
4.5
0
0.1
0.2
t – Time – ns
Figure 38
0.3 0.4 0.5 0.6
t – Time – ns
0.7
0.8
0.9
VO – Output Voltage – V
VI
5.10
VO – Output Voltage – V
2.60
VI – Input Voltage – V
SMALL SIGNAL PULSE RESPONSE
V I – Input Voltage – V
SMALL SIGNAL VOLTAGE FOLLOWER
4.8
1
Figure 39
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
TYPICAL CHARACTERISTICS
5.1
5.05
5
4.95
4.9
4.85
0
0.1 0.2 0.3 0.4 0.5
0.6 0.7 0.8 0.9
1
Channel 1
VDD = 10 V, VI = 5 V,
RL = 1 kΩ, tT = 0.1 µs,
TA = 25°C
5.8
CL = 100 pF
CL = 1000 pF
5.4
5.2
5
CL = 10 nF
RNULL = 100 Ω
4.6
0
1
2
3
4
5
t – Time – ns
Figure 40
IL– Load Current – mA
IL– Load Current – mA
Sinking
6
VCOM Buffer
VDD = 10 V, VI = 5 V,
RL = 500 Ω, tT = 0.1 µs,
TA = 25°C
0
–6
5.2
5
4.8
CL = 10 nF
RNULL = 100 Ω
4.6
CL = 500 pF and
1000 pF
Sourcing
6
VO – Output Voltage – V
5.4
CL = 1000 pF
CL = 10 nF
5.5
5
CL = 100 nF
RNULL = 20 Ω
4.5
4
t – Time – ns
3.5
6 7 8 9 10 11 12 13 14 15
t – Time – ns
Figure 42
Figure 43
4.4
14
8
12
–12
CL = 100 pF
2
7
TRANSIENT LOAD REGULATION – VCOM BUFFER
Channel 1
VDD = 10 V, VI = 5 V,
RL = 1 kΩ, tT = 0.1 µs,
TA = 25°C
1
6
Figure 41
TRANSIENT LOAD REGULATION – SOURCING
0
4.8
4.8
t – Time – ns
6
5
4
3
2
1
0
5.6
3
4
VO – Output Voltage – V
Channel 1
VDD = 10 V, VI = 5 V,
CS = 100 pF, RS = 100 Ω,
CL = 100 pF, RL = 1 kΩ,
tT = 0.1 µs, TA = 25°C
6
5
4
3
2
1
0
5
6
7
8
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1
2
3
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4
5
VO – Output Voltage – V
7
6
5
4
3
2
1
0
TRANSIENT LOAD REGULATION – SINKING
IL– Load Current – mA
TRANSIENT LOAD RESPONSE – SINKING
VO – Output Voltage – V
VLT – Input Voltage – V
transient curves (continued)
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
The BUF11702 was designed to buffer the gamma correction reference voltages supplied to the
digital-to-analog converters (DACs) within the LCD source drivers and provide the voltage/current requirements
for LCD panel common node (VCOM). See Figure 44.
10
10
BUF11702
TMS57569
VCOM Buffer
Reference
Gamma Correction
Buffer 1–10
Timing and
Control
OUT001
Start Pulse
TMS57569
OUT001
OUT384
OUT384
TMS57605
TMS57605
OUT001
Panel
Timing
Controller
OUT256
1024 × 768
or
1280 × 1024
TFT-LCD Panel
VCOM
OUT001
OUT256
Figure 44. LCD Panel Drive Block Diagram
Depending on the size of the display, the BUF11702 will have to drive the gamma correction voltage inputs of a
different number of LCD source drivers. A typical LCD source driver available from TI is the TMS57569.
A 64 gray scale LCD source driver employs internal DACs to convert a 6-bit digital word into a corresponding
analog voltage. A 64 gray scale LCD source driver typically has 10 reference nodes to allow for external gamma
voltage correction. Gamma voltage correction is used to match the characteristic of the LCD source driver chip
as close as possible to the characteristic of the actual LCD panel to improve the overall picture quality. External
gamma correction voltages are often generated using a simple resistor ladder, as shown in Figure 45. The
BUF11702 acts as a buffer for the various nodes on the gamma correction resistor ladder. Due to the low output
impedance of the BUF11702 it forces the external gamma correction voltage on the respective reference node
of the LCD source driver providing an accurate match between the source driver and the LCD panel.
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
AVDD
BUF11702
LCD Source Driver
GMA
GMA
GMA
Positive Polarity
GMA
GMA
GMA
GMA
GMA
Negative Polarity
GMA
GMA10
Figure 45. Reference Buffer for LCD Source Driver
16
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
gamma correction
Figure 46 shows a typical 10-reference voltage gamma correction curve. As can be seen from this curve, the
various voltages that each buffer encounters vary greatly.
VDD1
GMA1
GMA2
GMA3
GMA4
GMA5
GMA6
GMA7
GMA8
GMA9
GMA10
VSS1
0
10
20
30
40
Input Data HEX0
Figure 46. Gamma Correction Curve
The LCD source driver DAC uses the reference voltages and internal resistor ladder to produce individual
voltages for each input code.
For gamma correction voltages GMA1 through GMA5, the voltage levels would be between VDD1/2 and VDD1,
and for GMA6 through GMA10, the voltage levels would be between GND and VDD1/2. That means that buffers 1
to 5 must have input stages that swing close to the positive rail, but will not have to swing very close to ground (or
the negative rail). Therefore buffers 1 through 5 have only a single NMOS input pair. Buffers 6 to 10 have similar
but opposite requirements in that they must have input ranges that go down to ground (or negative rail), enabling
them to have only a PMOS input pair.
The output stages have been designed to match the characteristic of the input stage. That means that the output
stage of buffer 1 swings very close to the positive range, whereas its ability to swing to GND (or negative rail) is
limited. Buffers 2 to 5 have output stages with slightly larger output resistances, as they will not have to swing as
close to the positive rail as buffer 1. The converse is true for buffers 6 to 10 in the sense that they have to swing
closer to ground than the positive rail.
This approach significantly reduces the silicon area and cost of the whole solution. However due to this
architecture the right buffer needs to be connected to the right gamma correction voltage. Connect buffer 1 to the
gamma voltage closest to the positive rail, buffers 2 to 5 to the following voltages. Buffer 10 should be connected
to the gamma correction voltage closest to GND (or the negative rail), buffers 9 through 6 to the following
voltages.
When the LCD source driver has its gamma correction curves matched to the LCD panel, not all 10 reference
inputs will be required; quite often only 4 might be used. The quad channel BUF4701 is an ideal device for these
applications; it combines high drive with wide bandwidth in a 10-pin MSOP.
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
driving LCD source drivers with >64 grey scale
When a greater number of gray scales are required, two or more BUF11702 devices can be used in parallel, see
Figure 47. This might introduce some redundancy, but still provides a cost-effective way of producing more
reference voltages over the use of quad op-amps.
BUF11702
BUF11702
OUT1
LCD Driver
GMA1
GMA2
OUT1
OUT2
OUT2
GMA3
GMA4
Positive Polarity
OUT3
GMA5
GMA6
OUT3
OUT4
OUT4
GMA7
GMA8
OUT7
GMA9
GMA10
OUT7
OUT8
GMA11
GMA12
OUT8
Negative Polarity
OUT9
OUT9
GMA13
GMA14
OUT10
OUT10
GMA15
GMA16
Figure 47. Two BUF11702 Driving a 16-Reference LCD Source Driver
An 8-bit source driver typically has 16 to 18 input pins for external gamma correction voltages. Using two
BUF11702 ICs, a total of 20 gamma correction voltages can be provided to the respective LCD source driver.
Despite the possible redundancy, the overall cost of two BUF11702s is very competitive.
18
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
transient load regulation
The BUF11702 has been designed to be able to sink/source dc currents in excess of 10 mA. Its output stage has
been designed to deliver output current transients with little disturbance of the output voltage. However there are
times when very fast current pulses are required. Therefore, in LCD source driver buffer applications, it is quite
normal for capacitors to be placed at the outputs of the reference buffers. These are to improve the transient load
regulation. These will typically vary from 100 pF and more. The BUF11702 buffers were designed to drive
capacitances in excess of 100 pF and retain effective phase margins above 50°, see Figure 48.
140
VDD = 10 V
RL = 2 kΩ
120
Phase Shift – Deg
100
80
60
40
20
0
10
100
CL – Load Capacitance – pF
1000
Figure 48. Phase Shift Between Output and Input vs Load Capacitance for Buffers 1–10
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
transient load regulation (continued)
As with all closed-loop amplifiers, if the capacitive load becomes too large, then the phase margin will be
reduced, introducing excessive ringing and overshoot. One way of overcoming this is to place series nulling
resistors between the output and these load capacitors, see Figure 49.
BUF11702
LCD Source Driver
OUT1
GMA
OUT2
GMA
OUT3
GMA
OUT4
GMA
OUT5
GMA
OUT6
GMA
OUT7
GMA
OUT8
GMA
OUT9
GMA
OUT10
GMA1
Positive Polarity
Negative Polarity
Figure 49. BUF11702 Driving a LCD Source Driver With Series Nulling Resistors
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
common buffer (VCOM)
The common buffer output of the BUF11702 has a greater output drive capability than buffers 1–10, to meet the
heavier current demands of driving the common node of the LCD panel. It was also designed to drive heavier
capacitive loads and still remain stable, see Figure 50.
45
VDD = 10 V
RL = 2 kΩ
40
Phase Shift – Deg
35
30
25
20
15
10
5
0
10
100
CL – Load Capacitance – pF
1000
Figure 50. Phase Shift Between Output and Input vs Load Capacitance for Common Buffer
Because the common node of the panel acts like a large capacitor, the common output of the BUF11702 will
have to supply very large pulses of current. In some applications the output drive capability of the BUF11702
might not be sufficient. Therefore discrete amplifiers with high output current drive capability and enough phase
margin to drive large capacitive loads could be used.
Possible alternatives include the OPA551, OPA350, BUF634, TLC081 or TLV4110/1. Because of their wide
bandwidth and the low frequency pole created by the LCD panel common node capacitance, extra
compensation may be required.
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
general PowerPAD design considerations
The BUF11702 is available in the thermally enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 51(a) and Figure 51(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 51(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 51. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
Y mils x Z mils with 18 vias
(Via diameter = 13 mils)
Figure 52. PowerPAD PCB Etch and Via Pattern
22
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
1. Prepare the PCB with a top side etch pattern as shown in Figure 52. There should be etching for the leads
as well as etch for the thermal pad.
2. Place eighteen holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them
small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the BUF11702 IC. These additional vias may be larger than the
13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal
pad area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the BUF11702 PowerPAD package should make their connection to the internal ground
plane with a complete connection around the entire circumference of the plated-through hole.
6. The topside solder mask should leave the terminals of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the BUF11702 IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
ǒ Ǔ
For a given θJA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula:
P
Where:
+
D
T
–T
MAX A
q JA
PD = Maximum power dissipation of BUF11702 IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case (0.72°C/W)
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
8
θJA = 27.9°C/W
2 oz. Trace and Copper
Pad With Solder
Maximum Power Dissipation – W
7
6
TJ = 150°C
5
4
3
2
1
0
–40
–20
0
20
40
60
80
100
TA – Free-Air Temperature – °C
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
This lower thermal resistance enables the BUF11702 to deliver maximum output currents even at high ambient
temperatures.
24
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
BUF11702 evaluation module (SLOP356)
The BUF11702 has an evaluation module where it can be mounted along with reference resistors and load
capacitors. This enables the BUF11702 to be used in its own daughterboard in existing designs for easy
evaluation. The schematic of the BUF11702 EVM is shown below. Note that the EVM has been configured for
single supply use. As such, all decoupling capacitors are connected to the ground plane of the EVM, as are the
ground terminals of the BUF11702.
J2
J3
JP3
GND
GND
VREF
INCOM
GND
INCOM
R11
CH10
R21
R10
OUT9
IN9
R9
IN8
CH8
OUT8
R8
CH7
IN7
R7
CH6
OUT7
BUF11702
IN6
OUT4
IN4
R4
R19
IN2
R18
R17
C13
C12
R26
CH7
R27
CH6
C11
R28
R15
C10
CH5
R29
CH4
C9
R30
C8
CH3
R31
OUT2
R12
IN1
C7
OUT1
C6
R1
NC
C4
GND
VDD2
CH1
VDD
VDD
JP2
CH2
R32
GND
NC
VDD
C2
R25
CH8
R13
R2
C3
C14
OUT3
R3
CH1
R24
CH9
R14
IN3
CH2
R20
C15
OUT5
R5
CH3
CH10
R16
IN5
CH4
R23
OUT6
R6
CH5
C16
OUT10
IN10
CH9
OUTCOM
R22
OUTCOM
JP1
J1
VDD
C1
Figure 54. BUF11702 Evaluation Module Schematic
In populated versions of the EVM, capacitors C1 to C4 have been included. Capacitors C1 and C2 are bulk
decoupling capacitors of 6.8 µF while capacitors C3 and C4 are 100 nF ceramic high frequency decoupling
capacitors. Resistors R1 to R32 and capacitors C5 to C16 have not been included and are application specific.
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BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
APPLICATION INFORMATION
reference voltages
The reference voltages can be supplied externally via the connector J2 (not included) or generated onboard via
resistors R1 to R11. Provision on the board for an external low side reference has been included so that the negative references can be referred to a voltage other than ground.
The reference ladder can be referred to either VDD (master supply voltage) or a secondary voltage, VDD2. This
allows a low noise or absolute reference voltage to be used for the LCD source driver’s DACs other than the
system voltage. If the secondary voltage is used, then jumper JP1 should be left open and jumper JP2 shorted. If
a ratiometric reference (proportional to the master supply voltage) is to be used, then jumper JP1 and JP2
should be shorted, feeding VDD through to the reference ladder.
output
The outputs of the BUF11702 are fed to connector J3 (not mounted). This enables the output voltages to be
monitored directly on the EVM or fed off-board for evaluation in a real system.
Onboard load resistors, R23 to R32, connected to ground can also be mounted. These can be used to simulate
resistive loading of the LCD source driver.
Transient improving capacitors are frequently used in LCD panel applications, and so pads to mount these transient improving capacitors, C6 to C16, have been included. Due to the possible magnitude of these capacitors,
pads have been placed between the output of the BUF11702 and these capacitors to mount nulling resistors,
R12 to R22. If the nulling resistors are not required, shorts could be placed instead of resistors.
The pads for R1 to R32 and capacitors C3 to C16 have been laid out to support 0805 or 1206 size components.
PowerPAD
The EVM has been laid out to support the PowerPAD feature of the BUF11702. An area is provided on the EVM,
under the BUF11702, for the exposed leadframe to be connected to. Eighteen vias are connected to the ground
plane of the EVM to reduce the thermal case to ambient resistance, θCA, significantly. See applications section
on general PowerPAD design considerations.
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
BUF11702
10+1-CHANNEL LCD GAMMA CORRECTION BUFFER
SLOS359B – MARCH 2001 – REVISED OCTOBER 2001
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
0,65
20
0,10 M
11
Thermal Pad
(See Note D)
4,50
4,30
0,15 NOM
6,60
6,20
Gage Plane
1
10
0,25
A
0°– 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
4073225/F 10/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
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