REV 1.0 2002/04/28 BW0406X Sigma-Delta voice CODEC Sigma-Delta Voice CODEC BW0406X GENERAL DESCRIPTION FEATURES The BW0406X is Sigma-Delta CODEC for speech and telephony applications. The product contains both digital IIR/FIR filter and smoothing filter. The normal input and output channels have µ/A law format with 38dB signal to distortion ratio. The input and output of this device is compressed form(A-law, µ-law) and 14bit linear which can be easily determined by control select pins An on-chip voltage reference circuit is included to allow the single supply operation - Single chip voice line Codec (A/D, D/A converter included) - Oversampled Sigma Delta modulator/ Demodulator - Input/Output format : 8bit µ-law/A-law and linear 14bit * These three types are easily selectible by control pins * When serial interface mode, the 14bit linear data has 16bit format with two don't care bits from LSB - Sigma Delta ADC. * 256X Oversampling * On chip Decimation Filter * On chip Smoothing Filter - Sigma Delta DAC. * 256X Oversampling * On chip 256X Interpolation Filter * On chip Analog Post Filter - Single ended Input and Output. - Sampling Rate of 8~11KHz - On chip voltage reference circuitry - Single +3.3V Power Supply - 2Vpp In, Output signal swing - Power Consumption * Operating Mode : 10mW Typ(3.3V) * Powerdown Mode : 33µW Typ(3.3V) TYPICAL APPLICATIONS - Speech Processing (Recognition, Synthesis, Compression etc.) - Telephony - Modem FUNCTIONAL BLOCK DIAGRAM WITH INPUT/OUPUT APPLICATION ALOOP MUTE TPOST TDECI REFH REFL SINPO<1:0> SDECI<1:0> DAPWD AINFB Analog Input Voltage Reference Output - + AMODIN VREFOUT Analog ∆Σ Modulator Decimation filter Serial Interface 1. 14bit Linear PCM in 16bit format 2. µ-law 3. A-law SDOUT ADC Serial Output SDIN DAC Serial Interface Voltage Reference APOSTOUT Analog Postfilter Analog Output Digital ∆Σ Modulator Interpolation filter DADS LCS Differential to Single circuit + Smoothing filter Selectible powerdown circuit CPSEL X256FS BCK SYNC SEC ASIC SAMSUNG ELECTRONICS Co. LTD RST VDDD 1/14 VSSD VDDA VSSA ADPWD DAPWD ANALOG BW0406X Sigma-Delta voice CODEC CORE PIN DESCRIPTION PIN No. NAME I/O I/O PAD TYPE 20 VDDA AP vdda Analog Power (+3.3V) 17 VSSA AG vssa Analog Ground (0.0V) 26 REFH AP piar50_bb Analog Reference Power(+3.3V) 25 REFL AG piar50_bb Analog Reference Ground (0.0V) 15 AMODIN AI piar50_bb ADC Analog input 28 MUTE DI picc_bb Analog Mute select (High active) 9 ALOOP DI picc_bb Analog loop back select (High active) 18 VREFOUT AO poar50_bb Vref output 14 AINFB AB poar50_bb Analog Input Gain control 23 APOSTOUT AO poa_bb DAC Analog output 40 ADPWD DI picc_bb Power Down1 (High active) 39 DAPWD DI picc_bb Power Down2 (High active) 38 RST DI picc_bb Digital Reset (High active) 43 X256FS DI picc_bb 256*Sampling Freq.(FS) Clock 46 SYNC DI picc_bb Sampling Freq.(FS) Clock 1,2 SDECI<1:0> DI picc_bb ADC Digital Filter input select 7 TDECI DI picc_bb ADC Digital Filter Test input 35,36 SINPO<1:0> DI picc_bb DAC Post Filter input select 37 SDIN DI picc_bb Serial Data Input 30 TPOST DI picc_bb DAC Post Filter Test input 44 LCS DI picc_bb Linear/Compand data select (Low/High) 45 CPSEL DI picc_bb µ-law/A-law select (Low/High) 4 VSSD DG vssd Digital Ground 3 VDDD DP vddd Digital Power Supply 48 SDOUT DO pot2_bb Serial Data Output 47 BCK DI picc_bb Bit Clock 29 DADS DO pot2_bb DAC Modulator output PIN DESCRIPTION I/O TYPE ABBR. - AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional AP : Analog Power AG : Analog Ground DP : Digital Power DG : Digital Ground NOTES 1. This pin description is not fixed, but recommended. 2. The Power pin(VDDA,VDDD) must be connected by DIODE_SLOT2. 3. The Ground pin (VSSA, VSSD) must be connected bye DIODE_SLOT2. 4. SDECI<1:0>, TDECI -> Decimation Filter Block test pin. 5. SINPO<1:0>, TPOST -> Post Filter Block test pin. 6. To operate the power down mode, the two control select pins, ADPWD and DAPWD must be activated simultaneously. SEC ASIC 2/14 ANALOG BW0406X Sigma-Delta voice CODEC CORE CONFIGURATION RST SYNC TPOST DADS TDECI SDOUT DAPWD ADPWD LCS CPSEL VREFOUT SDIN APOSTOUT X256FS bw0406x ALOOP MUTE SINPO<1:0> SDECI<1:0> VDDD BCK VSSD AINFB VDDA AMODIN VSSA REFH REFL SEC ASIC 3/14 ANALOG BW0406X Sigma-Delta voice CODEC ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit VDDD -0.3 to 3.8 V Digital Input Voltage DIN -0.3 to 3.8 V Storage Temperature Range Tstg -40 to 125 °C Operating Temperature Range Topr 0 to 70 °C Supply Voltage NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operations under any of these conditions is not implied. 2. All voltages are measured with respect to VSS(VSSA or VSSD) unless otherwise specified. RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit Supply Voltage VDDA • VSSA VDDD • VSSD 3.15 3.3 3.45 V Supply Voltage Difference VDDA • VDDD 0.1 0.0 0.1 V Digital Input Voltage Range 2.7 3.3 3.6 V Analog Input Voltage Range − 2 − Vpp Characteristics NOTES It is strongly recommended that all the supply pins (VDDA, VDDD) be powered from the same source to avoid power latch up. CONTROL CLOCK CHARACTERISTICS Characteristics Min Typ Max Unit Conditions 1.843 2.048 2.816 MHz Fs=8KHz Minimum Pulse Width Low Minimum Pulse Width High 390 390 − 160 160 ns ns SYNC Frequency(Fs clock) − 8 - KHz Duty Cycle 40 − 60 % X256FS SEC ASIC Symbol 4/14 ANALOG BW0406X Sigma-Delta voice CODEC AC ELECTRICAL CHARACTERISTICS (Measurement Bandwidth is 20Hz-4KHz. Full scale input sine wave 1KHz, FS=8KHz, @VDDA=3.3V, Ta=25°C,,Unless otherwise specified.) Characteristics Symbol Min Typ Max Unit Resolution - 14 - Bits Sampling rate - 8 - KHz Conditions - ADC Analog Input Characteristics * Signal to Distortion Ratio 35 38 - dB 0dB Input : µ/A Law compand 70 75 - dB 0dB Input : Linear - dB 28 29.5 29 23 -40dB Input : µ-Law compand -40dB Input : A-Law compand 25 24 - dB -45dB Input : µ-Law compand -45dB Input : A-Law compand Offset Error - - ±20 mV - Input Voltage Range - 2 - Vpp - DAC Analog Input Characteristics 35 38 - dB 70 75 - dB 30 33.5 - dB 29 32 25 30 24 27 Offset Error - Output Voltage Range - * Signal to Distortion Ratio 0dB Input : µ/A Law compand 0dB Input : Linear -40dB Input : µ-Law compand -40dB Input : A-Law compand -45dB Input : µ-Law compand - dB - ±20 mV - 2 - Vp--p - -45dB Input : A-Law compand Digital Filter Specification Passband 0 Passband Ripple Stopband 0.4 +/-0.25 0.4 Stopband Attenuation Fs dB 0.6375 -40 Fs dB Power Supply Power comsumption (3.3v Operating Mode) Analog Digital - 2.5 0.5 3 0.7 mA Power comsumption (3.3v Powerdown Mode) - 10 - µA SEC ASIC 5/14 - ANALOG BW0406X Sigma-Delta voice CODEC CORE LAYOUT GUIDE N-WELL Guardring P+ Guardring VDDD VSSD VBB DIGITAL BLOCK Analog Input ANALOG BLOCK VSSA VBB Guardring Analog Output VDDA NOTE 1. The layout of bw0406x consists of digital part and analog part. The digital part and the analog part must be divided. 2. The substrate of digital and analog part is seperated from digital and analog ground so that it can minimize noise through substrate. 3. It is recommended that you use thick analog power metal. when connecting to PAD, and the path should be kept as short as possible. 4. Digital power and analog power are used separately. 5. When the core block is connected to other blocks, it must be double guardring using N-well and P+active to remove the substrate and coupling noise. In that case, the power metal should be connected to PAD directly. 6. Digital input signal lines must be same length to reduce the difference of delay. SEC ASIC 6/14 ANALOG BW0406X Sigma-Delta voice CODEC CORE EVALUATION GUIDE VSSD VDDD C3 + C4 MUTE ALOOP ADPWD C3 RST VDDA + C4 X256FS VSSA SYNC 2 Analog Input - + R1 R2 Analog Output R3 C2 BW0406X AMODIN C1 AINFB SDECI<1:0> TDECI DAPWD APOSTOUT 2 SINPO<1:0> VREFOUT DSP Controller SDIN + C6 REFH TPOST C5 REFL + C3 LCS CPSEL C4 SDOUT DADS BCK LOCATION DESCRIPTION C3 0.1µF TANTALUM CAPACITOR C4, C6 10µF CERAMIC CAPACITOR C1 0.33µF TANTALUM CAPACITOR C2 75pF CERAMIC CAPACITOR R1, R2 50kΩ RESISTOR R3 200kΩ RESISTOR C5 0.1µF TANTALUM CAPACITOR <The Connection User Guide Line for Embedded Core Test> NOTES 1. If SDOUT is externally shorted with SDIN, The CODEC is achieved to loop-back test mode(ADC->DAC). 2. If end users want to test CODEC in integrated chip, The above pin must be extracted to the PAD(pin 14). 3. The analog power/ground must be separated from digital power/ground. 4. CPSEL = 1 ;A-law select, 0 ;µ-law select 5. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively. 6. Power typical value : VDDA = VDDD = 3.3V, VSSA = VSSD = 0.0V SEC ASIC 7 /14 ANALOG BW0406X Sigma-Delta voice CODEC PACKAGE CONFIGURATION Ct + Cc 22 40 ADPWD NC21 21 41 NC41 VDDA 20 42 NC42 NC19 19 43 X256FS VREFOUT 18 44 LCS VSSA 17 45 CPSEL NC16 16 46 SYNC AMODIN 15 47 BCK 48 SDOUT TDECI NC8 3 4 5 6 7 8 9 NC11 NC6 2 NC10 NC5 1 ALOOP VSSD BW0406X 10 11 12 AINFB 14 NC13 13 3.3V NC22 NC12 DAPWD L REFL REFH NC27 DADS MUTE TPOST NC31 NC32 23 VDDD 39 VSSP APOSTOUT SDECI<0> RST VDDP 24 SDECI<1> 38 SINPO<0> NC24 Ct + SDIN Cc 37 SINPO<1> 36 35 34 33 32 31 30 29 28 27 26 25 L + Ct Cc LOCATION DESCRIPTION Ct 0.1µF TANTALUM CAPACITOR Cc 10µF CERAMIC CAPACITOR L FERRITE BEAD (0.1mH) SEC ASIC 8 /14 ANALOG BW0406X Sigma-Delta voice CODEC CONTROL CLOCKS CHARACTERISTICS Characteristics Symbol Min Typ Max Unit X256FS Frequency Fmck - 2.048 - MHz BCK Frequency Fbck - 128 - KHz SYNC Frequency Fsync - 8 - KHz X256FS Duty cycle (H:L) MCDuty 40:60 50:50 60:40 % BCK Duty cycle (H:L) BCDuty 40:60 50:50 60:40 % SYNC Duty cycle (H:L) SYDuty 40:60 50:50 60:40 % X256FS Falling and BCK Edge Delay(Hold) Tdbck 5 10 15 ns X256FS Falling and SYNC Edge Delay(Hold) Tdsync 5 10 15 ns BCK Falling and SDOUT Delay Tdsdout 5 10 15 ns BCK Rising and SDIN Setup Tsetup 10 15 20 ns BCK Rising and SDIN Hold Thold 10 15 20 ns X256FS 0.5 VDDD BCK 1/Fmck SYNC 0.5 VDDD 1/Fbck 0.5 VDDD X256FS 1/Fsync 0.5 VDDD "H" "L" MCDuty 0.5 VDDD BCK "H" "L" SYNC 0.5 VDDD BCDuty "H" "L" SYDuty BCK 0.5 VDDD SYNC 0.5 VDDD X256FS 0.5 VDDD X256FS 0.5 VDDD Tdsync Tdbck Thold SDOUT 0.5 VDDD SDIN 0.5 VDDD BCK 0.5 VDDD BCK 0.5 VDDD Tsetup Tdsdout *Notes : BCK rising edge must NOT occur at the same time as SYNC edge. SEC ASIC 9 /14 ANALOG BW0406X Sigma-Delta voice CODEC TIMING DIAGRAM The frame of sync clock(SYNC) transitions determine the start of the serial data. Input data * All input data are clocked in by the falling edge of BCK. * 14bit, 2's complement or 8bit A-law, µ-law data format. Output data *All output data are clocked out by the falling edge of BCK. * 14bit, 2's complement or 8bit A-law, µ-law data format. Notes 1. SYNC clock is at sampling frequency, Fs 2. 14bit linear data has 16bit serial data format, this is accomplished by 16FS ( = Fs clock x 16 ) and two don't care bits are added from LSB, to fit into 16bit format. Fs Clock SYNC 16Fs 13 12 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X SDOUT[ADC output](Linear data) 13 ; MSB, 0 ; LSB 7 6 7 ; MSB, 0 ; LSB 5 4 3 2 1 0 X SDOUT[ADC output](Compressed data) 13 12 13 ; MSB, 0 ; LSB 11 10 9 8 7 6 X : Non-valid data (0 insetion) X : Non-valid data (0 insetion) 5 4 3 2 1 0 X X X : Don't care data X X X X X X X X X : Don't care data SDIN [DAC input](Linear data) 7 7 ; MSB, 0 ; LSB 11 BCK 6 5 4 3 2 1 0 SDIN [DAC input](Compressed data) Codec serial interface timing diagram Fs SYNC 16Fs BCK 256Fs X256FS Codec clock interface timing diagram SEC ASIC 10/14 ANALOG BW0406X Sigma-Delta voice CODEC INPUT/OUTPUT APPLICATION GUIDE 1. Input stage application guide R1 AINFB R1 C1 - + AMODIN Analog Input + Typical value of R1 and C1 R1 > 50KΩ C1 = 0.33µF 2. Output stage application guide R3 Speaker Driver Amp APOSTOUT C2 Ground How to determine the value of R3 and C2. C2 = 1.5*10-5/R3 For example : If you choose R3 as 200KΩ, then the value of C3 is 75pF. 3. VREFOUT port application guide VREFOUT C1 C2 Ground C1 = 0.1µF, C2 = 10µF * Note : The user should dispose the C1 and C2 as the order shown above and dispose the capacitors to VREFOUT pin as close as possibe. SEC ASIC 11/14 ANALOG BW0406X Sigma-Delta voice CODEC PHANTOM CELL INFORMATION REFL REFH DADS DADS TPOST SINPO[0] SINPO[1] VDDA:P VDDA:P VDDA:P VDDA:P SDIN RST MUTE DAPWD APOSTOUT ADPWD bw0406x X256FS VREFOUT: LCD VREFOUT: CPSEL VREFOUT: SYNC VSSAG: BCK VSSA:G SDOUT VSSAG: AMODIN 12/14 AINFB ALOOP TDECI SDECI[0] VSSD:G VSSD:G VSSD:G SDECI[1] SDECI[1] VDDD:P VDDD:P VDDD:P SEC ASIC VSSA:G VSSA:G ANALOG BW0406X Sigma-Delta voice CODEC LAYOUT GUIDE ANALOG POWER:P ANALOG POWER:P ANALOG POWER:P PAD ANALOG POWER:P ANALOG GROUND:G PAD ANALOG GROUND:G ANALOG GROUND:G ANALOG GROUND:G SAME NAME PORT: SAME NAME PORT: SAME NAME PORT: SAME NAME PORT: Correct Examples : Each Same Name Port Should be Connected to PAD, Respectively. PAD ANALOG POWER:P ANALOG GROUND:G ANALOG GROUND:G ANALOG POWER:P PAD SAME NAME PORT: PAD PAD SAME NAME PORT: Wrong Examples : Each Same Name Port Merged together around GDS, and connected to together to PAD Analog Pads should be Placed as short as possible To GDS Analog Ports Digital Ports At least 50um Space recommended Digital Logics At least 50um Space recommended SEC ASIC • Digital Lines should not cross Analog lines 13/14 ANALOG BW0406X Sigma-Delta voice CODEC FEEDBACK REQUEST It should be quite helpful to our CODEC core development if you specify your system requirements on CODEC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. - Could you explain external/internal pin configurations as required? Specially requested function list : 1. What is your signal band to use, 3.6KHz? 4KHz? or 4.8KHz? 2. What is your analog in/output signal voltage swing? and what kind of format do your want as analog signal in/ouput: single or differential format? If you can, Please let us know, what is your exact in/output signal spec. 3. What is your minimum S/N+D spec? 4. Do you want linear phase characteristic or you don't care on digital filter spec? 5. Could you give us exact design spec of speech codec? (For example, A-law, µ-law and so on.) REVISION HISTORY Modified Items Version Date Ver 0.1 01.02.24 - p7 : Package Configuration has been changed - p9 : Two typos have been corrected Ver 1.0 02.04.28 - p5 : Digital Filter Characteristics added - p13 : Phantom Cell Information added - p14 : Layout Guide added SEC ASIC 14/14 Comments ANALOG