ETC C12C

1.2 Micron CMOS Process Family
Process parameters
Features
• Double Poly / Double Metal,
• 2.4 µm Poly and Metal I Pitch,
• 5.5 Volts Maximum Operating Voltage,
• Twin-tub process on P-type or N-type wafers,
• ProToDuctionTM Option for low cost prototypes,
• Triple Metal option available,
.• Low leakage process
• Standard cell library available
Description
The 1.2µm process provides flexibility,
speed and packing density needed in mixed signal
designs. The aggressive design rules on both metal
layers are comparable to most 0.8µm processes.
Also, the overall design rules are compatible with
most other 1.2um processes making second
sourcing easy.
1.2µm
5volts
Units
Metal I or II pitch (width/space)
1.2 / 1.2
µm
Metal III pitch (width/space)
5.0 / 5.0
µm
Poly pitch (width/space)
1.2 / 1.2
µm
Contact
1.2 x 1.2
µm
Via 1 & 2
1.4 x 1.4
µm
Gate geometry
1.2
µm
N-well junction depth
4.0
µm
P-well junction depth
4.0
µm
N+ junction depth
0.20
µm
P+ junction depth
0.31
µm
Gate oxide thickness
225
Å
Inter poly oxide thickness
390
Å
MOSFET Electrical Parameters
1.2 MICRON - 5 volts
Technology outline
• Drain Engineered Structure to Ensure
Reliability against Hot-Carrier Injection
• Planarization with non-etch-back
SOG Processes
N Channel
P Channel
min. typ. max. min. typ. max.
Vt (10x1.2µm)
0.55
0.70
0.85
0.55
0.70
0.85
Units
Conditions
V
saturation
Vds=Vgs=5v
Ids (10x1.2µm)
220
115
µA/µm
Gain β (10x10µm)
73
24
µA/V2
0.56
0.73
√v
12
V
Ids=20nA
• State-of-the-art Metal technology :
Ti/TiN/Al/TiN sandwich
• Plasma Silicon Nitride Passivation
for Reliability against Moisture
Body Factor (50x50µm)
Subthreshold Slope
90
90
mV/dec.
Vds=0.1v
• Latchup Free Process on Non-Epi
Material Achieved
Maximum Substrate
Current (50x1.2µm)
0.20
.01
µA/µm
Vds=5.5v
Vgs=2.7v
15
V
Ids = 14µA
0.82
µm
L drawn = 1.5µm
Bvdss
Field Threshold
L Effective
www.dalsasemi.com
For More Information:
DALSA Semiconductor Sales
18 Boulevard de l’Aéroport
Bromont, Québec, Canada
J2L 1S7
10
10
15
15
10
10
1.0
Tel :
Fax
email:
(450) 534-2321 ext. 1448
(800) 718-9701
(450) 534-3201
dalsasales@dalsasemi.com
1.2 Micron CMOS Process Family [cont’d]
Resistances (Ω /sq.)
Capacitances (fF/µm2)
min.
typ.
max.
min.
typ.
Inter-poly
0.88
1.06
1.27
Nwell*
570
Gate oxide
1.4
1.5
1.6
Pwell
2300
max.
N+ Junction
0.35
N+
35
42
55
P+ Junction
0.60
P+
80
85
120
Poly gate
15
22
25
Poly capacitor
75
100
125
Bipolar gain1
80
PNP vertical
10
1 Test
0.038
Metal II
0.038
* For narrow Nwell resistor
R = (573 x width) / (width - 2.0)
typ.
NPN lateral [p- substrate]
Metal I
condition : Vce = 5 volts
FIG 2 : I-V Characteristics for a 50x1.2µm P-MOSFET
FIG 1 : I-V Characteristics for a 50x1.2µm N-MOSFET
12
-7
Vgs = 5 volts
Vgs = -5 volts
-6
10
-5
Vgs = 4 volts
Ids (mA)
6
Vgs = 3 volts
4
Vgs = -4 volts
-4
-3
Vgs = -3 volts
-2
Vgs = 2 volts
2
0
Vgs = -2 volts
-1
0
0
1
2
3
4
6
5
0
-1
-2
Vds (volts)
FIG 3 : Subthreshold Characteristics at Vds=0.1 volt for
a 50x1.2
1.2µm N-MOSFET
360
10-04
320
10-04
280
10-05
10-05
Ids (A)
200
10-08
8
10-08
120
10-11
80
10-11
10-12
40
10-12
0
10-13
Vgs (volts)
1.6
2.0
12
10
10-10
1.2
14
10-07
160
0.8
-6
10-06
10-09
0.4
-5
10-03
240
10-07
Ids (µA)
Ids (A)
10-06
0
-4
FIG 4 : Subthreshold Characteristics at Vds=-0.1 volt for
a 50x1.2µm P-MOSFET
10-03
10-13
-3
Vds (volts)
6
10-09
-8
10-10
-6
4
-4 2
-2
0
0.4
0.8
Vgs (volts)
NOTE : These values are for guidance only. Many of them can be adjusted to suit customer requirements.
For full process specifications contact a Mitel sales office or representative.
1.2
1.6
2.0
0
Ids (µA)
Ids (mA)
8