APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features Product Features • • • • • • • • • • • • Dedicated clock buffer power pins for reduced noise, crosstalk and jitter Buffer XIN Reference clock output Input clock frequency 33.3 MHz Reference may be a clock or a crystal Output frequencies of 33.3, 66.6, 100 and 133.3 MHz selectable (PCIX requirements) Output grouped in two banks of 5 clocks each. SMBus clock control interface for individual clock disabling, SSCG control and individual bank frequency selection Output clock duty cycle is 50% (± 5%) <250 pS skew between output clocks within a bank Output jitter <250 pSec. (175pSec with all outputs at the same frequency) Spread Spectrum feature for reduced EMI OE pins for separate output bank enable control and testability 48 Pin SSOP and TSSOP package Block Diagram AGOOD# SSCG# CLKA0 SSCG Logic /N CLKA1 1 0 XIN XOUT 0 SDATA SCLK IA(0:2) SA(0,1) SB(0,1) /N I 2C Control Logic 1 Test Mode Logic Table INPUT PINS OEA OEB HIGH HIGH HIGH HIGH LOW SA1 SB1 LOW LOW HIGH HIGH X OUTPUT PINS SA0 SB0 LOW HIGH LOW HIGH X CLKA(0:4) CLKB(0:4) XIN 2 * XIN 3 * XIN 4 * XIN Tri-State REF XIN XIN XIN XIN Tri-State Note: A and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device’s XIN pin. OEA or OEB will tristate REF. Pin Configuration REF 1 48 SDATA VDD 2 47 SCLK XIN 3 46 VDD XOUT 4 45 VSS VSS 5 44 VDD SA0 6 SA1 7 43 42 SB1 SB0 VSS 8 41 VSS CLKA0 9 40 CLKB0 CLKA1 10 39 CLKB1 VDDA 11 CLKA2 12 C9530 • 38 VDDB 37 CLKB2 VSS 13 36 VSS VDDA 14 35 VDDB CLKA3 15 34 CLKB3 CLKA4 16 33 CLKB4 VSS 17 32 VSS AGOOD# 18 31 BGOOD# CLKB1 CLKB2 VSS 19 30 AVDD IA0 20 29 AVDD IA1 21 28 VSS CLKB3 CLKB4 OEB BGOOD# REF IA2 22 27 SSCG# AVDD 23 26 VSS OEA 24 25 OEB CLKA2 CLKA3 CLKA4 OEA CLKB0 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07033 Rev. ** 5/1/2000 Page 1 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features Pin Description Pin No. 3 Pin Name XIN PWR VDDA I/O I 4 XOUT VDDA O 1 REF VDD O 24* OEA VDD I 25* OEB VDD I 18 AGOOD# VDD O 31 BGOOD# VDD O 6*, 7* SA(0,1) VDD I 43*, 42* SB(0,1) VDD I 20*, 21*, 22* 27* IA(0:2) SSCG# VDD VDD I I 48 47 11, 14 38, 35 2, 44, 46 23, 29, 30 SDATA SCLK VDDA VDDB VDD AVDD VDD VDD - I/O I PWR PWR PWR PWR CLKA (0:4) CLKB (0:4) VSS VDDA O VDDB O - PWR 9, 10, 12, 15, 16 40, 39, 37, 34, 33 5, 8, 13, 17, 19, 26, 28, 32, 36, 41, 45 Description Crystal Buffer input pin. Connects to a crystal, or an external clock source. Serves as input clock TCLK, in Test mode. Crystal Buffer output pin. Connects to a crystal only. When a Can Oscillator is used or in Test mode, this pin is kept unconnected. Buffered inverted outputs of the signal applied at Xin, typically 33.33 MHz Output Enable for clock bank A. Causes the CLKA (0:4) output clocks to be in a Tri-state condition when driven to a logic low level. Output Enable for clock bank B. Causes the CLKB (0:4) output clocks to be in a Tri-state condition when driven to a logic low level. When this output signal is a logic low level, it indicates that the output clocks of the A bank are locked to the input reference clock. This output is latched. When this output signal is at a logic low level, it indicates that the output clocks of the B bank are locked to the input reference clock. This output is latched. Clock Bank A selection bits. These control the clock frequency that will be present on the outputs of the A bank of buffers. See table on page one for frequency codes and selection values. Clock Bank B selection bits. These control the clock frequency that will be present on the outputs of the B bank of buffers. See table on page one for frequency codes and selection values. SMBus address selection input pins. See SMBus Address table. Enables Spread Spectrum clock modulation when at a logic low level, see pg. 3. Data for the internal SMBus circuitry. See pg 4. Clock for the internal SMBus circuitry. See pg. 4 3.3V common power supply pin for Bank A PCI clocks CLKA (0:4). 3.3V common power supply pin for Bank B PCI clocks CLKB (0:4). Power supply for internal Core logic. Power for internal analog circuitry. This supply should have a separately decoupled current source from VDD. A bank of Five 33.3, 66.6, 100.0 or 133.3 MHz output clocks (1x, 2x, 3x and 4x Xin clock). A bank of Five 33.3, 66.6, 100.0 or 133.3 MHz output clocks (1x, 2x, 3x, and 4x Xin clock). Ground pins for the device Notes: Pin numbers ending with a * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is connected to them. A bypass capacitor (0.1 µF) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins, their high frequency filtering characteristic will be canceled by the lead inductance of the trace. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s). Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07033 Rev. ** 5/1/2000 Page 2 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features Spectrum Spread Clocking Down Spread Description Spread Spectrum is a modulation technique for distributing clock period over a certain bandwidth (called Spread Bandwidth). This technique allows the distribution of the undesirable electromagnetic energy (EMI) over a wide range of frequencies therefore reducing the average radiated energy present at any frequency over a given time period. As the spread is specified as a percentage of the resting (non-spread) frequency value, it is effective at the fundamental and, to a greater extent, at all it's harmonics. In this device, Spread Spectrum is enabled externally through pin 27 (SSCG#) or internally via SMBus Byte 0 Bit 0 and 6. Spread spectrum is enabled externally when the SSCG# pin is low. This pin has an internal device pull up resistor, which causes its state to default to a high (Spread Spectrum disabled) unless externally forced to a low. It may also be enabled by programming SMBus Byte 0 Bit 0 LOW (to enable SMBus control of the function) and then programming SMBus Byte 0 Bit 6 LOW to set the feature active. Spread off Spread on Center Frequency, Spread on Center Frequency, Spread off Spectrum Spreading Selection Table Output clock Frequency % OF FREQUENCY SPREADING SMBus Byte 0 Bit 5 =0 SMBus Byte 0 Bit 5 =1 MODE 33.3 MHz (XIN) 1.0% (-1.0% + 0%) 0.5% (-0.5% + 0%) Down Spread 66.6 MHz (XIN*2) 1.0% (-1.0% + 0%) 0.5% (-0.5% + 0%) Down Spread 100.0 MHz (XIN*3) 1.0% (-1.0% + 0%) 0.5% (-0.5% + 0%) Down Spread 133.3 MHz (XIN*4) 1.0% (-1.0% + 0%) 0.5% (-0.5% + 0%) Down Spread When SSCG is enabled, the device will down spread the clock over a range that is 1% of its resting frequency. This means that for a 100 MHz output clock the frequency will sweep through a spectral range from 99 to 100 MHz. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07033 Rev. ** 5/1/2000 Page 3 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features 2-Wire SMBus Control Interface The 2-wire control interface implements a write slave only interface according to SMBus specification. The device can be read back. Sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported. Through the use of the IA0, IA1, and IA2 pins the SMBus address of the device may be changed so that multiple devices may reside on a single SMBus control signaling bus and not interfere with each other. SMBus Address Selection Table SMBus address of the device IA0 BIT (Pin 20) IA1 BIT (Pin 21) IA2 BIT (Pin 22) DE 0 0 0 DC 1 0 0 DA 0 1 0 D8 1 1 0 D6 0 0 1 D4 1 0 1 D0 0 1 1 D2 1 1 1 During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledgement is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode. The device will respond to writes to 10 bytes (max) of data to its selected address by generating the acknowledge (low) signal on the SDATA wire following reception of each byte. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07033 Rev. ** 5/1/2000 Page 4 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features Transmit Receive 1 1 0 1 0 0 1 ACK 0 ACK BYTE COUNT COMMAND BYTE (Don't Care) SDATA MSB (Don't Care) 8 8 START CONDITION ACK BYTE 0 BYTE N (Valid) (Valid) 1 0 1 8 8 STOP CONDITION Fig.5a (WRITE) Transmit 1 ACK LSB SCLK Receiv ACK 0 0 1 ACK BYTE COUNT ACK 1 (Valid) SDATA MSB BYTE1 BYTE 0 ACK BYTE N ACK (Valid) (Valid) 8 8 ACK (Valid) LSB 8 SCLK START CONDITION 8 STOP CONDITION Fig.5b (READ) Fig.5 Serial Control Registers NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true power up. Bytes are set to the values shown initially only after true power up condition occurs. Following the acknowledge of the Address Byte , two additional bytes must be sent: 1) “Command Code “ byte, and 2) “Byte Count” byte. 3) Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged. Byte 0: Function Select Register Bit 7 6 5 4 3 2 1 0 @Pup 1 0 1 0 0 0 0 1 Pin# 27 42 43 7 6 - Description Test Mode Enable. 1=normal operation, 0 = Test mode Spread Spectrum modulation control bit (effective only when Bit 0 of this register is set to a 0) 0=OFF, 1 = ON SSCG Spread width select. 1=0.5%, 0=1.0% See table below for clarification SB1 Bank B MSB frequency control bit (effective only when Bit 0 of this register is set to a 0) SB0 Bank B LSB frequency control bit (effective only when Bit 0 of this register is set to a 0) SA1 Bank A MSB frequency control bit (effective only when Bit 0 of this register is set to a 0) SA0 Bank A LSB frequency control bit (effective only when Bit 0 of this register is set to a 0) Hardware/SMBus frequency control. 1=Hardware (pins 6, 7, 42, 43, and 27), 0=SMBus Byte 0 bits 1-4 and 6 Clarification Table for Byte0, bit5 Byte 0, bit6 0 0 1 1 Byte0, bit5 0 1 0 1 Description Frequency generated from second PLL Frequency generated from XIN Spread @ -1.0% Spread @ -0.5% Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07033 Rev. ** 5/1/2000 Page 5 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features Test Table These output frequencies will be present when SMBus byte 0 bit 7 has been set to a logic 0 state. Test Function Clock Frequency CLKA(0:4) XIN/6 Outputs CLKB(0:4) XIN/4 REF XIN Table 3 Notes: 1. XIN is the frequency of the clock that is present on the XIN input during test mode. Byte 1: A Bank and REF Clock Control Register (1 = Enable, 0 = Stopped at a low level) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 1 16 15 12 10 9 Description Reserved Reserved REF Enable/Stopped CLKA4 Enable/Stopped CLKA3 Enable/Stopped CLKA2 Enable/Stopped CLKA1 Enable/Stopped CLKA0 Enable/Stopped Byte 2: B Bank Clock Control Register (1 = Enable, 0 = Stopped at a low level) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 33 34 37 39 40 Description Reserved Reserved Reserved CLKB4 Enable/Stopped CLKB3 Enable/Stopped CLKB2 Enable/Stopped CLKB1 Enable/Stopped CLKB0 Enable/Stopped Note: Stopping a clock indicated that the clock output is fixed in a logic low state. This effect will occur within 2 clock cycles from the time the bit is set and does so in a manner so as not to cause any short or runt clock cycles. When the stop is bit is changed from a stopped state to a running state the same (maximum 2 clock latency) delay occurs with the first cycle being full in period (for the frequency that is selected Internal Crystal Oscillator This device will operate in two input reference clock configurations. In its simplest mode a 33.33 MHz fundamental cut parallel resonant crystal is attached to the XIN and XOUT pins. In the second mode a 33.33MHz input reference clock is driven in on the XIN clock from an external source. In this application the XOUT pin must be left disconnected. Output Clock Frequency Control All of the output clocks have their frequency selected by the logic state of the S0 and S1 control bits. The source of these control signals is determined by the SMBus register Byte 0 Bit 0. At initial power up this bit is set of a logic 1 state and thus the frequency selections are controlled by the logic levels present on the devices SA(0,1) and SB(0,1) pins. If the application does not use an SMBus interface then hardware frequency selection SA(0,1), (SB(0,1) that must be used. If it is desired to control the output clocks using an SMBus interface, then this bit (Byte 0 Bit 0) must first be set to a low state. After this is done the device will use the contents of the internal SMBus register Byte 0, Bits 1,2,3 and 4) to control the output clock’s frequency. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07033 Rev. ** 5/1/2000 Page 6 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features Output Clock Tri-state Control All of the clocks in Bank A (CLKA(0:4)) and bank B (CLKB(0:4)) may be placed in a tri-state condition by bringing their relevant OE pins (OEA and OEB) to a logic low state. This transition to and from a tristate and active condition is a totally asynchronous event and clock glitching may occur during the transitioning states. This function is intended as a board level testing feature. When output clocks are being enabled and disabled in active environments the SMBus control register bits are the preferred mechanism to control these signals in an orderly and predictable manner. Both output enable pins contain internal pull-up resistors that will insure that a logic 1 (high) is maintained and sensed by the device if no external circuitry is connected to these pins. Absolute Maximum Ratings Maximum Power Supply: Storage Temperature: Operating Temperature: Maximum ESD protection 5.5 -65ºC to + 150ºC 0ºC to +70ºC 2000V Maximum Input Voltage Relative to VDD: VDD + 0.3V Maximum Input Voltage Relative to VSS: VSS - 0.3V Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD) Document#: 38-07033 Rev. ** 5/1/2000 Page 7 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features DC Parameters Characteristic Symbol Min Typ Max Units Conditions note 1 Input Low Voltage VIL1 - - 1.0 Vdc Input High Voltage VIH1 2.0 - - Vdc Input Low Voltage VIL2 - - 1.0 Vdc Input High Voltage VIH2 2.2 - - Vdc Input Low Current (@VIL = VSS) IIL -66 -5 µA Input High Current (@VIL = VDD) IIH 5 µA Tri-State leakage Current Ioz - - 10 µA Dynamic Supply Current Idd3.3V - - 300 mA note 4 Unloaded Supply Current Isdd - - 30 mA Device running, OEA and OEB at a logic low level (outputs disabled). All input pins except XIN and XOUT Input pin capacitance Cin - - 5 pF Pin inductance Lpin - - 7 nH Crystal pin capacitance Cxtal 32 34 38 pF Crystal DC Bias Voltage VBIAS 0.3Vdd Vdd/2 0.7Vdd V Crystal Startup time Txs - - 40 µS VDD = AVDD = VDDA = VDDB = 3.3V ±5%, Note1: Note2: Note3: Note4: Note5: note 2 For internal Pull up resistors, note 1 and note 3 from XIN and XOUT Pins to Ground. note 5 From Stable 3.3V power supply. TA = 0ºC to +70ºC Applicable to input signals: SA0, SA1, SB0, SB1, OEA, OEB and SSCG# Applicable to Sdata, and Sclk. Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K. All outputs load in accordance with table 1, all output buffers enabled and all OE pins at a logic 1 level. Although the device will reliably interface with crystals of a 17pF – 20pF CL range, it is optimized to interface with a typical CL = 18pF crystal specifications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07033 Rev. ** 5/1/2000 Page 8 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features AC Parameters Symbol Tcyc THIGH TLOW Tr / Tf TSKEW TCCJ Tr / Tf TCCJ tpZL, tpZH tpLZ, tpHZ tstable Parameter CLKA(0:4) CLKB(0:4) period CLKA(0:4) CLKB(0:4) period CLKA(0:4) CLKB(0:4) low time CLKA(0:4) a, CLKB(0:4)rise and fall times (Any CLK ) to (Any CLK) Skew time CLK(A:B)(0:4) Cycle to Cycle Jitter REFOUT rise and fall times REFOUT Cycle to Cycle Jitter OE to clock enable delay (all outputs) OE to clock disable delay (all outputs) All clock Stabilization from power-up 133 MHz Min Max 7.0 8.0 Output Frequency 100 MHz 66 MHz Min Max Min Max 9.5 10.5 14.5 15.5 33 MHz Min Max 25.5 30.5 Units Notes ns 1, 2, 4 3 3 - 4 4 - 6 6 - 11 11 - ns ns 2,6 2, 7 0.50 1.33 0.50 1.33 0.50 1.33 0.50 1.33 ns 2, 3 - 250 - 250 - 250 - 250 ps 2, 4, 5. 9 2, 4, 5, 10 250 or 175 (see note 10) 1.0 4.0 1.0 4.0 ps 1.0 4.0 1.0 4.0 ns ps - 10.0 - 10.0 ns 10.0 - 10.0 ns 3 - 3 ms 750 - 10.0 - 10.0 - 10.0 - 10.0 - 3 - 3 - 2, 3 2, 4 8 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: This parameter is measured as an average over 1uS duration, with an input frequency of 33.333 MHz All outputs loaded as per table 1 below. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V (see Fig.6A and Fig.6B) Probes are placed on the pins, and measurements are acquired at 1.5V. (See Figs.6A & 6B) This measurement is applicable with Spread ON or OFF. Probes are placed on the pins, and measurements are acquired at 2.4Vs, (see Figs. 6A & 6B) Probes are placed on the pins, and measurements are acquired at 0.4V. The time specified is measured from when all VDD’s reach their respective supply rail (3.3V) till the frequency output is stable and operating within the specifications Note 9: Applicable only to clocks within the same bank Note10: The cycle to cycle jitter of the device is dependent on 2 factors. They are the jitter component of the input reference clock and whether the 2 output clock banks are operating at the same frequency, When the frequency of the output banks is the same, output jitter is guaranteed to not be more than 175pSec. When the output clocks of each bank differ in frequency, the device is guaranteed to be no more than 250 pSec. Output Name REF CLK(A:B)(0:4) Max Load (in pF) 20 30 Table 1 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07033 Rev. ** 5/1/2000 Page 9 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features Test and Measurement Setup 3 . 3 V S ig n a ls tD C - - 3 .3 V Output under Test Probe 2 .4 V Load Cap 1 .5 V 0 .4 V 0V Tr Tf Fig. 6A Fig. 6B Output Buffer Characteristics Buffer Characteristics for CLKA(0:4), CLKB(0:4), and REF Characteristic Symbol Min Typ Max Units Conditions Pull-Up Current IOH1 -33 - - mA VDD-0.5 Pull-Up Current IOH2 -11 - - mA 1.2V Pull-Down Current IOL1 9.4 - - mA 0.4V Pull-Down Current IOL2 22 - - mA 1.2V VDD = AVDD = VDDA = VDDB = 3.3V ±5%, TA = 0ºC to +70ºC Suggested Oscillator Crystal Parameters Characteristic Symbol Min Typ Max Units Frequency Fo 33.0 33.33 33.5 MHz Tolerance TC - - +/-100 PPM Note 1 TS - - +/- 100 PPM Stability (TA -10 to +60C) Note 1 TA - - 5 PPM Aging (first year @ 25C) Note 1 - - - - CXTAL - 20 - Operating Mode Load Capacitance Conditions Parallel Resonant, Note 1 pF The crystal’s rated load. Note 1 40 Ohms Note 2 RESR Effective Series Resistance (ESR) Note1: For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meets or exceeds these specifications Note 2: Larger values may cause this device to exhibit oscillator startup problems To obtain the maximum accuracy, the total circuit loading capacitance should be equal to CXTAL. This loading capacitance is the effective capacitance across the crystal pins and includes the clock generating device pin capacitance (CFTG), any circuit traces (CPCB), and any onboard discrete load capacitors (CDISC). Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07033 Rev. ** 5/1/2000 Page 10 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features Suggested Oscillator Crystal Parameters (Cont.) The following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal. CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC) (CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB + CXOUTFTG + COUTDISC) Where: CXTAL CXOUTFTG CXOUTFTG CXINPCB CXOUTPCB CXINDISC CXOUTDISC = = = = = = = the load rating of the crystal the clock generators XIN pin effective device internal capacitance to ground the clock generators XOUT pin effective device internal capacitance to ground the effective capacitance to ground of the crystal to device PCB trace the effective capacitance to ground of the crystal to device PCB trace any discrete capacitance that is placed between the XIN pin and ground any discrete capacitance that is placed between the XOUT pin and ground CXINPCB CXINDISC CXOUTPCB CXOUTDISC XIN CXINFTG XOUT CXOUTFTG Clock Generator As an example, and using this formula for this datasheet’s device, a design that has no discrete loading capacitors (CDISC) and each of the crystal to device PCB traces has a capacitance (CPCB) to ground of 4pF (typical value) would calculate as: CL = (4pF + 36pF + 0pF) X (4pF + 36pF + 0pF) (4pF + 36pF + 0pF) + (4pF + 36pF + 0pF) = 40 X 40 40 + 40 = 1600 80 = 20pF Therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you should specify a parallel cut crystal that is designed to work into a load of 20pF. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07033 Rev. ** 5/1/2000 Page 11 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features Package Drawing and Dimensions 48 Pin TSSOP Outline Dimensions INCHES SYMBOL C L H E MIN a A2 MIN NOM MAX - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.031 0.039 0.041 0.80 1.00 1.05 B 0.007 - 0.011 0.17 - 0.27 C 0.004 - 0.008 0.09 - 0.20 D 0.488 0.492 0.496 12.40 12.50 12.60 E 0.236 0.240 0.244 6.00 6.10 6.20 0.02 BSC 0.50 BSC H 0.315 0.319 0.323 8.00 8.10 8.20 L 0.018 0.024 0.030 0.45 0.60 0.75 a 0º - 0º - 8º 8º A A1 B MAX A e D NOM MILLIMETERS 48 Pin SSOP Outline Dimensions e INCHES SYMBOL MIN NOM MAX MIN NOM MAX A 0.095 0.102 0.110 2.41 2.59 2.79 A1 0.008 0.012 0.016 0.203 0.305 0.406 A2 0.088 - 0.092 2.24 - 2.34 B 0.008 - 0.0135 0.203 - 0.343 C 0.005 - 0.010 0.127 - 0.254 D 0.620 0.625 0.630 15.75 15.88 16.00 E 0.291 0.295 0.299 7.39 7.49 7.60 e Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com MILLIMETERS 0.025 BSC 0.635 BSC H 0.395 - 0.420 10.03 - 10.67 L 0.020 - 0.040 0.508 - 1.016 a 0º - 0º - 8º Document#: 38-07033 Rev. ** 8º 5/1/2000 Page 12 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features Ordering Information Part Number Package Type C9530CY 48 Pin SSOP Commercial, 0°C to +70°C C9530CT 48 Pin TSSOP Commercial, 0°C to +70°C Note: Production Flow The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: CYPRESS C9530CT Date Code, Lot # C9530CT Package Y = SSOP T = TSSOP Revision Device Number Notice Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07033 Rev. ** 5/1/2000 Page 13 of 14 APPROVED PRODUCT C9530 PCIX I/O System Clock Generator With EMI Control Features Document Title: C9530 PCIX I/O System Clock Generator with EMI Control Features Document Number: 38-07033 Rev. ECN No. ** 106961 Issue Date 06/12/01 Orig. of Change IKA Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Description of Change Convert from IMI to Cypress Document#: 38-07033 Rev. ** 5/1/2000 Page 14 of 14