CB664 I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM Approved Product Product Features Product Description • • • • • • The device is a high fanout system clock buffer. Its primary application is to distribute clocks needed to support a wide range of applications such as SDRAM clocks. This device provides low skew distribution clock heavily loaded. One important application of this component is where long traces are used to transport clocks from their generating devices to their loads. The creation of EMI and the degradation of waveform rise and fall times is greatly reduces by running a single reference clock trace to this device and then using it to these devices EMI is therefore minimized and board real estate is saved. 7 output buffer for high clock fanout applications. 2 Output may be individually disabled with I C VDD = 3.3 volts Output frequency range 10 MHz to 100 MHz <250ps skew between output clocks. 16-pin SSOP and TSSOP package. Block Diagram Pin Configuration VDD I2C Control SDATA SCLK REFIN 2 SDR(0:1) 1 SDR2 2 SDR(3:4) 2 SDR(5:6) Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com VDD SDR0 SDR1 VSS CLKIN SDR2 VDD SDATA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Document#: 38-07024 Rev. ** SDR6 SDR5 VSS VDD SDR4 SDR3 VSS SCLK 5/6/99 Page 1 of 8 CB664 I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM Approved Product Pin Description Pin No. Pin Name PWR I/O Type 5 CLKIN VDD I PAD 2,3,6,11,12,15,16 SDR(0:6) VDD O BUF1 8 SDATA - I/O PAD 9 SCLK - I PAD 4,10,14 1,7,13 VSS VDD - - - Description This pin is connected to the input reference clock. This clock be in the range of 10.0 to 100.0 MHz Low Skew output clock. 2 Serial data of I C-wire control interface. Has internal pull-up resistor. 2 Serial data of I C-wire control interface. Has internal pull-up resistor COMMON Ground Power for output clock buffers and core logic Maximum Ratings Maximum Input Voltage Relative to VSS: VSS – 0.3V Maximum Input Voltage Relative to VDD: VDD + 0.3V Storage Temperature: Operating Temperature: Maximum Power Supply: o o 0 to +125 C o o 0 to +70 C 7V Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Document#: 38-07024 Rev. ** 5/6/99 Page 2 of 8 CB664 I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM Approved Product 2-Wire I2C Control Interface The 2-wire control interface implements a write only slave interface. The device control be read back. Subaddressing is not supported, thus, all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is a 7-bit address with a read /write bit as the LSB. Data is being transferred MSB first. The device respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions. Control Signal Registers Note: The pin# column lists the affected pin number where applicable. The @Pup column gives the state at true power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated. Following the acknowledge of the Address Byte (D2) two additional bytes must be sent: 1. “Command Code” byte and 2. “Byte Count” byte Although the data (bits) in these two bytes are considered “ don’t care”, they must be sent and will be acknowledge. After the Command Code and the Count bytes have been acknowledge, the below described sequence (Byte0, Byte1, Byte2…) will be valid and acknowledged. Byte 0: (1= Enable, 0= stopped) Byte 1: (1= Enable, 0= stopped) Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin # 6 3 2 - Description SDR2(Enable =1,stopped=0) Reserved Reserved Reserved SDR1(Enable =1,stopped=0) SDR0(Enable =1,stopped=0) Reserved Reserved @Pup 1 1 1 1 1 1 1 1 Pin # 16 15 12 11 - Description SDR6 (enable=1,s topped=0) SDR5 (enable=1, stopped=0 ) Reserved Reserved SDR4 (enable=1, stopped=0) SDR3 (enable=1, stopped=0) Reserved Reserved See application note AN664-01 for further reducing power consumption with I2C Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07024 Rev. ** 5/6/99 Page 3 of 8 CB664 I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM Approved Product Electrical Characteristics Characteristics Input Low Voltage Input High Voltage Input Low Current Input High Current Tri-State leakage current Dynamic Supply Current (all outputs loaded with 30 pF) Static Supply Current Short Circuit Current Input Rise Time Symbol VIL VIH IIL IIH Ioz Idd66 Idd100 Isdd Min 2.0 -66 Typ - Max 0.8 - 9 12 - - 66 10 100 140 1 Symbol TSKEW Min 45 - Typ 50 - Max 55 250 Units Vdc Vdc µA µA µA mA mA mA Conditions - Input Frequency = 66 Mhz Input Frequency =100 Mhz All outputs disabled no input clock ISC 25 mA 1 input at a time – 30 seconds VIR 2.4 nS 0.8 to 2.4 Volts VDD =VDD1 thru VDD6 = 3.3V± ±5%, TA = 0°°C to 70°°C Switching Characteristics Characteristics Output Duty Cycle Buffer Out/Out Skew all Buffer Outputs Buffer Input to Output Skew Jitter Cycle to Cycle* Jitter Absolute (Peak to Peak)* Units % pS Conditions Measured at 1.5V (50/50 in) 35 pF Load Measured at 1.5V TSKEW 2.0 0 5.0 nS TJCC 50 pS @35 pF loading TJabs 150 pS @35 pF loading VDD =VDD1 thru VDD6 = 3.3V± ±5%, TA = 0°°C to 70°°C *this jitter is additive to the input clock’s jitter Buffer Characteristics ( All Clock Outputs) Characteristics Pull-Up Current Min ull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.4V and 2.4V Rise/Fall Time Max between 0.4V and 2.4V Symbol IOHmin IOHmax IOLmin IOLmax Min - Typ - Max -54 30 54 23 Units mA mA mA mA Conditions Vout = 1.0 V Vout = 2.6 V Vout = 1.2 V Vout = 0.4 V TRFmin - - 1.33 nS 30 pF Load TRFmax - - 1.33 nS 30 pF Load VDD = VDDI thru VDD6 = 3.3V± ±5%, TA = 0°°c TO +70°°C Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07024 Rev. ** 5/6/99 Page 4 of 8 CB664 I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM Approved Product PCB Layout Suggestion Via to VDD Plane Via to GND Plane C1 C2 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 Void (Cut) in power plane FBI or R1 C3 VCC C7 6.8 to 22µF This is only a layout recommendation for best performance and lower EMI. The designer may choose a different approach but C1, C2, C3 (all are o.1µF) should always be used and placed as close to their VDD pins as is physically possible. FB1 or R1 is a ferrite Bead or resistor as needed to reduce conducted EMI from the device into the systems power circuitry. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07024 Rev. ** 5/6/99 Page 5 of 8 CB664 I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM Approved Product Package Drawing and Dimensions 16 Pin TSSOP Outline Dimensions INCHES C SYMBOL L H E a D A2 A A1 B e MIN NOM MILLIMETERS MAX MIN NOM MAX A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.031 0.039 0.041 0.80 1.00 1.05 B 0.007 - 0.012 0.19 - 0.30 C 0.004 - 0.008 0.09 - 0.20 D 0.193 0.197 0.201 4.90 5.00 5.10 E 0.169 0.173 0.177 4.30 4.40 4.50 e 0.026 BSC 0.65 BSC H 0.244 0.252 0.260 6.20 6.40 6.60 L 0.018 0.024 0.030 0.45 0.60 0.75 a 0º - 0º - 8º 8º 16 Pin SSOP Outline Dimensions INCHES SYMBOL MIN NOM MAX MIN NOM MAX A 0.068 0.073 0.078 1.73 1.86 1.99 A1 0.002 0.005 0.008 0.05 0.13 0.21 A2 0.066 0.068 0.070 1.68 1.73 1.78 B 0.010 0.012 0.015 0.25 0.30 0.38 C 0.005 0.006 0.009 0.13 0.15 0.22 D 0.239 0.244 0.249 6.07 6.20 6.33 E 0.205 0.209 0.212 5.20 5.30 5.38 e Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com MILLIMETERS 0.0256BSC 0.65 BSC H 0.301 0.307 0.311 7.65 7.80 7.90 L 0.022 0.030 0.037 0.55 0.75 0.95 a 0° 0° 4° 4° 8° Document#: 38-07024 Rev. ** 8° 5/6/99 Page 6 of 8 CB664 I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM Approved Product Ordering Information Part Number Package Type CB664ET 16 Pin TSSOP Commercial, 0ºC to +70ºC CB664EY 16 Pin SSOP Commercial, 0ºC to +70ºC Note: Production Flow The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI, YYWWW CB664ET Lot # CB664ET Package T = TSSOP Revision Device Number DISCLAIMER Cypress Semiconductor Corporation reserves the right to change or modify the information contained in this datasheet and the products described therein, without prior notice. Cypress Semiconductor Corporation does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this datasheet are provided for illustration purposes only and they vary depending upon specific applications. Cypress Semiconductor Corporation makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does Cypress Semiconductor Corporation assume any liability arising out of the application or use of any product or circuit described herein. Cypress Semiconductor Corporation does not authorize use of its products as critical components in any application in which the failure of the Cypress Semiconductor Corporation product may be expected to result in significant injury or death, including life support systems and critical medical instruments. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07024 Rev. ** 5/6/99 Page 7 of 8 CB664 I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM Approved Product Document Title: CB664 I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM Document Number: 38-07024 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109163 08/29/01 NDP Convert from IMI to Cypress Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07024 Rev. ** 5/6/99 Page 8 of 8