CCD 153A
512-Element High Speed
Linear Image Sensor
512 x 1 photosite array
µm pitch
13 µm x 13 µm photosites on 13µ
High speed: up to 20 MHz data rate
Enhanced spectral response
Low dark signal
High responsivity
On-chip clock drivers
Dynamic range typical: 5000:1
Over 1 V peak-to-peak outputs
Dark and white references contained in
sample-and-held output
The CCD153A is a 512-photoelement linear image sensor utilizing charge-coupled device technology. It is
designed for visible and very-near-IR imaging applications such as page scanning, facsimile, optical character recognition, earth-resources-satellite telescopes,
and other applications which require high resolution,
high responsivity, high data rates, and high dynamic
The CCD153A has been improved and is pin-for-pin
compatible with the CCD153 except for the deletion of
the end-of-Scan Waveform (EOSOUT). The CCD153A
has several new features which may be implemented
at the user’s option by supplying input voltages and wave
forms different than those required for standard
CCD153-type operation.
Photoelement size is 13 µm (0.51mils) x 13 µm (0.51
mils) on 13 µm (0.51 mils) centers. The devices are
manufactured using Fairchild Imaging’s advanced second-generation n-channel Isoplanar buried-channel
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
charge packets from “A” and “B” shift registers to their amplifiers so
that the original serial sequential string of video information may be
easily demutiplexed off-chip.
The CCD153A consists of the following functional elements illustrated in the Block Diagram and Circuit Diagram (Fig1.).
Gated Charge Detectors & Reset Gates: Each transport analog shift register delivers charge packets to a precharged diode. The
change in diode potential is linearly proportional to the amount of
charge delivered in the charge packet. This potential is applied to the
input gate of a MOS transistor amplifier (see below), which linearly
amplifies the input potential. The diode is reset to the reset drain
bias voltage (VRD) by the reset gate structure. Reset occurs when
both the internal reset clocks (φT on the “A: side, φT on the “B” side)
are “High.” Each side is reset just before the next charge packet is
delivered from its respective transport analog shift register.
Photosites: A row of 512 image sensor elements separated by a
diffused channel stop and covered by a silicon dioxide surface passivation layer. Image photons pass through the transparent silicon
creating hole-electron pairs. The photon generated electrons are
accumulated in the photosites. The amount of charge accumulated
in each photosite is a linear function of the incident illumination intensity and the integration period. The output signal will vary in an
analog manner from a thermally generated background level at zero
illumination to a maximum at saturation under bright illumination.
Photogate: The photogate structure, located at the edge of the
Output Amplifiers and Sample-and Hold Gates: Each sides’
photosites, provides a bias voltage for the photosites.
gated charge integrator drives the input of a two-stage linear MOStransistor amplifier. A schematic diagram of this circuit is shown in
Figure 9 below. The two stages of each amplifier are separated by
sample-and-hold gates. The output of the first stage is connected to
the input of the second stage whenever the sample-and-hold gates is
“High”. The output of the second stage is connected to the VIDEOOUT
pin. The sample-and-hold gates are switching MOS transistors: clocking these gates results in a sampled-and-held output, thus eliminating the reset clock feedthrough. When on-chip sample-and-hold is
used, pin 2 is to be tied to pin 3 and pin 21 is to be tied to pin 22. Offchip sample-and hold pulses can be supplied through pins 2 and 22.
The sample-and-hold operation can be disabled by tying pins 2 and
22 to VDD. Whenever on-chip sample-and hold is not used, pins 3
and 21 should be left unconnected.
Transfer Gate: The transfer gate structure separates the outer
edge of the photogates from the analog shift registers. Chargepackets generated and accumulated in the photosites are transferred
into the transport analog shift registers whenever the transfer gate
voltage goes “High”. All odd-numbered charge packets are transferred into the “A” transport analog shift register: all even-numbered
charge packets are transferred into the “B” transport analog shift
register. The transfer gate also controls the input of charge from VEI
into the white reference cells (described below). The time inteval
between successive transfer pulses determines the integration time.
Analog Shift Registers: Four 273-element analog shift registers transport charge towards the output end of the chip. the two
inner registers, the transport registers, move the image generated
charge packets serially to the two gated charge detectors and amplifiers. The two outer shift registers, the peripheral registers, accumulate charge generated at the chip periphery (by photons passing
through unavoidable gaps in the light shield layer, etc.) and transport it to charge sinks. The primary shift register clock is φT. The
complementary phase relationship of the secondary shift register
clocks φT and φT, generated on-chip, provide alternate delivery of
Clock Driver Circuits: Two MOSFET clock-driver circuits onchip allow sample-and-held operation of the CCD153A with only two
externally-supplied clocks: the square-wave primary shift register
transport clock φT, which determines the output data rate, and the
transfer clock φX, which determines the integration time.
Dark and White Reference Cells and Circuitry — At each
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
Saturation Exposure — The minimum exposure level that will
end of the 512-photosite array there are four additional sensing elements covered by opaque metallization. These “Dark Reference
Cells” provide four charge packets (two on each side) at each end of
the serial video output which indicate the typical dark (non-illuminated) signal level. In addition, two “white Reference Cells” (one per
side) are input into the serial video outputs after the last pixel (#512)
and the dark reference cells. (Refer to the section on the transfer
gate, above) Each white reference cell generates an output signal
pulse approximately 80% of the amplitude of a photosite saturation
(maximum) signal. These cells may be used as inputs to external
DC restoration and/or automatic gain control circuits. White reference amplitude is slightly dependent on exposure, especially at infrared wavelengths
provide a saturation output signal. Exposure is equal to the light
intensity times the photosites integration time.
Charge Transfer Efficiency — Percentage of valid charge information that is transferred between each successive stage of the
transport registers.
Responsivity — The output signal voltage per unit exposure for a
specified spectral type of radiation. Responsivity equals output voltage divided by exposure.
Total Photoresponse Non-uniformity — The difference of the
response levels of the most and the least sensitive element under
uniform illumination. Measurement of PRNU excludes first and last
Charge-Coupled Device — A Charge-coupled device is a semiconductor device in which finite isolated charge-packets are transported from one position in the semiconductor to an adjacent position by sequential clocking of an array of gates. The charge-packets
are minority carriers with respect to the semiconductor substrate.
Dark Signal — The output signal in the dark caused by thermally
generated electrons that is a linear function of the integration time
and highly sensitive to temperature. (See accompanying photos for
details of definition.)
Transfer Clock φX — The transfer clock is the voltage waveform
Saturation Output Voltage — The maximum usable signal out-
applied to the transfer gate to move the accumulated charge from
the image sensor elements to the CCD transport shift registers.
put voltage. Charge transfer efficiency decreases sharply when the
saturation output voltage is exceeded.
Transport Clock φT — The transport clock is the clock applied to
Integration Time — The time interval between the falling edge of
the gates of the CCD transport shift registers to move the chargepackets received from the image sensor elements to the gate chargedetector/amplifiers.
any two successive transfer pulses (φX). The integration is the time
allowed for the photosites to collect charge.
Pixel - A picture element (photosite).
Sample-and-Hold Clock (φSHCA, φSHCB) — The voltage waveform applied to the sample-and-hold gates in the output amplifiers
to create a continuous sampled video signal at the output. The
sample-and-hold feature may be defeated by connecting φSH(A+B)
to VDD.
Isolation Cell — A site on-chip producing an element in the video
output that serves as a buffer between valid video data and dark
reference signals. The output from an isolation cell contains no
valid information and should be ignored.
Dynamic Range — The saturation exposure divided by the rms
temporal noise equivalent exposure. Dynamic range is sometimes
defined in terms of peak-to-peak noise. To compare the two definitions a factor of four to six is generally appropriate in that peak-topeak noise is approximately equal to four to six times rms noise.
RMS Noise Equivalent Exposure — The exposure level that
gives an output signal to the rms noise level at the output in the
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
Glass may be cleaned by saturating a cotton swab in alcohol and
lightly wiping the surface. Rinse off the alcohol with deionized water. Allow the glass to dry, preferably by blowing with filtered dry N2
or air.
It is important to note in design and applications considerations that
the devices are very sensitive to thermal conditions. The dark signal dc and low frequency components approximately double for every 5º C temperature increase and single-pixel dark signal non-uniformities approximately double for every 8º C temperature increase.
The devices may be cooled to achieve very long integration times
and very low light level capability.
Order CCD153ADC where “D” stands for a ceramic package and
“C” for commercial temperature range.
Also available are printed circuit boards that include all the necessary clocks, logic drivers and video amplifiers to operate the
CCD153A. The boards are fully assembled and tested and require
only one power supply for operation (+20V). The printed circuit board
order codes are CCD153DB. The CCD153A,143A and 133A can
be operated in the same printed circuit board. The 24 pin CCD133A
and 153A devices are to be placed at the center of the 28 pin socket
on the printed circuit board.
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500