Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input. All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS. Features ■ Wide supply voltage range: ■ High noise immunity: 3.0V to 15V 0.45 VDD (typ.) ■ Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS ■ Low power: 50 nW (typ.) ■ Medium speed operation: 12 MHz (typ.) with 10V supply Ordering Code: Package Number Package Description CD4027BCM Order Number M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body CD4027BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Outputs tn (Note 2) Inputs tn−1 (Note 1) Pin Assignments for DIP and SOIC CL (Note 3) J K S R Q Q Q I X O O O I O X O O O I I O O X O O O O I X I O O I O X X O O X X X X I O X I X X X O I X O I X X X I I X I I I (No Change) O I = HIGH Level O = LOW Level X = Don't Care = LOW-to-HIGH = HIGH-to-LOW Top View Note 1: tn−1 refers to the time interval prior to the positive clock pulse transition Note 2: tn refers to the time intervals after the positive clock pulse transition Note 3: Level Change © 1999 Fairchild Semiconductor Corporation DS005958.prf www.fairchildsemi.com CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 CD4027BC Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 5) DC Supply Voltage (VDD) Input Voltage (VIN) −0.5 VDC to +18 VDC DC Supply Voltage (VDD) −0.5V to VDD +0.5 VDC −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW −40°C to +85°C Note 4: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. Lead Temperature (TL) (Soldering, 10 seconds) 0V to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3V to 15 VDC Input Voltage (VIN) Note 5: VSS = 0V unless otherwise specified. 260°C DC Electrical Characteristics (Note 6) Symbol IDD VOL VOH VIL Parameter Quiescent Device Current IOH IIN +25°C Max Min Typ +85°C Max Min Max Units VDD = 5V, VIN = VDD or VSS 4 4 30 µA VDD = 10V, VIN = VDD or VSS 8 8 60 µA VDD = 15V, VIN = VDD or VSS 16 16 120 µA |IO| < 1 µA Output Voltage VDD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V HIGH Level |IO| < 1 µA Output Voltage VDD = 5V 4.95 4.95 5 4.95 V VDD = 10V 9.95 9.95 10 9.95 V VDD = 15V 14.95 14.95 15 14.95 LOW Level HIGH Level Input Voltage IOL Min LOW Level Input Voltage VIH −40°C Conditions V VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 V VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0 V VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V V VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0 V VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA Current (Note 7) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA Current (Note 7) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA VDD = 15V, VO = 13.5V −3.6 Input Current −3.0 −8.8 −2.4 mA VDD = 15V, VIN = 0V −0.3 −10−5 −0.3 −1.0 µA VDD = 15V, VIN = 15V 0.3 10−5 0.3 1.0 µA Note 6: VSS = 0V unless otherwise specified. Note 7: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4027BC Absolute Maximum Ratings(Note 4) (Note 5) CD4027BC AC Electrical Characteristics (Note 8) TA = 25°C, CL = 50 pF, trCL = tfCL = 20 ns, unless otherwise specified Symbol tPHL or tPLH tPHL or tPLH Typ Max Units Propagation Delay Time Parameter VDD = 5V Conditions 200 400 ns from Clock to Q or Q VDD = 10V 80 160 ns VDD = 15V 65 130 ns VDD = 5V 170 340 ns ns Propagation Delay Time VDD = 10V 70 140 VDD = 15V 55 110 ns Propagation Delay Time VDD = 5V 110 220 ns from Set to Q or VDD = 10V 50 100 ns Reset to Q VDD = 15V 40 80 ns Minimum Data Setup Time VDD = 5V 135 270 ns VDD = 10V 55 110 ns VDD = 15V 45 90 ns VDD = 5V 100 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 from Set to Q or Reset to Q tPHL or tPLH tS tTHL or tTLH fCL Transition Time Maximum Clock Frequency tW tWH ns VDD = 5V 2.5 5 MHz VDD = 10V 6.2 12.5 MHz VDD = 15V 7.6 15.5 MHz Maximum Clock Rise VDD = 5V 15 µs and Fall Time VDD = 10V 10 µs VDD = 15V 5 (Toggle Mode) trCL or tfCL Min µs Minimum Clock Pulse VDD = 5V 100 200 ns Width (tWH = tWL) VDD = 10V 40 80 ns VDD = 15V 32 65 ns Minimum Set and VDD = 5V 80 160 ns Reset Pulse Width VDD = 10V 30 60 ns VDD = 15V 25 50 ns Any Input 5 7.5 pF Per Flip-Flop 35 CIN Average Input Capacitance CPD Power Dissipation Capacity pF (Note 9) Note 8: AC Parameters are guaranteed by DC correlated testing. Note 9: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application note, AN-90. Typical Applications Ripple Binary Counters Shift Registers www.fairchildsemi.com 4 CD4027BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A 5 www.fairchildsemi.com CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.